Slide Set 2A
for ENCM 501 in Winter Term, 2017
Steve Norman, PhD, PEng
Electrical & Computer Engineering
Schulich School of Engineering
University of Calgary
Winter Term, 2017
ENCM 501 W17 Lectures: Slide Set 2A
Contents
What is the purpose of this slide set?
Comparisons, branches and jumps
A loop to sum positive elements in an array
slide 2/11
ENCM 501 W17 Lectures: Slide Set 2A
Outline of Slide Set 2A
What is the purpose of this slide set?
Comparisons, branches and jumps
A loop to sum positive elements in an array
slide 3/11
ENCM 501 W17 Lectures: Slide Set 2A
slide 4/11
What is the purpose of this slide set?
There wasn’t time in the tutorial period of Wed Jan 18 to look
at slides 12–14 of that day’s slide set.
These slides three describe instructions for comparisons,
branches, and jumps, and present the problem of translating a
simple C while loop containing a simple if statement.
The solution to the problem uses many of the key instructions
in the MIPS64 ISA, which is the ISA used for most examples
in the course textbook.
Handling of branch and jump instructions is a very important
factor in processor performance, so it’s useful to look at the
MIPS instructions in a lecture.
ENCM 501 W17 Lectures: Slide Set 2A
Outline of Slide Set 2A
What is the purpose of this slide set?
Comparisons, branches and jumps
A loop to sum positive elements in an array
slide 5/11
ENCM 501 W17 Lectures: Slide Set 2A
slide 6/11
Comparisons, branches and jumps
Compare: dest gets 1 if src1 < src2 , and 0 otherwise . . .
SLT dest , src1 , src2
MIPS is unusual—the result does not go into a “condition
code register”. Note also that there are variations for unsigned
comparison and comparison of a GPR to a constant.
Branch: If GPR1 == GPR2 goto label . . .
BEQ GPR1 , GPR2 , label
There are variations. The most common is BNE: branch if not
equal.
Jump: Goto label . . .
J
label
ENCM 501 W17 Lectures: Slide Set 2A
Outline of Slide Set 2A
What is the purpose of this slide set?
Comparisons, branches and jumps
A loop to sum positive elements in an array
slide 7/11
ENCM 501 W17 Lectures: Slide Set 2A
A loop to sum positive elements in an array
Translate this fragment:
long int *p, *q; // R16, R17
long int sum;
// R18
sum = 0;
q = p + 100;
while (p != q) {
if (*p > 0)
sum += *p;
p++;
}
Repeat, changing the types of p and q to int *.
slide 8/11
slide 9/11
ENCM 501 W17 Lectures: Slide Set 2A
Below is a very straightforward translation of the C code.
A good C compiler with optimization turned on would produce
faster but less straightforward code.
L1:
L3:
L2:
OR
DADDIU
BEQ
NOP
LD
SLT
BEQ
NOP
DADDU
DADDIU
J
NOP
# [next
R18, R0, R0
R17, R16, 800
R16, R17, L2
# sum = 0
# q = p + 100
# if (p == q) goto L2
R8, 0(R16)
R9, R0, R8
R9, R0, L3
# R8 = *p
# R9 = 0 < *p
# if (!R9) goto L3
R18, R18, R8
R16, R16, 8
L1
# sum += *p
# p++
# goto L1
instruction after while loop]
ENCM 501 W17 Lectures: Slide Set 2A
slide 10/11
Remarks about the previous slide
Why the NOPs? In MIPS there is a delay slot following
every jump or branch. After a jump, the delay slot instruction
is executed before the jump target instruction is executed.
After a branch, the delay slot instruction gets executed
regardless of whether the branch is taken.
Okay, but why do delay slots exist? It made sense in the
1980’s—simple pipelining was feasible, but getting the
jump/branch target instruction started one clock cycle after a
jump/branch was not. It’s up to compiler writers to try to find
safe and useful work to do in delay slots. (Filling a delay slot
with a NOP is small waste of memory and time.)
ENCM 501 W17 Lectures: Slide Set 2A
slide 11/11
“Repeat, changing the types of p and q
to int *.”
I
I
I
Change 800 to 400 for q = p + 100
Change 8 to 4 for p++
Change LD to LW. Subtle detail: LW will sign-extend the
32-bit number it gets from memory to make an equivalent
64-bit number in the destination GPR, so the 64-bit SLT
that follows will “do the right thing”.
You will not be tested on the weird little detail about LW!