EE247
Lecture 12
• Administrative issues
ƒ Midterm exam Thurs. Oct. 23rd
o You can only bring one 8x11 paper with your
own written notes (please do not photocopy)
o No books, class notes or any other kind of
handouts/notes, calculators, computers, PDA,
cell phones....
o Midterm includes material covered to end of
lecture 14
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 1
EE247
Lecture 12
• Data converters
– Static converter error sources (continued)
•
•
•
•
Offset
Full-scale error
Differential non-linearity (DNL)
Integral non-linearity (INL)
– Measuring DNL & INL
• Servo-loop
• Code density testing (histogram testing)
– Dynamic tests
• Spectral testingÆ Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of
frequency
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 2
ADC Differential Nonlinearity
1. Endpoints
connected
2. Ideal characteristics
derived eliminating
offset & full-scale
error
3. DNL measured Æ
code width
deviation from
1LSB
EECS 247 Lecture 12:
8
7
Digital Output Code
DNL = deviation
of code width from
Δ (1LSB)
ADC Transfer Curve
Real
Ideal
-0.4 LSB DNL error
6
5
4
3
0 LSB DNL error
2
1
+0.4 LSB DNL error
0
0
1
2
3
4
5
6
7
8
ADC Input Voltage [Δ]
Data Converter Performance Metrics
© 2008 H. K. Page 3
ADC Differential Nonlinearity
• Ideal ADC transitions point equally spaced by 1LSB
• For DNL measurement, offset and full-scale error is
eliminated
• DNL [k] (a vector) measures the deviation of each
code from its ideal width
• Typically, the vector for the entire code is reported
• If only one DNL # is presented that would be the worst
case
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 4
ADC DNL
• DNL=-1 implies missing code
• For an ADC DNL < -1 not possible Æ undefined
• Can show:
al l i
∑
DN L[i ] = 0
• For a DAC DNL < -1 possible
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 5
DAC Differential Nonlinearity
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 6
DAC Differential Nonlinearity
• To find DNL for DAC
– Draw end-point line from 1st point to last
– Find ideal LSB size for the end-point corrected
curve
– Find segment sizes:
segment [m]=V[m]-V[m-1]
D N L[ m ] =
s e g m e n t[ m ] − V [ L S B ]
V [ LSB ]
• Unlike ADC DNL, for a DAC DNL can be <-1LSB
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 7
Impact of DNL on Performance
• Same as a somewhat larger
quantization error, consequently
degrades SQNR
• How much – later in the course...
• The term "DNL noise", usually means
"additional quantization noise due to
DNL"
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 8
ADC Integral Nonlinearity
End-Point
INL = deviation of code
transition from its ideal location
2. Ideal characteristics
derived eliminating offset
& full-scale error (same
as for DNL)
Digital Output Code
1. Endpoints connected
7
6
5
-1 LSB INL
4
3
2
1
3. INLÆ deviation of code
transition from ideal is
measured
EECS 247 Lecture 12:
0
-1
0
1
2
3
4
5
6
ADC Input Voltage [Δ]
Data Converter Performance Metrics
7
8
© 2008 H. K. Page 9
ADC Integral Nonlinearity
INL = deviation of code transition
from its ideal location
ADC Transfer Function
Output
INLMax
INL is also a vector INL[k]
If one INL # reported
ÆWorst case INL
Most commonÆ End-point:
Straight line through the endpoints is
usually used as reference,
i.e. offset and full scale errors are
eliminated in INL calculation
Real
Input
INL
Ideal converter steps found for the endpoint
line, then INL is measured
EECS 247 Lecture 12:
Ideal
Data Converter Performance Metrics
INLMax
INL Curve
Digital
Output
© 2008 H. K. Page 10
ADC Integral Nonlinearity
Best-Fit
Output
INL = deviation of code transition
from its ideal location
Real
Best-Fit
• A best-fit line (in the leastmean squared sense) fitted
to measured data
Ideal
Input
• Ideal converter steps found
then INL measured
ADC Transfer Function
INL
Note: Typically INL #s smaller for
best-fit compared to end-point
EECS 247 Lecture 12:
INL Curve
Data Converter Performance Metrics
© 2008 H. K. Page 11
ADC Integral Nonlinearity
Best Fit versus End-Point
+1/2 LSB INL
7
– A best-fit line (in the
least-mean squared
sense)
– Ideal converter steps is
found then INL is
measured
Digital Output Code
• Best-Fit
6
5
-1/2 LSB INL
Best Fit
4
3
2
1
End-point INLmax =1LSB
Best-fit INLmax =+-1/2LSB
0
-1
EECS 247 Lecture 12:
0
1
2
3
4
5
6
ADC Input Voltage [Δ]
Data Converter Performance Metrics
7
8
© 2008 H. K. Page 12
ADC Integral Nonlinearity
Can derive INL by:
1• Construct uniform staircase between 1st and last transition
• INL for each code:
IN L[ m] =
T [ m] − T [i deal ]
2• Can show
IN L[ m] =
W [i deal ]
m −1
∑
i =1
DN L[i ]
Æ INL is found by computing the cumulative sum of DNL
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 13
ADC Differential & Integral Nonlinearity
Example
IN L[ m] =
m −1
∑
i =1
DN L[i ]
Notice:
INL[0] Æ undefined
INL[1]=0
INL[2N-1]=0
EECS 247 Lecture 12:
Code #
DNL
[LSB]
INL [LSB]
0
-
-
1
0.18
0
2
-0.55
0.18
3
0.55
-0.37
4
-0.55
0.18
5
-0.27
-0.37
6
0.64
-0.64
7
-
0
Data Converter Performance Metrics
© 2008 H. K. Page 14
ADC Differential & Integral Nonlinearity
Example
Max.
DNL
1
DNL [LSB]
INL
[LSB]
0
-
-
1
0.18
0
2
-0.55
0.18
3
0.55
-0.37
0.5
4
-0.55
0.18
0
5
-0.27
-0.37
6
0.64
-0.64
-
0
0
-0.5
-1
1
INL [LSB]
DNL
[LSB]
Code
#
0.5
0
1
2
3
4
-0.5
-1
0
1
2
3
Code #
EECS 247 Lecture 12:
4
5
Max.
INL
5
6
6
7
7 7
Data Converter Performance Metrics
© 2008 H. K. Page 15
DAC Integral Nonlinearity
Can derive INL by:
• Connect end points
• Find ideal output values
• INL for each code:
INL[ m] =
V [ m] − V [i dea l ]
2• Can show
IN L[ m] =
V [ LSB]
m −1
∑
i =1
DN L[i ]
Æ INL is found by computing the cumulative sum of DNL
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 16
DAC Integral Nonlinearity
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 17
DAC DNL and INL
* Ref: “Understanding Data Converters,” Texas Instruments Application Report
SLAA013, Mixed-Signal Products, 1995.
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 18
Example: INL & DNL
Large INL & Small DNL
Smooth variations in transfer
curve Æ Small DNL
EECS 247 Lecture 12:
Large DNL & Small INL
Abrupt variations in transfer
curve Æ Large DNL
Data Converter Performance Metrics
© 2008 H. K. Page 19
Monotonicity
•
Monotonicity guaranteed if
| INL | ≤ 0.5 LSB
The best fit straight line is taken as the reference for determining the INL.
•
This implies
| DNL | ≤ 1 LSB
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 20
Non-Monotonic DAC
DN L[ m] =
Analog
Output [LSB]
s eg ment[ m] − V [ L SB ]
V [ LSB]
7
s eg ment[ 4 ] − V [ L SB ]
6
DN L[ 4 ] =
V [ LSB]
− 0. 5 − 1
=
= − 1 . 5[ L S B ]
1
2. 5 − 1
DN L[ 5] ==
= 1.5[ L SB ]
1
5
4
-0.5
2
• DNL< -1LSB for a DAC
Æ Non-monotonicity
1
• When can non-monotonicity
cause major problems?
EECS 247 Lecture 12:
2.5
3
Digital
Input
0
000 001 010 011 100 101 110 111
Data Converter Performance Metrics
© 2008 H. K. Page 21
Non-Monotonic ADC
• Code 011
associated with two
transition levels !
• For non-monotonic
ADC
ÆDNL not
defined @ nonmonotonic
steps
Digital Output
111
110
101
100
011
010
001
Analog
input
000
0
EECS 247 Lecture 12:
Δ
2Δ
Data Converter Performance Metrics
3Δ 4Δ 5Δ
6Δ
7Δ
© 2008 H. K. Page 22
How to measure DNL/INL?
• DAC:
– Simply apply digital codes and use a good voltmeter to
measure corresponding analog output
• ADC
– Not as simple as DACÆ need to find "decision levels", i.e.
input voltages at all code boundaries
• One way: Adjust voltage source to find exact code trip
points "code boundary servo"
• More versatile: Histogram testing
ÆApply a signal with known amplitude distribution and
analyze digital code distribution at ADC output
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 23
Code Boundary Servo
Input
Digital
Code
i1
A
C1
Digital
Comp.
B
VREF fS
A<B
R2
ADC
Input
A≥B
ADC
Under
Test
C2
i2
ADC
Output
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 24
• i1 and i2 are small, and
C1 is large, so the
ADC analog input
moves a small fraction
of an LSB each
sampling period
• For a code input of
101, the ADC analog
input settles to the
code boundary shown
ADC Digital Output
Code Boundary Servo
111
110
101
100
011
010
001
000
Δ
2Δ
3Δ
4Δ 5Δ
6Δ
7Δ
ADC Analog Input
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 25
Code Boundary Servo
Input
Digital
Code
i1
A
Good DVM
C1
Digital
Comp.
B
VREF fS
A<B
R2
ADC
A≥B
C2
i2
ADC
Output
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 26
Code Boundary Servo
• A very good digital voltmeter (DVM)
measures the analog input voltage
corresponding to the desired code boundary
• DVMs have some interesting properties
– They can have very high resolutions (8½ decimal
digit meters are inexpensive)
– To achieve stable readings, DVMs average
voltage measurements over multiple 60Hz ac line
cycles to filter out pickup in the measurement loop
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 27
Code Boundary Servo
• ADCs of all kinds are
notorious for kicking
back high-frequency,
signal-dependent
glitches to their analog
inputs
Good DVM
VREF
R2
• A magnified view of an
analog input glitch
follows …
EECS 247 Lecture 12:
Data Converter Performance Metrics
fS
ADC
C2
© 2008 H. K. Page 28
• Just before the input is
sampled and
conversion starts, the
analog input is pretty
quiet
• As the converter begins
to quantize the signal, it
kicks back charge
EECS 247 Lecture 12:
analog input
Code Boundary Servo
start of conversion
0
Data Converter Performance Metrics
1/fS
time
© 2008 H. K. Page 29
Code Boundary Servo
• How do we control this
error?
EECS 247 Lecture 12:
DVM measures the average
input including the glitch
analog input
• The difference between
what the ADC
measures and what the
DVM measures is not
ADC INL, it’s error in
the INL measurement
ADC converts this voltage
0
Data Converter Performance Metrics
time
1/fS
© 2008 H. K. Page 30
Code Boundary Servo
• A large C2 fixes this
Good DVM
• At the expense of longer
measurement time
VREF
R2
fS
ADC
C2
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 31
Histogram Testing
• Code boundary measurements are slow
– Long testing time
• Histogram testing
– Quantize input with known pdf (e.g. ramp or
sinusoid)
– Measure output pdf
– Derive INL and DNL from deviation of measured
pdf from expected result
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 32
Histogram Test Setup
VREF
fS
Ramp VREF
ADC
0
PC
Time
• Slow (wrt conversion time) linear ramp applied to ADC
• DNL derived directly from total number of occurrences of each
code @ the output of the ADC
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 33
A/D Histogram Test Using Ramp Signal
Digital Output
Example:
ADC
Input/Output
ADC sampling rate:
fs =100kHz Æ Ts=10μsec
1LSB =10mV
For 0.01LSB measurement
resolution:
Æn =100 samples/code
Æ Ramp duration per code:
=100x10μsec=1msec
Analog
input
n/fs
Ramp
Æ Ramp slope: 10mV/msec
Time
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 34
Digital Output
A/D Histogram Test Using Ramp Signal
Example:
Ramp slope: 10mV/msec
1LSB =10mV
Each ADC codeÆ1msec
ADC
Input/Output
Analog
input
fs =100kHz Æ Ts=10μsec
n/fs
Ramp
# of
Samples
Per code Time
Æn =100 samples/code
EECS 247 Lecture 12:
Digital
Output
Data Converter Performance Metrics
© 2008 H. K. Page 35
Ramp Histogram
Example: Ideal 3-Bit ADC
7
200
ADC characteristics
ideal converter
180
160
Code Count
Digital Output Code
6
5
4
3
140
120
100
80
2
60
1
40
0
20
0
1
2
3
4
5
6
ADC Input Voltage [Δ]
EECS 247 Lecture 12:
7
8
0
0
Data Converter Performance Metrics
1
2
3
4
5
6
7
ADC output code
© 2008 H. K. Page 36
Ramp Histogram
Example: Real 3-Bit ADC Including Non-Idealities
7
180
160
6
-0.4 LSB DNL
140
5
Code Count
Digital Output Code
200
ADC characteristics
ideal converter
120
4
100
3
+0.4 LSB INL
2
80
60
1
40
+0.4 LSB DNL
20
0
0
1
2
3
4
5
6
ADC Input Voltage [Δ]
EECS 247 Lecture 12:
7
0
8
0
1
2
3
4
5
6
7
ADC output code
Data Converter Performance Metrics
© 2008 H. K. Page 37
Example: 3 Bit ADC
1- Remove “Over-range bins”
(0 and full-scale)
2- Compute average count/bin
(600/6=100 in this case)
Code Count, End bins removed
DNL Extracted from Histogram
140
120
100
80
60
40
20
0
0
1
2
3
4
5
6
7
ADC output code
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 38
Example: 3 Bit ADC
Process of Extracting from Histogram
3- Normalize:
Divide histogram by
average count/bin
Æ ideal bins have exactly the
average count, which, after
normalization, would be 1
Æ Non-ideal bins would have
a normalized value greater of
smaller than 1
Normalized Code Count
-
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
ADC output code
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 39
4- Subtract 1 from the
normalized code count
5- Result Æ DNL (+-0.4Lsb
in this case)
DNL = Counts / Mean(Counts) -1
Example: 3 Bit ADC
DNL Extracted from Histogram
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
1
2
3
4
5
6
7
ADC output code
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 40
Example: 3-Bit ADC
Static Characteristics Extracted from Histogram
• Width of all codes derived from
measured DNL (Code=DNL +
1LSB)
Reconstructed ADC
Transfer Characteristic
7
6
Digital Output
• DNL histogram Æ used to
reconstruct the exact converter
characteristic (having measured
only the histogram)
• INLÆ(deviation from a straight
line through the end points)- is
found
5
4
3
2
1
0
0
1
2
3
4
5
6
7
ADC Input Voltage
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 41
Example: 3 Bit ADC
DNL & INL Extracted from Histogram
ADC characteristics
Ideal converter
DNL [LSB]
1
0.5
6
-0.4 LSB DNL
0
-0.5
5
-1
4
3
+0.4 LSB INL
1
2
3
4
5
6
3
4
5
6
1
INL [LSB]
Digital Output Code
7
0.5
2
1
+0.4 LSB DNL
0
-0.5
0
0
1
2
3
4
5
ADC Input Voltage [Δ]
EECS 247 Lecture 12:
6
7
-1
1
Data Converter Performance Metrics
2
Digital Output Code
© 2008 H. K. Page 42
Measuring DNL
• Ramp speed is adjusted to provide large number of
output/code - e.g. an average of 100 outputs of each
ADC code (for 1/100 LSB resolution)
• Ramp test can be quite slow for high resolution ADCs
• Example:
16bit ADC & 100conversions/code @100kHz
sampling rate
(216or 65,536 codes)(100 conversions/code)
100,000 conversions/sec
EECS 247 Lecture 12:
Data Converter Performance Metrics
= 65.6 sec
© 2008 H. K. Page 43
ADC Histogram Testing
Sinusoidal Inputs
• Solution:
ÆUse sinusoidal test
signal (may need to filter
out harmonics)
• Problem: Ideal ADC
histogram not flat but has
“bath-tub shape”
EECS 247 Lecture 12:
ADC Output- Raw Histogram
Code Count
• Ramp signal generators
linear to only 8 to10bits
Æ Need to find input signal
with better purity
1000
500
0
Data Converter Performance Metrics
1000
2000
3000
4000
ADC output code
© 2008 H. K. Page 44
At sinusoid midpoint crossings:
dv/dt Æ max.
Æ least # of samples
Digital Output
ADC Histogram Test Using Sinusoidal Signals
ADC
Input/Output
Analog
input
# of
Samples
Per code Time
At sinusoid amplitude peaks:
dv/dt Æ min.
Æ highest # of samples
EECS 247 Lecture 12:
Data Converter Performance Metrics
Sinusoid
Digital
Output
© 2008 H. K. Page 45
Histogram Testing
Correction for Sinusoidal PDF
• References:
– [1] M. V. Bossche, J. Schoukens, and J. Renneboog,
“Dynamic Testing and Diagnostics of A/D Converters,” IEEE
Transactions on Circuits and Systems, vol. CAS-33, no. 8,
Aug. 1986.
– [2] IEEE Standard 1057
• Is it necessary to know the exact amplitude and offset
of sinusoidal input? No!
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 46
DNL/INL Extraction Matlab Program
function [dnl,inl] = dnl_inl_sin(y);
%DNL_INL_SIN
% dnl and inl ADC output
% input y contains the ADC output
% vector obtained from quantizing a
% sinusoid
T = -cos(pi*ch/sum(h));
% linearized histogram
hlin = T(2:end) - T(1:end-1);
% truncate at least first and last
% bin, more if input did not clip ADC
trunc=2;
hlin_trunc = hlin(1+trunc:end-trunc);
% Boris Murmann, Aug 2002
% Bernhard Boser, Sept 2002
% histogram boundaries
minbin=min(y);
maxbin=max(y);
% calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
dnl= [0 hlin_trunc/lsb-1];
misscodes = length(find(dnl<-0.99));
% histogram
h = hist(y, minbin:maxbin);
% cumulative histogram
ch = cumsum(h);
EECS 247 Lecture 12:
% transition levels found by:
% calculate inl
inl= cumsum(dnl);
Data Converter Performance Metrics
© 2008 H. K. Page 47
Example: Test Results for DNL & INL
Using Sinusoidal Histogram
DNL [LSB]
DNL = +1.3 / -1 LSB, missing code if (DNL<-0.99)
1
0
-1
0
500
1000
2000
code
2500
3000
3500
4000
3000
3500
4000
INL = +1.7 / -0.69 LSB
2
INL [LSB]
1500
1
0
-1
0
EECS 247 Lecture 12:
500
1000
1500
2000
code
2500
Data Converter Performance Metrics
© 2008 H. K. Page 48
Example: Matlab ADC Model
DNL/INL Code Test
hist(y, min(y):max(y));
0.5
0
-0.5
-1
fs = 1e6;
fx = 494e3 + pi;
% try fs/10!
C = round(100 * 2^B / (fs / fx));
-30
-20
0
10
20
30
20
30
0.4
0
-30
-20
-10
0
10
Digital Output
dnl_inl_sin(y);
EECS 247 Lecture 12:
-10
INL = +0.7 LSB
0.8
INL [LSB]
t = 0:1/fs:C/fx;
x = (range+1) * sin(2*pi*fx.*t);
y = adc(x, th) - 2^(B-1);
DNL = +0.7 / -0.7 LSB
1
DNL [LSB]
% converter model
B = 6;
% bits
range = 2^(B-1) - 1;
% thresholds (ideal converter)
th = -range:range; % ideal thresholds
th(20) = th(20)+0.7; % error
Data Converter Performance Metrics
© 2008 H. K. Page 49
Histogram Testing Limitations
•
•
•
•
The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.
Histogram testing assumes monotonicity
E.g. “code flips” will not be detected.
Dynamic sparkle codes produce only minor DNL/INL errors
E.g. 123, 123, …, 123, 0, 124, 124, … Æ look at ADC output to
detect
Noise not detected & averaged out
E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution
ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 50
Example: Hiding Problems in the Noise
• INL Æ 5
missing codes
• DNL "smeared
out" by noise!
• Always look at
both DNL/INL
• INL usually
does not lie...
EECS 247 Lecture 12:
[Source: David Robertson, Analog Devices]
Data Converter Performance Metrics
© 2008 H. K. Page 51
Why Additional Tests/Metrics?
• Static testing does not tell the full story
– E.g. no info about "noise“ or high frequency effects
• Frequency dependence (fs and fin) ?
– In principle we can vary fs and fin when performing
histogram tests
– Result of such sweeps is usually not very useful
– Hard to separate error sources, ambiguity
– Typically we use fs=fsNOM and fin << fs/2 for
histogram tests
• For additional infoÆ Spectral testing
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 52
DAC Spectural Test or Simulation
Digital
Sinusoid
Signal
Generator
Device Under Test
(DUT)
DAC
Vout
Spectrum
Analyzer
Clock
Generator
• Input sinusoid Æ Need to have significantly better purity compared to DAC
linearity
• Spectrum analyzer need to have better linearity than DUT
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 53
Direct ADC Spectral Test via DAC
Device Under Test (DUT)
Vin
Signal
Generator
ADC
DAC
Vout
Spectrum
Analyzer
Clock
Generator
• Need DAC with much better performance compared to ADC
under test
• Beware of DAC output sinx/x frequency shaping
• Good way to "get started"...
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 54
ADC Spectral Test via
Data Acquisition Sytem
Device Under Test
(DUT)
Vin
Signal
Generator
ADC
Data
Acquisition
System
PC
Clock
Generator
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 55
Analyzing ADC Outputs via
Discrete Fourier Transform (DFT)
x(t)
⇒
x(k)
• Sinusoidal waveform has all its power at one single frequency
• An ideal, infinite resolution ADC would preserve ideal, single tone
spectrum
• DFT used as a vehicle to reveal ADC deviations from ideality
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 56
Discrete Fourier Transform
The DFT of a block of N time samples
{x(k)} = {x(0), x(1), x(2),…,x(N-1)}
yields a set of N frequency bins
{Am} = {A0,A1,A2,…,AN-1}
where:
N-1
Am =
Σx
mn
n WN
m = 0,1,2,…,N-1
n=0
WN ≡ e
EECS 247 Lecture 12:
-j2π/N
Data Converter Performance Metrics
© 2008 H. K. Page 57
Discrete Fourier Transform (DFT)
Properties
• DFT of N samples spaced Ts=1/fs seconds:
– N frequency bins from DC to fs
– Bin m represents frequencies at m * fs /N [Hz]
• DFT frequency resolution:
– Proportional to fs /N in [Hz/bin]
• DFT with N = 2k ( k is an integer) can be found using a
computationally more efficient algorithm named:
– FFT Æ Fast Fourier Transform
EECS 247 Lecture 12:
Data Converter Performance Metrics
© 2008 H. K. Page 58
DFT Magnitude Plots
•
Because magnitudes of DFT bins (Am) are symmetric around fS /2, it is
redundant to plot ⏐Am⏐’s for m >N/2
0
•
fs/2
fs
Usually magnitudes are plotted on a log scale normalized so that a
full scale sinusoidal waveform with rms value aFS yields a peak bin of
0dBFS:
⏐Am⏐
⏐Am⏐ [dBFS] = 20 log10
EECS 247 Lecture 12:
aFS .N/2
Data Converter Performance Metrics
© 2008 H. K. Page 59
Matlab Example
Normalized DFT
1
%
t
%
y
%
s
%
s
%
f
1e6;
50e3;
1;
100;
Amplitude
=
=
=
=
time vector
= linspace(0, (N-1)/fs, N);
input signal
= Afs * cos(2*pi*fx*t);
spectrum
= 20 * log10(abs(dft(y)/N/Afs*2));
drop redundant half
= s(1:N/2);
frequency vector (normalized to fs)
= (0:length(s)-1) / N;
EECS 247 Lecture 12:
0.5
0
-0.5
-1
Magnitude [ dBFS ]
fs
fx
Afs
N
0
0.2
0.4
0.6
0.8
0.3
0.4
Time
1
-4
x 10
0
-100
-200
-300
0
fx /fs
Data Converter Performance Metrics
0.1
0.2
0.5
Frequency [ f / fs]
© 2008 H. K. Page 60