10/12/2016
FSM Outputs May or May Not Depend Directly on Inputs
University of Illinois at Urbana-Champaign
Dept. of Electrical and Computer Engineering
As mentioned previously, for our class,
FSM outputs depend only on state,
not on FSM inputs.
ECE 120: Introduction to Computing
Historically, such an FSM was called
a Moore machine.
The more general model,
◦ in which outputs may also depend on inputs,
◦ was called a Mealy machine.
Machine Models
ECE 120: Introduction to Computing
© 2016 Steven S. Lumetta. All rights reserved.
slide 1
ECE 120: Introduction to Computing
© 2016 Steven S. Lumetta. All rights reserved.
More General Model Always Used in Practice
Inputs May Allow Us to Design a Smaller FSM
In practice,
◦ designers always use Mealy machines,
◦ so FSM outputs may depend
directly on inputs.
Why use the general model?
slide 2
Inputs carry information.
We can sometimes build a smaller FSM
if we make use of that information.
If a designer wants
◦ an output to be independent of inputs,
◦ the designer simply designs the FSM
to meet that requirement.
So the names are just of historical interest.
ECE 120: Introduction to Computing
© 2016 Steven S. Lumetta. All rights reserved.
slide 3
ECE 120: Introduction to Computing
© 2016 Steven S. Lumetta. All rights reserved.
slide 4
10/12/2016
More General Model Can Introduce Timing Issues
An Example Illustrates the Tradeoffs
Why do we use the simpler model in ECE120?
Let’s use an example to illustrate these
tradeoffs.
If outputs depend directly on inputs,
Say that we want to recognize the
sequence 01 in a serial input B.
output timing also depends on input timing,
so we lose the benefit of treating time as a
discrete value (an integer).
ECE 120: Introduction to Computing
Whenever B is 0 in one cycle and 1 in the
next cycle, we set the output Z equal to 1.
© 2016 Steven S. Lumetta. All rights reserved.
slide 5
ECE 120: Introduction to Computing
© 2016 Steven S. Lumetta. All rights reserved.
slide 6
Mealy Machine for 01 Sequence Recognizer
Transition Diagrams Look Different for Mealy Machines
Consider the
design to the
right.
Now let’s draw
the state diagram.
IN
D
Q
S0
Q
What is the next-state equation (
= IN
And the output equation?
OUT
Q
S0
Q
OUT
Outputs depend on inputs, so
◦ states cannot be labeled with outputs.
◦ Instead, transitions are labeled with
1/1
outputs.
= ?)?
Current IN is 1.
0/0
Last IN was 0.
© 2016 Steven S. Lumetta. All rights reserved.
D
We have two states.
OUT = IN · S0’
ECE 120: Introduction to Computing
IN
slide 7
ECE 120: Introduction to Computing
0
1
0/0
1/0
© 2016 Steven S. Lumetta. All rights reserved.
slide 8
10/12/2016
A Timing Diagram Reveals the Timing Issues
We Can Usually Ignore the Narrow Output Problem
Recall that
OUT = IN · S0’
Usually, narrow output pulses don’t matter.
IN
D
Q
S0
Q
If inputs
◦ come from flip-flops on the same clock,
◦ changes arrive early enough
(but may limit clock speed).
OUT
S0 is 0 after this edge.
We may have problems if inputs are
external or if outputs are used
externally (not on the same clock).
OUT pulse width
depends on
input timing .
ECE 120: Introduction to Computing
slide 9
ECE 120: Introduction to Computing
© 2016 Steven S. Lumetta. All rights reserved.
slide 10
How Can We Fix the Narrow Pulse Problem?
The New Flip-Flop Splits One State into Two
What if we need a
wider output pulse?
IN
The new
flip-flop splits
the “1” state
into “11” and
“01” states.
IN
D
Q
S0
Q
OUT
Do we have to redesign the system
entirely? (as a Moore machine)
IN
No! Just add
another flipflop.
ECE 120: Introduction to Computing
D
0
Q
S0
Q
D
Q
Note: the 01 state
is not reachable
from other states.
OUT
S1
Q
slide 11
ECE 120: Introduction to Computing
D
Q
S0
Q
D
Q
OUT
S1
Q
1
00/0
11/1
1
0
0
01/0
1
© 2016 Steven S. Lumetta. All rights reserved.
slide 12
10/12/2016
Summary of the Two Models
OUT is Delayed but High for a Full Cycle with Moore
IN
D
Moore: outputs depend only on state, not on
inputs
Q
S0
Q
D
Q
OUT
Mealy: outputs can also depend on inputs
S1
S0 is 0 after this edge.
Q
Mealy is used in practice.
◦ Can reduce size of design, but
◦ may create thin output pulses.
OUT is high
for a full
clock cycle.
Solving these problems is easy:
add flip-flops to make a Moore design.
(OUT=1 delayed to rising edge.)
ECE 120: Introduction to Computing
slide 13
ECE 120: Introduction to Computing
© 2016 Steven S. Lumetta. All rights reserved.
slide 14