258
IEEE TRANSACTIONS ON COMPUTERS, VOL.
[8] K. M. Chandy, C. V. Ramamoorthy, and A. Cowan, "A framework for
hardware-software tradeoffs in the design of fault-tolerant computers," in Proc.
Fall Joint Comput. Confi AFIPS, pp. 55-63, 1972.
[9] J. Losq, "A highly efficient redundancy scheme: Self-purging redundancy,"
IEEE Trans. Comput., vol. C-25, pp. 569-578, June 1976.
[10] -, "Redundancy scheme for optimum multiple fault tolerance," Stanford
Univ. Digital Syst. Lab. Tech. Note 33, Jan. 1974.
[11] S. Y. H. Su and E. DuCasse, "A reconfiguration scheme for tolerating multiple
failures in digital systems," in Proc. 1975 Int. Computer Symp., vol. II, pp.
216-222, Taipei, Taiwan.
c-29, NO. 3, MARCH 1980
subtracting the squared difference from the squared sum as shown
in (1). The product is then one quarter of the resultant
difference-thus the name quarter square. This is similar to the
technique suggested by Logan [4] who proposed that digital multiplication be performed by accumulating squares via the Binomial Theorem:
AB = o{(A + B)2 - A2
-
B2}.
(2)
Equation (2) requires one more squaring device than (1). Logan
proposed an LSI squaring device which would be used to perform
the indicated squares in (2). A value of 10 input bits was placed as
the upper limit on feasible LSI squaring circuits (1971 Technology). For squares involving more than 10 bits Logan proposed a
double precision algorithm using (2) as a base.
For the digital quarter square (DQS) multiply scheme
proposed in this correspondence memory sizes of 2N+'1 x 2N will
be required for products of N bit words. Values of N up to 16 may
be accommodated with current LSI memories and even larger
A Digital Quarter Square Multiplier
word length products should be possible with VLSI without resorting to double precision techniques.
EVERETT L. JOHNSON
Fig. 1 shows the block diagram of a single ROM implementaAbstract-An application of the quarter square multiplication tion of a product circuit. For the product of two N-bit words,
technique used in analog computing is proposed for digital multipli- 2`2N-bit words are required to store the complete product table.
cation. Significant savings in storage requirements for ROMIn the following discussion, it is assumed that x and y are
implemented product tables are demonstrated. A two's complement positive and that x > y. Fig. 2 shows the basic block diagram of
multiplication circuit utilizing the digital quarter square technique is
the DQS multiplier. The sum of x and y may result in a value of
presented.
N + 1 bits. The difference will always be representable by N bits.
Index Terms-Absolute value circuit, digital quarter square multi- ROM 1 contains (x + y)2/4 and ROM 2 contains the two's complication, high-speed digital multiplication, ROM product tables.
plement of (x _ y)2/4.
Fig. 3 shows the symbolic square of a 4 bit quantity A. Note
INTRODUCTION
that the least significant two bits of the squared quantity have
Large-scale integrated (LSI) circuit technology has permitted possible values of 00 or 01. The division by 4 which is required by
the development of iterative circuit solutions to the design of the DQS algorithm is accomplished by not storing the two least
high-speed multipliers [1], [2]. A survey of current high-speed significant bits of each of the squared quantities. No loss of
multipliers and the theory of their operation has been presented significance in the resultant product is incurred.
by Waser [3]. In this correspondence a suggestion for an alternative
Comparison of the storage requirements of the two techniques
approach will be presented. This alternate approach involves a demonstrates the significant reduction in storage requirement in
variation of the straightforward application of ROM look-up the digital quarter square multiplier. The ratio of the single ROM
tables for obtaining the product of two binary numbers.
requirement to the DQS bit requirement is
The multiplier and multiplicand form the address which points
22N x 2N
Single ROM Bits
to the memory location containing their product. The amount of
x
2N+1 2N+2N X (2N-2)
DQS Bits
storage required in an ROM implemented multiplier increases as
2M where M is the sum of the number of bits in the multiplicand
2N
and multiplier. The large amount of storage required is due to the
(3)
redundancy in the products stored, i.e., the product 6 would be
3- 1
N
stored in four different locations as the result of 2 x 3, 3 x 2,
1 x 6, and 6 x 1. It will be demonstrated in the following sections
2N
for large N.
that a significant reduction in the storage requirements can be
realized by utilizing ROM's and an analog computer multiplicaFor an 8 bit multiplier the single ROM technique requires 64k
tion technique called quarter square multiplication.
of 16 bit words, the DQS technique requires 512 sixteen bit words
QUARTER SQUARE MULTIPLICATION
and 256 fourteen bit words. Certainly the DQS technique makes
The quarter square multiplication technique is easily ROM implemented multipliers for short word length economically feasible. However, there is a slight reduction in the speed
demonstrated algebraically as
of the DQS technique compared to the single ROM caused by the
Xy
(X
y)2}.
(1)
f{(X + y)2
addition required before and after accessing the ROM's.
It involves generating the sum and difference of two numbers and
TwO's COMPLEMENT MULTIPLICATION
Fig. 4 shows the block diagram of a DQS configuration which
Manuscript received January 10, 1979; revised September 18, 1979.
allows
multiplication of two's complement numbers. All restricState
The author is with the Department of Electrical Engineering, Wichita
tions of the previous section are removed on the sign and relative
University, Wichita, KS 67208.
1
=
_
_
0018-9340/80/0300-0258$00.75 © 1980 IEEE
IEEE TRANSACTIONS ON COMPUTERS, VOL.
c-29, NO. 3,
MARCH 1980
XB
(N BITS)
259
2
X 2N
(BITS)
I
(I2N
ROM
XY
BITS)
(N BITS )
Fig. 1. Single ROM multiplier.
(N
(N
XY
N BITS)
Fig. 2. Digital quarter square multiplier.
magnitudes of x and y. In order to allow multiplication of two's Po
complement numbers, an absolute value circuit (discussed in the p1
next section) is used to give the absolute values of the sum and
difference of x and y. The ROM containing the values of 2
(x - y)2/4 has been enlarged over the one in Fig. 2 since the P3
difference of x and y may be N + I bits long if x and y are of p4
different signs. The sign bit of (x + y)2/4 is always 0 and that of
- (x - y)2/4 is always 1. Note that the sign bit is not stored but is
5
used in the final summation.
P6
Assuming a single ROM multiplier is implemented for two's P7
complement multiplication by using external circuitry to handle
the sign bit, the ratio of bits required for the single ROM to that cn
for the DQS multiplier is
22N x 2N
Single ROM Bits
(4)
DQS Bits
2 X 2N+1 x 2N 2
For an 8 bit multiplier, 64 times as many bits are required for
the single ROM multiplier. For a 16 bit multiplier 16 384 times
more bits are required for the single ROM multiplier than for the
DQS multiplier.
ABSOLUTE VALUE CIRCUIT
Fig. 5 shows the truth table and circuit for a single stage of the
absolute value circuit. A is the quantity for which the absolute
value is desired, SB is the sign bit of A, C", I is the carry from the
previous stage and S is the absolute value of A. Equation (5) gives
the output for the nth bit and (6) is the carry relation:
=A
=
=
A3 A2A1A
0
A1A0
A2AO
= A2A1
3A1
= A3A2
= C6
A3A2A1A0
+
+
+
Al
C2
A3AO
A3A0
+ A2 + C3
A3A2
+ C4
+ A3 + C5
A2A0 AlAo AO
A3A1 A2A1
A1
A2 A2A1
A2AO
AlAo
A3 A3A2 A3A1 A3Ao
P7 P6 P5
P4
P3
P2
p1
- Carriies from previous
coluinmn summation
Fig. 3. Symbolic square of a digital quantity.
Sn = An (E SB 3 Cn-1
Cn = An.' Cn- 1.
(5)
(6)
The circuit in Fig. 5 can be ganged to form an N bit absolute
value circuit. The least significant carry in is the sign bit of A, SB.
For increased speed a two-gate delay absolute value circuit can be
implemented by eliminating the time required for carry propagation. The carry value needed at each stage n can be determined
from (6) as
Cn - = An-l * An - 2 *---- Al AO * SB.
(7)
P0
260
IEEE TRANSACTIONS ON COMPUTERS, VOL.
C-29, NO. 3, MARCH 1980
Fig. 4. Two's complement DQS multiplier.
An
O
0
0
1
1
1
1
-
SB
0
1
1
0
0
1
1
Cn-1
1
0
1
0
1
0
1
Sn Cn
'*
::::::"
*
0 0
1
0
1
0
1
0
0 0
1 0
*-0-*0
000**
0-0 000
00*0 00
*0* 00
**0000
DON'T CARE
SUM COLUMNS FOR PRODUCT
}24
I
BIT WORDS
36 4 BIT
MULTIPLICATION'
Fig. 6. 24 bit multiplication using 4 bit partial products.
Don
An
SB
Cn-1
Fig. 5. Truth table and circuit for bit
3
* * *
* *
24 BIT WORDS
NINE 8 BIT
J MULTIPLICATIONS
SUM COLUMNS FOR PRODUCT
n
of absolute value circuit.
PARTIAL PRODUCT MULTIPLIER
Stenzal et al. [5] described a technique of forming m bit partial
products in an N bit multiplication. The results of the m bit products were then summed using (c, d) counters [1] where c is the
number of input bits and d is the number of bits in the sum. An
example was given of a 24 bit multiplier using thirty-six 256 x 8
ROM's to form the 4 bit partial products. Each dot in Fig. 6 in the
columns to be summed represents the result of each 4 bit multiplication. Completion of the multiplication requires the summation
of the columns using (c, d) counters. Using the same partial product scheme but using DQS 'multipliers for the partial products
requires seventy-two 32 x 8 ROM's giving a factor of 4 savings in
the ROM bit requirements, but a decrease in multiplier speed
equal to the delay through the two addition and absolute value
circuits.
Another option which would require only twice the number of
ROM bits as the Stenzal 4 bit partial product example, but would
give a faster multiplier, would be to use 8 bit DQS partial products. Fig. 7 shows the resultant partial products which would
Fig. 7. 24 bit multiplication using 8 bit partial products.
have to be summed to complete the multiplication. Without the
DQS 8 bit partial products, 64 times as many bits would be
required.
REMARKS
Application of the quarter square multiplication technique to
digital multiplication significantly decreases the number of bits of
storage required to implement a given word length multiplication
using ROM's. Some loss of speed occurs due to the additions
required in the DQS technique, however the power consumption
and cost should decrease. Multiplication times on the order of 100
ns or less should be attainable in an LSI implementation' of a
digital quarter square multiplier, with the ultimate speed being
determined by the ROM used.
A senior project group at Wichita State University built an 8 bit
DQS multiplier using standard TTL adders, gates, and 1702
EPROM's. The multiply time, as expected, was the sum of the 2
additions, absolute value, and ROM access times.
261
IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 3, MARCH 1980
multiple lead failures (not necessarily permanent stuck-at faults)
and we denote by s the probability of a single lead failure. Since
349-356, May 1965.
the
faults on different lines in the system are not necessarily equiA. Habibi and P. A. Wintz, "Fast multipliers," IEEE Trans. Comput., vol. C-19,
probable we denote by sx the probability of a fault on line X. The
pp. 153-157, Feb. 1970.
S. Waser, "High speed monolithic multipliers for real-time digital signal proces- probability s is in general time-dependent and the most
sing," Computer, vol. 11, no. 10, pp. 19-29, Oct. 1978.
commonly used fault probability function is s(t) = 1 - e where
J. R. Logan, "A square-summing high-speed multiplier," Comput. Des., pp. 67-70,
A is the failure rate. Consequently, the signal reliability of the
June 1971.
A. Stenzel, B. Kubitz, and C. Garcia, "A compact high-speed parallel multiplica- system, denoted by SR(t), is time-dependent and is defined as
tion scheme," IEEE Trans. Comput., vol. C-26, pp. 948-957, Oct. 1977.
follows:
REFERENCES
[1] L. Dadda, "Some schemes for parallel multipliers," Alta Freq., vol. 19, pp.
[2]
[3]
[4]
[5]
-A New Approach to the Evaluation of the
Reliability of Digital Systems
ISRAEL KOREN AND EITAN SADEH
Abstract-Signal reliability, as a measure of digital systems'
reliability, has not been used until recently due to lack of efficient
evaluation methods. A new approach to the evaluation of signal
reliability is presented in this work. A reliability transfer function of
digital systems is defined and a method for its evaluation is presented. This approach provides a new insight into the problem of
digital system reliability. Furthermore, it simplifies signal reliability
calculations and can easily be mechanized.
Index Terms-Functional reliability, multiple faults, reliability
transfer matrix, star product, signal reliability.
SR(t)= Pr{the output signal is correct at time t}.
In some applications of reliability analysis (e.g., prediction of mission time) the accumulative signal reliability in the time interval
[0, t] rather than at instant t, is needed. This accumulative signal
reliability, denoted by R,(t), is defined as follows:
R,(t)
= Pr{the output signals are correct in the time interval [0, t]}.
These two signal reliabilities have been analyzed and compared to
the corresponding functional reliabilities [6]. Here we restrict ourselves to evaluation of the non-accumulative signal reliability and,
for convenience, we call it signal reliability. Several applications of
the signal reliability were mentioned in [2]-[4], [6], [7]. One of the
important applications of signal reliability is comparison between
different realizations of a logical system. Employing the functional
reliability measure results in a less accurate reliability comparison
of different designs. When the functional reliability is evaluated,
the reliability of the basic element is raised to the number of these
elements in the system, e.g., [5], [8]. Although reliability is a function of the complexity of the system, the complexity may not be
treated as a simple function of the number of basic elements [8].
Contrary to the functional reliability measure, the signal reliability depends upon the exact structure of the system, the nature of
the possible failures and their probabilities, thus yielding a more
accurate reliability comparison of different designs.
In the next section we present a procedure for the evaluation of
the signal reliability of combinational systems. For convenience,
we omit t as an argument of the reliability and failure probability
functions and these functions are understood to be
time-dependent.
I. INTRODUCTION
Two reliability measures can be employed when the reliability
of a digital system is evaluated, namely, functional reliability and
signal reliability [1]-[6]. The first one is undoubtedly simpler to
apply and requires a smaller amount of computation however, it
is known to be exceedingly pessimistic [1]-[6]. The more accurate
signal reliability measure has not been used until recently, due to
lack of efficient evaluation methods. Algorithms for the evaluation
of signal reliabilities have been introduced lately by Ogus [2] and
Koren [4J, [6J. However, both methods require complex symbolic
manipulations resulting from the existence of statistical dependence among the various signals in a digital system [2]-[4], [6].
In this work we present a new approach to the evaluation of
signal reliabilities in which statistical dependence between signals
III. THE RELIABILITY TRANSFER MATRIX
is handled in a natural way and symbol manipulations are
avoided. We introduce the concept of reliability transfer function,
The presence of faults in a system may cause incorrect logic
enabling us to incorporate any fault model into our analysis and signals on some lines. Consequently, the signal on each line X
to consider large subsystems (e.g., IC modules) rather than single may assume one of four values, namely, correct 0, correct 1, incorgates as basic elements. Consequently, for a large class of digital rect 0 and incorrect 1. These values will be designated by 0, 1, 2
systems this new approach reduces considerably the amount of and 3, respectively. Thus, the signal X is a random four-valued
computation involved in evaluating signal reliabilities.
variable and the probabilities of its four possible values are
II. PRELIMINARIES
To evaluate the reliability of a digital system we need to have
some knowledge on the nature of the possible faults and their
probabilities of occurrence. We assume that the possible faults are
Manuscript received July 5, 1977; revised August 17, 1979.
I. Koren is with the Department of Electrical Engineering, Technion-Israel
Institute of Technology, Haifa, Israel, on leave from the Department of Electrical
Engineering-Systems, University of Southern California, Los Angeles, CA 90007.
E. Sadeh was with the Department of Electrical Engineering and Computer
Science, University of California, Santa Barbara, CA 93106. He is now with Mark
Resources, Inc., Marina del Rey, CA 90291.
Pr{X = 0} = Pr{X is correctly a 0} Ro(X)
Pr{X = 11 = Pr{X is correctly a 11 -R(X)
Pr{X = 2} = Pr{X is incorrectly a 0} A R2(X)
Pr{X = 3} = Pr X is incorrectly a 1} A R3(X).
Clearly, RO(X) + R1(X) + R2(X) + R3(X) = 1.
The signal reliability of line X, denoted SR(X), is the probability that the signal on line X is correct, hence,
SR(X) = Ro(X) + R1(X).
0018-9340/80/0300-0261$00.75 © 1980 IEEE