ISSN 2319-8885
Vol.04,Issue.32,
August-2015,
Pages:6435-6439
www.ijsetr.com
Comparison of Effective area Efficient Architectures for Modified SQRT CSLA
P. NAVANEETHA1, G. SRI SATYA VANI2
1
PG Scholar, DRK Institute of Science and Technology, Bowrampet, Hyderabad, TS, India,
E-mail: [email protected].
2
Assistant Professor, DRK Institute of Science and Technology, Bowrampet, Hyderabad, TS, India,
E-mail: [email protected].
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable
systems. Carry Select Adder (CSLA) is a fast adder used in data- processing processors for performing fast arithmetic functions.
From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this
paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA)
and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still areaconsuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a
single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA,
the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the
Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT
CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This paper was aimed for
implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized
using Xilinx PlanAhead13.4.
Keywords: Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Save Adder (CSA).
I. INTRODUCTION
High-speed data path logic systems are one of the most
substantial areas of research in VLSI system design. The
speed of addition is limited by the time required to propagate
a carry through the adder in digital adders. The sum for each
bit position in an elementary adder is generated sequentially
only after the previous bit position has been summed and a
carry propagated into the next position. The CSLA is used in
many computational systems to alleviate the problem of carry
propagation delay by independently generating multiple
carries and then select a carry to generate the sum the CSLA
is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA) to generate partial sum and carry.
Design of high speed data path logic systems are one of the
most substantial research area in VLSI system design. Highspeed addition and multiplication has always been a
fundamental requirement of high-performance processors and
systems. The major speed limitation in any adder is in the
production of carries and many authors have considered the
addition problem. The basic idea of the proposed work is
using n-bit binary to excess-1 code converters (BEC) to
improve the speed of addition. The detailed structure and
function of BEC. This logic can be implemented with any
type of adder to further improve the speed. The proposed 16,
32 and 64-bit adders are compared in this paper with the
conventional fast adders such as carry save adder (CSA) and
carry look ahead adder (CLA).
This paper has realized the improved performance of the
CSA with BEC logic through custom design and layout.
The final stage CPA constitutes a dominant component of the
delay in the parallel multiplier. Signals from the multiplier
partial products summation tree do not arrive at the final
CPA at the same time. This is due to the fact that the number
of partial-product bits is larger in the middle of the multiplier
tree. Due to un-even arrival time of the input signals to the
final CPA, the selection of the ASIC Implementation of
Modified Faster Carry Save Adder 54 final adder is an
important work in parallel multipliers. Therefore decrease in
carry propagation delay will result in major enhancement of
the speed of the adder and multiplier. This paper is structured
as follows. In Section 2, an overview of the 4-bit binary to
excess-1 logic is provided. Section 3 deals with the proposed
modified carry save adder (MCSA) architecture. Among the
myriad of aggressive techniques, carry select adder (CSL)
has been an eminent technique in the space-time tug-of-war
of CPA design. It exhibits the advantage of logarithmic gate
depth as in any structure of the distant-carry adder family.
Conventionally, CSL is implemented with dual ripple-carry
adder (RCA) with the carry-in of 0 and 1, respectively.
Depending on the configuration of block length, CSL is
further classified as either linear or square root. The basic
idea of CSL is anticipatory parallel computation.
Copyright @ 2015 IJSETR. All rights reserved.
P. NAVANEETHA, G. SRI SATYA VANI
of a single bit full adder, to find out the output of summation
II. LITERATURE REVIEW
There are different types of fast adders used in processors
signal as carry-in signal is logic ‗0‘ is the inverse signal of
such as ripple carry adder (RCA), carry look ahead adder
itself as carry-in signal is logic ‗1‘. By sharing the common
(CLA) and carry select adder. Ripple carry adder provides
Boolean logic term in summation generation, a proposed
compact design but their computation time is high. Carry
carry select adder design. To share the common Boolean
look ahead adder gives fast result but it leads to an increase
logic term, it only needs to implement one OR gate with one
in area. Carry select adder provides a compromise between
INV gate to generate the carry signal and summation signal
RCA and carry look ahead adder. Ripple carry adder
pair. Once the carry-in signal is ready, then select the correct
produces worst case delay, because it consists of N single bit
carry-out output according to the logic state of carry-in
full adders. Each adder produces the sum and carry. The
signal.
carry of the previous full adder is given as the input to the
B. General
next adder. The carry is transferred through every stage and
Adders are commonly found in the critical path of many
produces a delay called worst case delay. In ripple carry
building blocks of microprocessors and digital signal
adder as value of N increases, delay also increases. So ripple
processing chips. Adders are essential not only for addition,
carry adder has the lowest speed among the fast adders. The
but also for subtraction, multiplication, and division.
CSLA is used to anticipate all possible values of input carry
Addition is one of the fundamental arithmetic operations. A
i.e. 0 and 1 and evaluates the result in advance. The result is
fast and accurate operation of a digital system is greatly
selected by the multiplexer. The CSLA uses dual RCA‘s to
influenced by the performance of the resident adders. The
generate partial sum and carry by considering Cin=0 and
most important for measuring the quality of adder designs in
Cin=1 then the final sum and carry is selected by using
the past were propagation delay, and area. The three most
multiplier. In regular CSLA area consumed is more due to
widely accepted metrics for measuring the Performance of a
the use of dual RCA‘s. The basic idea of this work is to use
circuit are power, delay and area. Minimizing Area and delay
Binary to excess-1 convertor (BEC) instead of RCA with
has always been considered important, but Reducing power
Cin=1to reduce the area and power.
consumption has been gaining prominence recently with the
The advantage of BEC is that it uses less number of logic
increasing level of device integration and the Growth in
gates than N bit full adders. To reduce the delay N bit ripple
complexity of micro-electronic circuits, reduction of Power
carry adders are replaced with N+1 bit BEC .So modified
dissipation has come to fore as a primary design goal. While
SQRT CSLA is area consuming than regular CSLA. Bedriji
power efficiency has always been desirable.
1962 proposes [1] that the problem of carry propagation
In electronic Circuits, only recently has it become a
delay is overcome by independently generating multiple
limiting
factor for a broad Range of applications, there by
radix carries and using these carries to select between
requiring consideration early on in the design process. Carry
simultaneously generated sums. The design and
Select Adder is one of the fastest adders used in many data
implementation of a generic fast asynchronous Hybrid
processing processors to perform fast arithmetic functions. It
Kogge-Stone Structure Carry Select based Adder (HKSSalleviates the problem of carry propagation delay by
CSA) is described in detail and its application in the design
independently generating multiple carries and then selects a
of asynchronous Double Precision Floating-Point Adder
carry to generate the sum. The carry-select adder (CSLA)
(DPFPA) is presented and the improved latency performance
provides a compromise between small area but longer delay
it provides is discussed. In this adder system, the addend and
ripple carry adder (RCA) and larger area with shorter delay
augends are divided into sub addend and sub augends
carry look-ahead adder. CSLA uses multiple pairs of ripple
sections that are added twice to produce two sub sums. One
carry adder (RCA) to generate partial sum and carry by
addition is done with a carry digit forced into each section,
considering carry input Cin=0 and Cin=1, then the final sum
and the other addition combines the operands without the
and carry are selected by multiplexers (MUX) The modified
forced carry digit. The selection of the correct, or true, sub
CSLA using BEC has reduced area and power consumption
sum from each of the adder sections depends upon whether
with slight increase in delay. BEC design consists of AND,
or not there actually is a carry into that adder section.
XOR and NOT gates as its structure. In this structure the
High-speed addition and multiplication has always been a
XOR gate will be replaced by MUX with NOT gate. The
fundamental requirement of high-performance processors and
proposed CSLA design reduces the area and power by
systems. The major speed limitation in any adder is in the
replacing the gates in BEC design.
production of carries and many authors have considered the
addition problem. High-speed data path logic systems are one
C. Regular CSLA Architecture
of the most substantial areas of research in VLSI system
As said above CSLA compromise between ripple carry
design. The speed of addition is limited by the time required
adder
and carry look ahead adder. The main disadvantage of
to propagate a carry through the adder in digital adders.
regular CSLA is the large area due to the multiple pairs of
ripple carry adder. The regular 16-bit carry select adder. It is
III. SYSTEM DESIGN
divided into five groups with different bit size RCA. From
A. Proposed System
the structure of CSLA, it is evident that there is scope for
In proposed architecture, an area-efficient carry select
reducing area and power consumption. The carry out
adder by sharing the common Boolean logic term to remove
calculated from the last stage i.e. least significant bit stage is
the duplicated adder cells in the conventional carry select
used to select the actual calculated values of the output carry
adder is shown in this way, it saves many transistor counts
and sum. The selection is done by using a multiplexer.
and achieves a low power. Through analyzing the truth table
International Journal of Scientific Engineering and Technology Research
Volume.04, IssueNo.32, August-2015, Pages: 6435--6439
Comparison of Effective area Efficient Architectures for Modified SQRT CSLA
Internal structure of the group 2 of regular 16-bit CSLA is
maximum carry delay. The structure of the 128-b regular
shown Fig.1 By manually counting the number of gates used
SQRT CSLA is shown in Figure. It has five groups of
for group 2 is 57 (full adder, half adder, and multiplexer).
different size RCA. The delay and area evaluation of each
One input to the mux goes from the RCA with Cin=0 and
group are shown in Figure, in which the numerals within
other input from the RCA with Cin=1.
specify the delay values, e.g., sum2 requires 10 gate delays.
The structure of the 128-b regular SQRT CSLA is shown in
Fig.3. It has sixteen groups of different size RCA. The delay
and area evaluation of first five groups are shown in Fig.3, in
which the numerals within specify the delay values, e.g.,
sum2 requires 10 gate delays. The steps leading to the
evaluation are as follows.
 The group2 has two sets of 2-b RCA, the arrival time of
selection input c1[time(t)=7] of 6:3 mux is earlier than
S3[t=8] and later than s2[t =6] Thus, sum3[t = 11] is
summation of S3 and MUX[t=3] andSUM2[t=10] is
summation of C1 and mux.

Except for group2, the arrival time of mux selection
Fig.1. Group 2.
input is always greater than the arrival time of data
outputs from the RCA‘s. Thus, the delay of group3 to
D. Modified CSLA Using BEC
group5 is determined, respectively as follows: {c6;
The Binary to excess one Converter (BEC) replaces the
sum[6 : 4]} = c3[t =10]+mux {c10; sum[10 : 7]} = c6[t =
ripple carry adder with Cin=1, in order to reduce the area and
13] + mux {cout; sum[15 : 11]} = c10[t = 16] +mux.
power consumption of the regular CSLA. The structure is
 The one set of 2-b RCA in group2 has 2 FA for Cin=1and
again divided into five groups with different bit size RCA
the other set has 1 FA and 1 HA for Cin=0. Based on the
and BEC. The group 2 of the modified 16-bit CSLA is
area count of Table I, the total number of gate counts in
shown Fig.2. By manually counting the number of gates used
group2 is determined as follows:
for group 2 is 43 (full adder, half adder, multiplexer, BEC).
Gate count=57(FA+HA+MUX).
FA=39(3 *13)
HA=6(1 * 6);Mux=12(3* 4)
 Similarly, the estimated maximum delay and area of the
other groups in the regular SQRT CSLA are evaluated.
Fig.2. Group2.
One input to the mux goes from the RCA with Cin=0 and
other input from the BEC. Comparing the group 2 of both
regular and modified CSLA, it is clear that BEC structure
reduces the area and power. But the disadvantage of BEC
method is that the delay is increasing than the regular CSLA.
Fig.3.Architecture of Regular SQRT 128-Bit CSLA.
E. Architecture of 128 Regular SQRT Bit CSLA
A 16-bit carry select adder can be developed in two
different sizes namely uniform block size and variable block
size. Similarly a 32, 64 and 128-bit can also be developed in
two modes of different block sizes. Ripple-carry adders are
the simplest and most compact full adders, but their
performance is limited by a carry that must propagate from
the least significant bit to the most-significant bit. The
various 16, 32, 64 and 128-bit CSLA can also be developed
by using ripple carry adders. The speed of a carry-select
adder can be the importance of the BEC logic stems from the
large silicon area reduction when the CSLA with large
number of bits are designed. The Boolean expressions of the
8-bit BEC is listed improved up to 40% to 90%, by
performing the additions in parallel, and reducing the
F. Modified SQRT Architecture Of 128 Bit CSLA
This architecture is similar to regular 64-bit SQRT CSLA,
the only change is that, we replace RCA with Cin=1 among
the two available RCAs in a group with a BEC. This BEC
has a feature that it can perform the similar operation as that
of the replaced RCA with Cin=1. Fig.4 shows 4.19 the
Modified block diagram of 128-bit SQRT CSLA. The
number of bits required for BEC logic is 1 bit more than the
RCA bits. The modified block diagram is also divided into
various groups of variable sizes of bits with each group
having the ripple carry adders, BEC and corresponding mux.
As shown in the Fig.4, Group 0 contain one RCA only which
is having input of lower significant bit and carry in bit and
produces result of sum[1:0] and carry out which is acting as
mux selection line for the next group, similarly the procedure
International Journal of Scientific Engineering and Technology Research
Volume.04, IssueNo.32, August-2015, Pages: 6435-6439
P. NAVANEETHA, G. SRI SATYA VANI
continues for higher groups but they includes BEC logic
The RTL Schematic of the Modified SQRT 128-bit CSLA
instead of RCA with Cin=1.Based on the consideration of
is given. It has a(127:0), b(127:0) and Cin are the inputs and
delay values, the arrival Percentage of delay overhead
S(127:0), Cout are the outputs as shown in Fig.5.
exhibits a similarly decreasing trend with bit size. The delay
overhead for the 8, 16, and 32-b is 14%, 9.8%, and 5.63%
respectively, whereas for the 64-b it reduces to only 4.75%.
The power–delay product of the proposed 8-b is higher than
that of the regular CSLA by 5.2% and the area-delay product
is lower by 2.9%. However, the power-delay product of the
proposed 16-b CSLA reduces by 1.76% and for the 32-b and
64-b by as much as 8.18%, and 12.28% respectively.
Similarly the area-delay product of the proposed design for
16-, 32-, 64-b and 128-b is also reduced by 6.7%, 11%, and
14.4% respectively.
Fig.6. Output waveform.
The output waveform of the Modified SQRT 128-bit is
given. The value of a and b are given in the decimal form as
shown in Fig.6.
a=1000
b=1000
Cin=0; Cout=2000
Fig.4.Architecture of Modified SQRT 128-Bit CSLA.
Advantages:
 Low power consumption
 Less area (less complexity)
 More speed compare to Regular CSLA.
Applications:
 Arithmetic logic units
 High speed multiplications
 Advanced microprocessors
 DSP.
IV. RESULTS
Fig.7. Device utilization.
The Device Utilization of the Modified SQRT CSLA
gives the number of slices, number of LUT‘S that are used as
shown in Fig.7.
Fig.5. RTL Schematic.
V. CONCLUSION
This project presented a simple approach to reduce the area
of CSLA architecture. The reduced number of gates of this
work offers the great advantage in the reduction of area. The
area (gate count) of the 128 bit Regular SQRT CSLA is
significantly reduced by 207 gates when compared with 128
International Journal of Scientific Engineering and Technology Research
Volume.04, IssueNo.32, August-2015, Pages: 6435--6439
Comparison of Effective area Efficient Architectures for Modified SQRT CSLA
bit Regular Linear CSLA and also the comparison between
[8]Y. Kim and L.-S. Kim, ―64-bit carry-select adder with
128 bit Regular Linear CSLA and 128 bit Modified Linear
reduced area,‖ Electron. Lett. vol. 37, no. 10, pp. 614–615,
CSLA, the area of the 128 bit Modified Linear CSLA is
May 2001.
reduced by 868 gates. Then the area of the 128 bit Modified
[9]J. M. Rabaey, Digtal Integrated Circuits—A Design
SQRT CSLA is reduced by 115 gates than the area of the 128
Perspective.Upper Saddle River, NJ: Prentice-Hall, 2001.
bit Modified Linear CSLA. Totally from the result analysis
the Modified SQRT CSLA has reduced area. The area of the
proposed design shows a decrease for 16-bit, 32-bit, 64-bit
and 128-bit sizes which indicate the success of the method
and not a mere tradeoff of delay for area. The Modified
CSLA architecture is therefore, low area, simple and efficient
for VLSI hardware implementation. Finally the comparison
between the area of 128 bit Regular SQRT CSLA and the
area of the 128 bit Modified SQRT CSLA, the area of 128 bit
Modified SQRT CSLA is reduced by 776 gates than the 128
bit Regular SQRT CSLA.
VI. FUTURE SCOPE
This project presented a simple approach to reduce the
area of CSLA architecture. This paper has really given a
effective description of an higher bit high speed and area
efficient carry select adder. This has been achieved by
altering the logic blocks of the regular module, which intern
helped us to have a new advantageous adder of higher bit
than previous one. Many electronic applications are required
of faster adders of higher number of bits which helps their
process very faster. Replacing RCA with BEC and using a
additional multiplexer for carry out which is decreasing the
propagation delay. This paper can provide us for future scope
like we can increase the number of bits of this adder and we
can think of new ideas to decrease still more area of the
device as it increases in its number of bits.
VII. RFERENCES
[1]Cadence, ―Encounter user guide,‖ Version 6.2.4, March
2008. Ramkumar, B. and Harish M Kittur, ―Low Power and
Area Efficient Carry Select Adder‖, IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, pp.1-5, 2012.
[2]Edison A.J and C.S.Manikandababu ―An Efficient CSLA
Architecture for VLSI Hardware Implementation‖
International Journal for Mechanical and Industrial
Engineering, Vol. 2. Issue 5, 2012.
[3]P.Sreenivasulu. K.SrinivasaRao, Malla Reddy, and
A.VinayBabu―Energy and Area efficient Carry Select Adder
on a reconfigurableHardware‖ International Journal of
Engineering Research andApplications, Vol. 2, Issue 2,
pp.436-440, march 2012.
[4]Sarabdeep Singh and Dilip Kumar, ―Design of Area and
Power efficient
Modified Carry Select Adder‖
International Journal of Computer
Applications
(0975 – 8887) Volume 33– No.3, November 2011.
[5]B. Ramkumar, H.M. Kittur, and P. M. Kannan, ―ASIC
implementationof modified faster carry save adder,‖ Eur. J.
Sci. Res., vol. 42, no. 1,pp.53–58, 2010.
[6]Y. He, C. H. Chang, and J. Gu, ―An area efficient 64-bit
square Root carry-select adder for low power applications,‖
in Proc. IEEE Int. Symp.Circuits Syst., vol. 4, pp. 4082–
4085, 2005.
[7]He, Y. Chang, C. H. and Gu, J. ―An Area Efficient 64-Bit
Square Root Carry-Select Adder for Low Power
Applications,‖ in Proc. IEEE Int.Symp. Circuits Syst., Vol.4,
pp. 4082–4085, 2005.
International Journal of Scientific Engineering and Technology Research
Volume.04, IssueNo.32, August-2015, Pages: 6435-6439