DAVE s.r.l.
CREATION:
May 2008
LAST REVISION:
Jan 2009
VERSION:
1.2.0
www.dave.eu
Neptune
Hardware Manual
DAVE
<Page intentionally left blank>
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DAVE
Neptune Hardware Manual
Trademarks
Ethernet® is a registered trademark of XEROX Corporation
All other trademarks are the property of their respective owners
Copyright
All rights reserved. Specifications may change any time without notification.
Disclaimer
DAVE does not assume any responsibility about availability, supplying and support about all the products
mentioned in this manual that are not strictly part of the Neptune module.
Life Support Applications
Neptune Embedded Computer Boards are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result in personal injury.
DAVE Srl customers who are using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify DAVE Srl for any damage resulting from such improper use or sale.
Company Address
DAVE S.r.L.
Via Forniz 2
33080 Porcia (PN) – Italy
Phone:
+39 0434 921215
e-mail:
[email protected]
URL:
www.dave.eu
Technical Support
e-mail:
[email protected]
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DAVE
History
Version
Date
Notes
0.9.0
June 2008
First draft
0.9.1
July 2008
Added pinout tables
0.9.2
August 2008
Added pin LPC_FLASH.ID0
0.9.5
September 2008
Added section “FPGA external interfaces“
0.9.6
September 2008
Replaced GPIO1 with GPIO10 in FPGA JTAG interface
0.9.7
October 2008
Added FPGA block diagram and RS485 automatic direction signal driver
1.0.0
November 2008
First Release
Added section “Power Supply”, section “Host board design guidelines” and section
“Naming, order codes and standard releases”
1.1.0
January 2009
Added section about temperature sensor
Added section about touch screen controller
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Contents
1 Introduction.........................................................................................................................................8
1.1 Block Diagram.................................................................................................................................................9
2 Specifications ...................................................................................................................................10
3 Module design...................................................................................................................................11
3.1 System architecture.......................................................................................................................................11
3.2 Boot options...................................................................................................................................................12
3.3 Open Firmware..............................................................................................................................................12
4 Board layout and Physical..................................................................................................................14
5 Power Supply....................................................................................................................................17
5.1 Power consumption.......................................................................................................................................17
5.2 Power sequencing.........................................................................................................................................17
5.3 Recommended voltage regulators..................................................................................................................18
5.4 Voltage monitoring.........................................................................................................................................18
6 Connectors pinout..............................................................................................................................19
6.1 How to read this section.................................................................................................................................19
6.2 Connectors pinout..........................................................................................................................................20
7 Resource allocation and FPGA notes..................................................................................................35
7.1 Resource allocation........................................................................................................................................35
7.1.1 Simplified memory map................................................................................................................................................35
7.1.2 IRQs............................................................................................................................................................................35
7.1.3 Temperature sensor.....................................................................................................................................................36
7.1.4 Touch screen controller.................................................................................................................................................36
7.2 FPGA notes...................................................................................................................................................36
7.2.1 FPGA external interfaces..............................................................................................................................................36
7.2.1.1 Local bus controller...................................................................................................................................................37
7.2.1.2 RS485 automatic direction signal driver.....................................................................................................................37
7.2.2 On-board FPGA JTAG interface....................................................................................................................................39
8 Host board design guidelines..............................................................................................................40
8.1 UARTs (RS232/RS485).................................................................................................................................41
8.2 VGA..............................................................................................................................................................42
8.3 Local bus (standard chip select).....................................................................................................................43
8.4 Local bus (8051-like chip select).....................................................................................................................44
8.5 Ethernet.........................................................................................................................................................45
8.6 USB host.......................................................................................................................................................46
8.7 AC97 audio....................................................................................................................................................47
8.8 CompactFlash...............................................................................................................................................48
8.9 Second boot flash (dual-boot function)............................................................................................................49
8.10 Geode JTAG................................................................................................................................................50
9 Naming, order codes and standard releases.......................................................................................51
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10 Agency approvals............................................................................................................................52
11 Support...........................................................................................................................................52
Illustration Index
Fig. 1: Dual-boot logical connections..................................................................................................................11
Fig. 2: Board layout - top view............................................................................................................................13
Fig. 3: Board layout - bottom view......................................................................................................................14
Fig. 4: Neptune Depth.......................................................................................................................................14
Fig. 5: Neptune Board.......................................................................................................................................15
Fig. 6: Graphical representation of reset thresholds for 3.3V................................................................................17
Fig. 7: FPGA PCI device memory mapping........................................................................................................33
Fig. 8: FPGA internal block diagram (default bitstream)......................................................................................34
Fig. 9: Internal FPGA JTAG connections............................................................................................................36
Fig. 10: UARTs reference schematic.................................................................................................................38
Fig. 11: VGA reference schematic.....................................................................................................................39
Fig. 12: Standard local bus chip select reference schematic................................................................................40
Fig. 13: 8051-like local bus chip select reference schematic................................................................................41
Fig. 14: Ethernet reference schematic................................................................................................................42
Fig. 15: Ethernet PCB copper keepout area.......................................................................................................42
Fig. 16: USB host reference schematic..............................................................................................................43
Fig. 17: AC97 codec reference schematic..........................................................................................................44
Fig. 18: CompactFlash reference schematic......................................................................................................45
Fig. 19: External LPC flash reference schematic................................................................................................46
Fig. 20: Geode JTAG reference schematic........................................................................................................47
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Technical Data
CPU
AMD Geode x86/x87-compatible CPU core
0.13 micron process
LX [email protected] processor - 600MHz
LX [email protected] processor - 500MHz
LX [email protected] processor – 433MHz
Multimedia
VESA 1.1 and 2.0 compliant, 8 or 16-bit Video Input Port (VIP)
Intel MMX and AMD 3DNow instruction sets
Audio Codec 97 (AC97) Controller
High performance 2D graphics controller
Video Output Port (VOP) supporting SD and HD 480p, 480i, 720p, and 1080i
Supervisor
AMD Geode™ CS5536 companion device
RTC and CMOS RAM
Memory
Cache
DDR
LPC Flash
NAND
64K I / 64K D L1 cache and 128K L2 cache
256MB or 512 MB 64-bit Memory Interface
1 MB
up to 1 GB
Interfaces)
LAN
UART
USB
External Bus
I/O Controller
Gigabit Ethernet including PHY
4 (Including one Infrared Communication Port)
4 2.0 Host ports or 3 2.0 Host ports and 1 2.0 device port
PCI specification v2.2 compliant, 32-Bit, 33/66 MHz operation
General Purpose I/O and Multi-Function General Purpose Timers
SMB Controller
Debug
JTAG IEEE 1149.1 Test Access Port
PC Card
Compact Flash
Hard Disk Support 100 MB/s ATA-6 IDE Controller
LCD controller
Resolution
Up to 1920x1440x32bpp in CRT mode and 1600x1200x32bpp in TFT mode
Type
CRT, TFT
Touch Screen
Yes
Mechanical
Connectors
3 x 140 pin 0.6 mm pitch
Physical
97 mm x 67 mm x 9,30 mm
Temperature
Commercial Temperature Range
Industrial temperature range available for the
LX [email protected] processor
PSU
3.3V
Through connector, full regulation on-board.
3.3V I/O and 1.20V/1.25V/1.40V (nominal) Core operation
Consumption
< 7W with high-load operation
Software
BIOS
Open Firmware
Multitasking OS
Linux 2.6.xx
Windows
WindowsCE 6.0
Agency approvals
Pre-compliance
EN 55022, EN 55024
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1 Introduction
NEPTUNE is a General Purpose microprocessor CPU board powered by the AMD Geode LX x86
compatible CPU familly.
NEPTUNE is suitable for single board computing or mobile computing applications, based on Linux,
Microsoft Windows CE and Microsoft Windows XP environments. Levering on the x86 compatibility,
NEPTUNE allows quick deployment of solutions based on software developed for the well-known x86
platform. Moreover, the adoption of Open Firmware as hardware-independent firmware, allows the users to
follow the developing strategies available for the typical embedded systems (e.g. U-boot powered systems).
The powerful on-board FPGA highly extends NEPTUNE versatility (*).
All interface signals are routed externally through three 140 pin 0.6mm pitch stacking connectors. Users should
complete hardware interfaces and connectors when they want to use them through the host board1.
A full overview of the board is given, both from mechanical and electrical point of view. Nevertheless, for
detailed information, user should refer to components manufacturer’s data sheet.
(*)
Please note that all the information provided by this document
refer to the Neptune module configured with the default FPGA
bitstream released with Neptune Development Kit. For more
details please see also section 7.2 on page 36.
1
With the expression “host board” we refer to the board where Neptune processor module will be plugged on.
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1.1 Block Diagram
NAND
FLASH
Up to 1GB
LPC
FLASH
1MB
NAND
CONTROLLER
LPC
4 x USB 2.0
AC97 AUDIO
L+R IN & OUT
IDE
CS5536
2 x UART
I2C
CLOCK
GEN.
TFT
DDR
256- 512MB
JTAG
GEODE
LX
VGA
140 x 2 0.6mm pitch
140 x 2 0.6mm pitch
PCI
Touch
Screen
Controller
2 x UART
GPIO
FPGA
EXT. BUS
PHY
Gigabit
Ethernet
PCI
LVDS PORT
(IN/OUT)
ETH
VIDEO INPUT PORT
140 x 2 0.6mm pitch
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2 Specifications
10
CPU
Speed
Flash NAND
LPC Flash
RAM
AMD Geode LX
433 MHz – 600 MHz
Up to 1 GB
1 MB
256 MB (typical) or 512 MB DDR @ 333 MHz
Supervision
AMD Geode™ CS5536 companion device
RTC and CMOS RAM
Power supply
Through connector, full regulation on-board.
3.3V I/O and 1.20V/1.25V/1.40V (nominal) Core operation
Dimensions
97 mm x 67 mm
Connectors
Hirose FX8C-140S-SV
Mating connectors
Hirose FX8C-140P-SV (5 mm board-to-board height)
Hirose FX8C-140P-SV1 (6 mm board-to-board height)
Hirose FX8C-140P-SV2 (7 mm board-to-board height)
Hirose FX8C-140P-SV4 (9 mm board-to-board height)
Hirose FX8C-140P-SV6 (11 mm board-to-board height)
Agency Approvals
EN 55022 (t.b.o.)
EN 61000-4-3 (t.b.o.)
EN 61000-4-4 (t.b.o.)
EN 61000-4-6 (t.b.o.)
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3 Module design
This section briefly describes the basic system architecture underling Neptune processor module.
3.1 System architecture
Neptune processor module is built around the AMD Geode LX CPU and the AMD CS5536 companion chip2.
Simplified block diagram is shown in section 1.1. Processor and companion chip are connected via PCI bus. This
bus – that is routed externally through main connectors – provides CPU to on-board FPGA connection, too.
FPGA plays an important role in module architecture. From the processor point of view, it acts as a complex
PCI device encapsulating several functions (16550-like UARTs, ethernet controller etc.). One the most appealing
function is the PCI-to-LocalBus bridging. Please note that the term local bus here referred has nothing to do with
the VESA Local Bus3. In this context the expression “local bus” refers to a generic bus composed by the following
signals instead:
•
address bus
•
data bus
•
chip selects
•
write enable signal
•
read enable signal
•
irqs
This functionality has been conceived to allow glue-less connection to typical peripheral devices and memory
chips used in the embedded world such as ethernet controllers, SRAMs, USB controllers, CAN controllers etc.
Native buses and interfaces provided by companion chip CS5536 are available externally as shown in block
diagram. About IDE bus please note that, in case this option is featured, on-board NAND memory acts as master
IDE disk.
For module available configurations please refer to chapter 9 on page 51.
For more detailed technical information about them please refer to respective databooks freely available for
download on AMD web site.
3
See for example http://en.wikipedia.org/wiki/VESA_Local_Bus .
2
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3.2 Boot options
Processor boots from the LPC flash whose ID is 0. By default on-board flash has ID 0. However, in order to
support dual-boot capability the configuration pin FWH_LPC_ID0 is externally accessible.
Neptune module
LPC
bus
GeodeLX/CS5536
Host board
LPC
flash
ID=1
LPC
flash
ID=0
Fig. 1: Dual-boot logical connections
By pulling it up, it allows to change on-board flash ID to 1 (see also section 8.9 on page 49). In this case, if the
host board provides a second LPC flash whose ID is set to 0, this becomes the boot device. This technique can be
used for several purposes such as:
•
•
•
OpenFirmware image backup
OpenFirmware environment backup
in-system on-board flash programming in production environment.
3.3 Open Firmware
Default system firmware is Open Firmware. This is the most know implementation of the general standard with
the same name. As a standard Open Firmware, formerly endorsed by the IEEE (1275-1994), defines the
interfaces of a computer firmware system. As specific Neptune firmware implementation, Open Firmware allows
the system to load platform-independent drivers directly from the PCI card, improving compatibility. Through Open
Firmware, the system can access USB (ext2 and fat32 file systems) and Ethernet (allowing TFTP, NFS, HTTP
services). Also it can load the Linux Kernel and every ELF executable file. The following is a non exhaustive list of
OpenFirmware capabilities and features:
12
✔
Complete TCP/IP Stack with high level protocols support (FTP, HTTP, ..): developer can debug systems
downloading the kernel from network avoiding flash reprogramming
✔
Availability of source code
✔
Integrated forth code debugger
DAVE
✔
Operating system functions (Open Firmware can launch specific applications)
✔
Serial command shell like a traditional embedded bootloader
✔
Reduced footprint
✔
Multiplatform
✔
File system support (FAT, EXT2)
✔
Support for high-level devices: IDE disks, USB pendrives, compact flashes, keyboards, VGA, usb-ethernet
adapters
✔
Flash LPC reprogramming
✔
Full BIOS emulation
✔
Support for complex PC operating systems (Windows XP/XP Embedded, Windows Vista, Linux).
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4 Board layout and Physical
Neptune has been designed to fit on a 97 x 67 mm2 area.
All Neptune modules have the same footprint, but some models may have just two connectors. Ask technical
support for further informations.
See the following figures to understand Neptune mechanical specifications.
Fig. 2: Board layout - top view
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Fig. 3: Board layout - bottom view
Fig. 4: Neptune Depth
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Fig. 5: Neptune Board
Fig. 6: Neptune: Bottom Side
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5 Power Supply
Powering is usually a delicate operation. In Neptune modules this operation has been embedded in the module
and therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from host
board, and therefore users should be aware of the ranges power supply can assume as well as all other
parameters. The only input power value is 3.3V.
The following table summarizes limits for power supply :
3.3V Power supply
MIN
3.2V
MAX
3.4V
Tab. 1- Power supply ranges
Beyond this limits, proper working is not guaranteed since reset circuits are triggered to start on these limits. For
further details about reset, see section 5.4.
5.1 Power consumption
The following table summarizes nominal current consumptions and power consumption at 3.3V. Also power
and current absorption are indicated in case of low-power.
Consumption
High-load operation current @ 3.3V
High-load operating power @ 3.3V
Low-load operating current
Low-load operating power
Inrush current
2,05 A
6,77 W
0,92 A
3,03 W
6A
Tab. 2 - Summary of the budgetary power consumption
High-load operating power and current have been measured with the CPU stressed and USB, Compact Flash
and Gigabit Ethernet working; low-load operating current and power have been measured with just the Linux
kernel loaded with minimal functions running and no active interfaces.
5.2 Power sequencing
Neptune has just one requirement about the 3.3V voltage ramp that must be monotonically rising and with a
rise time between 0 and 10 ms.
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5.3 Recommended voltage regulators
Neptune requires regulators that respond quickly to step changes in load. The best solution is a switching
regulator. Please note that the Peak Output Current of the PSU must be compliant with the Inrush current
parameter shown in Tab. 2 - Summary of the budgetary power consumption
5.4 Voltage monitoring
In order to guarantee that microprocessor is monitored accurately, we should consider possible range of its
supply, that are summarized below:
3.3V (min. 3.2V – max. 3.4V)
Due to the fact that power supply regulation is provided from external circuitry, it is mandatory to monitor
accurately both voltages.
As far as 3.3V is concerned, a reset threshold at 3.08V with a maximum, possible temperature variation of +/2.5% in the operative temperature range has been adopted. In practice reset threshold has a variation from 3.00V
to 3.15V all over the extended temperature range.
3.2V
3.3V
Range of Input
Range of Reset
3.0V
3.08V
3.15V
Fig. 7: Graphical representation of reset thresholds for 3.3V
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3.4V
DAVE
6 Connectors pinout
6.1 How to read this section
The following tables report the pinout of the Neptune connectors, J1000, J1001 and J1002.
Each row in the table report the following information:
Pin
Reference to the connector pin
Pin Name
Pin name in Neptune schematics
Internal
Connections
CPU/Companion chip/FPGA signal connected to the pin
ALX prefix stands for AMD GeodeLX CPU
CS5536AD prefix stands for AMD CS5536 companion chip
FPGA prefix stands for Lattice XP2 FPGA
i.e.: FPGA.PT36A means pin PT36A of FPGA
Function
Function associated to the pin
Ball/pin #
Microprocessor, FPGA or LPC flash ball/pin number
Supply Group
Power Supply Group (FPGA)
Voltage
Voltage
19
6.2 Connectors pinout
Several pins available on connectors are connected to on-board FPGA. The functions of these pins – underlined in following tables with yellow background –
are referred to the default bitstream delivered with Neptune Development Kit (ndk-x.y.z). It is highly recommended to see also section 7.2.1 on page
36 for more details about these pins.
J1001 CONNECTOR - ODD 1-69
Pin
Pin Name
Internal Connections
J1001.1
J1001.3
J1001.5
J1001.7
J1001.9
J1001.11
J1001.13
J1001.15
J1001.17
J1001.19
J1001.21
J1001.23
J1001.25
J1001.27
J1001.29
J1001.31
J1001.33
J1001.35
J1001.37
J1001.39
J1001.41
J1001.43
J1001.45
J1001.47
J1001.49
J1001.51
J1001.53
J1001.55
J1001.57
J1001.59
J1001.61
J1001.63
J1001.65
J1001.67
J1001.69
DGND
DGND
DGND
3V3_EXT
3V3_EXT
3V3_EXT
3V3_EXT
3V3_EXT
3V3_EXT
USB0+
USB0DGND
USB1+
USB1DGND
USB2+
USB2DGND
USB3+
USB3DGND
USB_VBUS
USB_OC#
USB_PWR_EN1
USB_PWR_EN2
AC97_BITCLK
AC97_SYNC
AC97_DATA_IN
AC97_DATA_OUT
DGND
LB_IRQ0
LB_IRQ1
LB_IRQ2
LB_IRQ3
LB_IRQ4
CS5536AD.USB1_DATPOS
CS5536AD.USB1_DATNEG
CS5536AD.USB2_DATPOS
CS5536AD.USB2_DATNEG
CS5536AD.USB3_DATPOS
CS5536AD.USB3_DATNEG
CS5536AD.USB4_DATPOS
CS5536AD.USB4_DATNEG
CS5536AD.USB_VBUS
CS5536AD.USB_OC_SENS#
CS5536AD.USB_PWR_EN1
CS5536AD.USB_PWR_EN2
CS5536AD.AC_CLK
CS5536AD.AC_S_SYNC/BOS0
CS5536AD.AC_S_IN
CS5536AD.AC_S_OUT/BOS1
FPGA.PT31A
FPGA.PT34A
FPGA.PT34B
FPGA.PT36B
FPGAPT45B
Function
-
Local bus IRQ0
Local bus IRQ1
Local bus IRQ2
Local bus IRQ3
Local bus IRQ4
Ball/
pin #
K16
K17
L16
L17
H17
H16
G17
G16
M15
N15
P17
N16
M1
L3
L1
L2
D8
D9
D10
D11
D12
Supply
Group
Voltage
Note
Internal 22 Ohm resistance
Internal 22 Ohm resistance
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
J1001001 CONNECTOR - ODD 71-139
Pin
Pin Name
Internal Connections
Function
J1001.71
J1001.73
J1001.75
J1001.77
J1001.79
J1001.81
J1001.83
J1001.85
J1001.87
J1001.89
J1001.91
J1001.93
J1001.95
J1001.97
J1001.99
J1001.101
J1001.103
J1001.105
J1001.107
J1001.109
J1001.111
J1001.113
J1001.115
J1001.117
J1001.119
J1001.121
J1001.123
J1001.125
LB_IRQ5
LB_RD#
LB_WR#
DGND
LB_D0
LB_D1
LB_D2
LB_D3
LB_D4
LB_D5
LB_D6
LB_D7
LB_D8
LB_D9
LB_D10
LB_D11
LB_D12
LB_D13
LB_D14
LB_D15
DGND
EXT_LPC_CLK
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#
LPC_FRAME#
Local bus IRQ5
Local bus read
Local bus write
Local bus data 0
Local bus data 1
Local bus data 2
Local bus data 3
Local bus data 4
Local bus data 5
Local bus data 6
Local bus data 7
Local bus data 8
Local bus data 9
Local bus data 10
Local bus data 11
Local bus data 12
Local bus data 13
Local bus data 14
Local bus data 15
-
J1001.127
LPC_SERIRQ
J1001.129
J1001.131
FWH_LPC_ID0
IOC_GPIO6
FPGA.PT31B
FPGA.PT45A
FPGA.PT32B
FPGA.PT4B
FPGA.PT19B
FPGA.PT21B
FPGA.PT23B
FPGA.PT25B
FPGA.PT27B
FPGA.PT4A
FPGA.PT3A
FPGA.PT3B
FPGA.PT21A
FPGA.PT25A
FPGA.PT27A
FPGA.PT19A
FPGA.PT23A
FPGA.PT24B
FPGA.PT5B
CS5536AD.LPC_AD0/GPIO16
CS5536AD.LPC_AD1/GPIO17
CS5536AD.LPC_AD2/GPIO18
CS5536AD.LPC_AD3/GPIO19
CS5536AD.LPC_DRQ#/GPIO20
CS5536AD.LPC_FRAME#/GPI
O22
CS5536AD.LPC_SERIRQ/GPIO
21/MFGPT2_RS
LPC_FLASH.ID0
CS5536AD.GPIO6/MFGPT0_R
S/MFGPT1_C1/MFGPT2_C2
J1001.133
IOC_GPIO25
J1001.135
IOC_GPIO26
J1001.137
IOC_GPIO27
J1001.139
DGND
Ball/
pin #
E9
E12
F9
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B6
B7
C4
C6
C7
D4
H2
J2
J1
K1
G1
H3
-
-
GPIO6
D2
CS5536AD.GPIO25/LOW_BAT
#/MFGPT7_C2
GPIO25
A9
CS5536AD.GPIO26/MFGPT7_
RS
CS5536AD.GPIO27/MFGPT7_
C1/32KHZ
GPIO26
B7
GPIO27
C8
-
-
-
Supply
Group
VCCIO1
VCCIO1
VCCIO1
Voltage
Note
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
Internally 10kOhm pull-down
Used to implement internal FPGA JTAG
interface. See section 7.2.2 on page 39 for
more details.
Used to implement internal FPGA JTAG
interface. See section 7.2.2 on page 39 for
more details.
Used to implement internal FPGA JTAG
interface. See section 7.2.2 on page 39 for
more details.
J1001 CONNECTOR - EVEN 2-70
Pin
Pin Name
J1001.2
J1001.4
J1001.6
DGND
DGND
DGND
J1001.8
J1001.10
J1001.12
J1001.14
J1001.16
J1001.18
3V3_EXT
3V3_EXT
3V3_EXT
3V3_EXT
3V3_EXT
UART1_TX
J1001.20
UART1_RX
J1001.22
J1001.24
J1001.26
J1001.28
J1001.30
J1001.32
UART2_RX
UART2_TX
I2C_CLK
I2C_DATA
EXT_PCI_CLK
PCBEEP
J1001.34
J1001.36
J1001.38
J1001.40
J1001.42
J1001.44
J1001.46
J1001.48
J1001.50
J1001.52
J1001.54
J1001.56
J1001.58
J1001.60
J1001.62
J1001.64
J1001.66
J1001.68
J1001.70
IRQ13
PR_GPIO0
PR_GPIO1
PR_GPIO2
PR_GPIO3
PR_GPIO4
PR_GPIO5
PR_GPIO6
PR_GPIO7
DGND
LB_A0
LB_A1
LB_A2
LB_A3
LB_A4
LB_A5
LB_A6
LB_A7
LB_A8
Internal Connections
-
-
Ball/
pin #
-
CS5536AD.GPIO8/UART1_TX/UART1_IR
_TX
CS5536AD.GPIO9/UART1_RX/UART1_IR
_RX
CS5536AD.GPIO3/UART2_RX
CS5536AD.GPIO4/UART2_TX
CS5536AD.GPIO14/SMB_CLK
CS5536AD.GPIO15/SMB_DATA
UART1_TX
E3
UART1_RX
D1
UART2_RX
UART2_TX
E1
E2
G3
F1
CS5536AD.GPIO1/AC_BEEP/MFGPT0_C
2
ALX.IRQ13
FPGA.PR16B
FPGA.PR22B
FPGA.PR22A
FPGA.PR20B
FPGA.PR21A
FPGA.PR21B
FPGA.PR24B/PCLKC2
FPGA.PT28A/PCLKT0
FPGA.PT18B
FPGA.PT24A
FPGA.PT26A
FPGA.PT18A
FPGA.PT22A
FPGA.PT5A
FPGA.PT20A
FPGA.PT22B
FPGA.PT26B
Default function
Logical GPIO32
Logical GPIO33
Logical GPIO34
Logical GPIO36
Logical GPIO36
Logical GPIO37
Logical GPIO38
Logical GPIO39
Local bus address 0
Local bus address 1
Local bus address 2
Local bus address 3
Local bus address 4
Local bus address 5
Local bus address 6
Local bus address 7
Local bus address 8
AB29
F10
F11
F13
F14
F15
F16
G14
E8
D5
D6
D7
E5
E6
F4
F5
F6
F7
Supply
Group
Voltage
Note
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO0
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
J1001 CONNECTOR - EVEN 72-140
Pin
Pin Name
Internal Connections
J1001.72
J1001.74
J1001.76
J1001.78
J1001.80
J1001.82
J1001.84
J1001.86
J1001.88
J1001.90
J1001.92
LB_A9
LB_A10
LB_A11
LB_A12
LB_A13
LB_A14
LB_A15
DGND
LB_CS#0
LB_CS#1
LB_CS#2
FPGA.PT20B
FPGA.PT30B
FPGA.PT33B
FPGA.PT35A
FPGA.PT44B
FPGA.PT46B
FPGA.PT30A
FPGA.PT33A
FPGA.PT35B
FPGA.PT46A
J1001.94
LB_CS#3
FPGA.PT32A
J1001.96
J1001.98
J1001.100
J1001.102
J1001.104
J1001.106
J1001.108
J1001.110
LB_CS#4
LB_CS#5
DGND
DDC_DAT
DDC_CLK
ETH_LED_LINK1000
ETH_LED_TX
VBAT
J1001.112
J1001.114
J1001.116
J1001.118
J1001.120
J1001.122
J1001.124
J1001.126
DGND
TSC_XP
TSC_YP
TSC_XM
TSC_YM
TSC_AUX
DGND
PWRBTN#
J1001.128
J1001.130
J1001.132
J1001.134
J1001.136
J1001.138
J1001.140
PCI_RST#
JTAGTDI
JTAGTMS
JTAGTDO
JTAGTCK
RST_IN#
DGND
FPGA.PT36A
FPGA.PT44A
FPGA.PT29B/PCLKC1
FPGA.PT29A/PCLKT1
Function
Local bus address 9
Local bus address 10
Local bus address 11
Local bus address 12
Local bus address 13
Local bus address 14
Local bus address 15
Local bus chip select 0
Local bus chip select 1
Local bus ALE
associated to LB_CS#1
Local bus buffer control
associated to LB_CS#1
Local bus chip select 4
Local bus chip select 5
-
CS5536AD.VBAT
Ball/
pin #
G6
A9
A10
A11
A12
A13
B9
B10
B11
B13
Supply
Group
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
Voltage
Note
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
VCCIO1
VCCIO1
VCCIO1
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
C9
VCCIO1
3.3 V
See Section 7.2.1 on page 36 for more details
C10
C11
A8
B8
VCCIO1
VCCIO1
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
VCCIO1
VCCIO1
3.3 V
3.3 V
A3
CS5536 Real-Time Clock Battery Back-Up.
See CS5536 Databook for current
consumption.
See also section 7.1.4 on page 36.
See also section 7.1.4 on page 36.
See also section 7.1.4 on page 36.
See also section 7.1.4 on page 36.
See also section 7.1.4 on page 36.
CS5536AD.GPIO28/PWR_B
UT#
CS5536AD.RESET_OUT#
PWR_BUT#
-
-
A8
A5
-
J1002 CONNECTOR - ODD 1-69
Pin
Pin Name
Internal Connections
J1002.1
J1002.3
J1002.5
J1002.7
IDE_CLK
IDE_IRQ
IDE_RST#
IDE_RDY
CS5536AD.MHZ66_CLK
CS5536AD.GPIO2/IDE_IRQ0
CS5536AD.IDE_RESET#
CS5536AD.IDE_RDY0/FLASH_IOCHRDY/FLA
SH_RDY/BUSY#
J1002.9
J1002.11
J1002.13
J1002.15
J1002.17
J1002.19
J1002.21
J1002.23
J1002.25
J1002.27
J1002.29
J1002.31
J1002.33
J1002.35
J1002.37
J1002.39
J1002.41
J1002.43
J1002.45
J1002.47
J1002.49
J1002.51
IDE_DASP#
IDE_PDIAG#
DGND
IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
DGND
IDE_IOW#
IDE_CS0#
J1002.53
IDE_CS1#
J1002.55
IDE_A0
J1002.57
J1002.59
J1002.61
IDE_A1
IDE_A2
IDE_ACK#
J1002.63
IDE_DRQ#
J1002.65
J1002.67
J1002.69
IDE_IOR#
DGND
NIDE_AD15
CS5536AD.GPIO5/MFGPT1_RS/MFGPT0_C1
CS5536AD.IDE_DATA0/FLASH_AD10/IO0
CS5536AD.IDE_DATA1/FLASH_AD11/IO1
CS5536AD.IDE_DATA2/FLASH_AD12/IO2
CS5536AD.IDE_DATA3/FLASH_AD13/IO3
CS5536AD.IDE_DATA4/FLASH_AD14/IO4
CS5536AD.IDE_DATA5/FLASH_AD15/IO5
CS5536AD.IDE_DATA6/FLASH_AD16/IO6
CS5536AD.IDE_DATA7/FLASH_AD17/IO7
CS5536AD.IDE_DATA8/FLASH_AD18/AD3
CS5536AD.IDE_DATA9/FLASH_AD19/AD4
CS5536AD.IDE_DATA10/FLASH_AD20/AD5
CS5536AD.IDE_DATA11/FLASH_AD21/AD6
CS5536AD.IDE_DATA12/FLASH_AD22/AD7
CS5536AD.IDE_DATA13/FLASH_AD23/AD8
CS5536AD.IDE_DATA14/FLASH_AD24/AD9
CS5536AD.IDE_DATA15/FLASH_ALE
CS5536AD.IDE_IOW0#/FLASH_WE#
CS5536AD.IDE_CS0#/FLASH_CS0#/FLASH_
CE0#
CS5536AD.IDE_CS1#/FLASH_CS1#/FLASH_
CE1#
CS5536AD.IDE_AD0/FLASH_AD25/AD0/FLAS
H_CLE
CS5536AD.IDE_AD1/FLASH_AD26/AD1
CS5536AD.IDE_AD2/FLASH_AD27/AD2
CS5536AD.IDE_DACK0#/FLASH_CS3#/FLAS
H_CE3#
CS5536AD.IDE_DREQ0/FLASH_CS2#/FLASH
_CE2#
CS5536AD.IDE_IOR0#/FLASH_RE#
-
Function
IDE_RDY0
Ball/
pin #
A10
B12
F15
A13
IDE_DATA0
IDE_DATA1
IDE_DATA2
IDE_DATA3
IDE_DATA4
IDE_DATA5
IDE_DATA6
IDE_DATA7
IDE_DATA8
IDE_DATA9
IDE_DATA10
IDE_DATA11
IDE_DATA12
IDE_DATA13
IDE_DATA14
IDE_DATA15
IDE_IOW#
IDE_CS0#
D3
B14
A15
C15
C16
B17
D15
E15
E16
E17
D17
D16
C17
A17
B16
B15
C14
C13
B10
IDE_CS1#
C10
IDE_AD0
A11
IDE_AD1
IDE_AD2
IDE_DACK0#
A12
B11
C12
IDE_DREQ0
A14
IDE_IOR0#
-
B13
-
Supply
Group
Voltage
Note
J1002 CONNECTOR - ODD 71-139
Pin
Pin Name
J1002.71
J1002.73
J1002.75
J1002.77
J1002.79
J1002.81
J1002.83
J1002.85
J1002.87
J1002.89
J1002.91
J1002.93
J1002.95
J1002.97
J1002.99
J1002.101
J1002.103
J1002.105
J1002.107
J1002.109
J1002.111
J1002.113
J1002.115
J1002.117
J1002.119
J1002.121
J1002.123
J1002.125
J1002.127
J1002.129
J1002.131
J1002.133
J1002.135
J1002.137
J1002.139
NIDE_AD14
NIDE_AD13
NIDE_AD12
NIDE_AD11
NIDE_AD10
NIDE_AD9
NIDE_AD8
NIDE_AD7
NIDE_AD6
NIDE_AD5
NIDE_AD4
NIDE_AD3
NIDE_AD2
NIDE_AD1
NIDE_AD0
DGND
NIDE_FCE7
NIDE_FCE6
NIDE_FCE5
NIDE_FCE4
NIDE_FCE3
NIDE_FCE2
NIDE_FCE1
NIDE_WP#/PD#
NIDE_WP#
NIDE_ALE
NIDE_CLE
NIDE_WE
NIDE_RE
DGND
ETH_MDI0N
ETH_MDI0P
DGND
ETH_MDI2N
ETH_MDI2P
Internal Connections
Function
Ball/
pin #
-
-
-
-
-
-
-
-
-
Supply
Group
Voltage
Note
J1002 CONNECTOR - EVEN 2-70
Pin
Pin Name
J1002.2
J1002.4
J1002.6
J1002.8
J1002.10
J1002.12
J1002.14
J1002.16
J1002.18
J1002.20
J1002.22
J1002.24
J1002.26
J1002.28
J1002.30
J1002.32
J1002.34
J1002.36
J1002.38
J1002.40
J1002.42
J1002.44
J1002.46
J1002.48
J1002.50
J1002.52
J1002.54
J1002.56
J1002.58
J1002.60
J1002.62
J1002.64
J1002.66
J1002.68
J1002.70
DGND
UART3_TX
UART3_RX
UART3_RTS
UART3_CTS
UART3_DTR
UART3_DSR
UART3_DCD
UART3_RI
DGND
UART4_TX
UART4_RX
UART4_RTS
UART4_CTS
UART4_DTR
UART4_DSR
UART4_DCD
UART4_RI
DGND
CRT_RED
CRT_GREEN
CRT_BLUE
VSYNC
HSYNC
AGND_CRT
TFT_DOTCLK
VIP_VSYNC
TFT_DISPEN
VIP_HSYNC
DGND
TFT_DRGB0
TFT_DRGB1
TFT_DRGB2
TFT_DRGB3
TFT_DRGB4
Internal Connections
FPGA.PR3A
FPGA.PR3B
FPGA.PR2B
FPGA.PR15A
FPGA.PR15B
FPGA.PR2A
FPGA.PR14A
FPGA.PR17A
FPGA.PR17B
FPGA.PR19A
FPGA.PR14B
FPGA.PR18A
FPGA.PR18B
FPGA.PR16A
FPGA.PR19B
FPGA.PR20A
ALX.RED
ALX.GREEN
ALX.BLUE
ALX.VSYNC/VOP_VSYNC
ALX.HSYNC/VOP_HSYNC
ALX.DOTCLK/VOPCLK
ALX.LDEMOD/VIP_VSYNC
ALX.DISPEN/VOP_BLANK
ALX.VDDEN/VIP_HSYNC
ALX.DRGB0/VOP7
ALX.DRGB1/VOP6
ALX.DRGB2/VOP5
ALX.DRGB3/VOP4
ALX.DRGB4/VOP3
Function
UART3 TX
UART3 RX
COM3 RTS
UART3 CTS
UART3 DTR
UART3 DSR
UART3 DCD
UART3 RI
UART4 TX
UART4 RX
UART4 RTS
UART4 CTS
UART4 DTR
UART4 DSR
UART4 DCD
UART4 RI
-
VSYNC
HSYNC
DOTCLK
VIP_VSYNC
TFT_DISPEN
VIP_HSYNC
DRGB0
DRGB1
DRGB2
DRGB3
DRGB4
Ball/
pin #
A14
A15
B14
B15
B16
C13
C14
C15
C16
D13
D14
D15
D16
E11
E13
E16
W3
V2
U2
AD3
AE3
AE1
AD4
AE4
AE2
AH7
AK6
AL6
AJ7
AK7
Supply
Group
Voltag
e
Note
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
See Section 7.2.1 on page 36 for more details
J1002 CONNECTOR - EVEN 72-140
Pin
Pin Name
J1002.72
J1002.74
J1002.76
J1002.78
J1002.80
J1002.82
J1002.84
J1002.86
J1002.88
J1002.90
J1002.92
J1002.94
J1002.96
J1002.98
J1002.100
J1002.102
J1002.104
J1002.106
J1002.108
J1002.110
J1002.112
J1002.114
J1002.116
J1002.118
J1002.120
J1002.122
J1002.124
J1002.126
J1002.128
J1002.130
J1002.132
J1002.134
J1002.136
J1002.138
J1002.140
TFT_DRGB5
TFT_DRGB6
TFT_DRGB7
TFT_DRGB8
TFT_DRGB9
TFT_DRGB10
TFT_DRGB11
TFT_DRGB12
TFT_DRGB13
TFT_DRGB14
TFT_DRGB15
DGND
TFT_DRGB16
TFT_DRGB17
TFT_DRGB18
TFT_DRGB19
TFT_DRGB20
TFT_DRGB21
TFT_DRGB22
TFT_DRGB23
TFT_DRGB24
TFT_DRGB25
TFT_DRGB26
TFT_DRGB27
TFT_DRGB28
TFT_DRGB29
TFT_DRGB30
TFT_DRGB31
ETH_AVDD
DGND
ETH_MDI1N
ETH_MDI1P
DGND
ETH_MDI3N
ETH_MDI3P
Internal Connections
Function
ALX.DRGB5/VOP2
ALX.DRGB6/VOP1
ALX.DRGB7/VOP0
ALX.DRGB8/VOP15
ALX.DRGB9/VOP14
ALX.DRGB10/VOP13
ALX.DRGB11/VOP12
ALX.DRGB12/VOP11
ALX.DRGB13/VOP10
ALX.DRGB14/VOP9
ALX.DRGB15/VOP8
ALX.DRGB16/VOP23
ALX.DRGB17/VOP22
ALX.DRGB18/VOP21
ALX.DRGB19/VOP20
ALX.DRGB20/VOP19
ALX.DRGB21/VOP18
ALX.DRGB22/VOP17
ALX.DRGB23/VOP16
ALX.DRGB24/VID8
ALX.DRGB25/VID9
ALX.DRGB26/VID10
ALX.DRGB27/VID11
ALX.DRGB28/VID12
ALX.DRGB29/VID13
ALX.DRGB30/VID14
ALX.DRGB31/VID15
DRGB5
DRGB6
DRGB7
DRGB8
DRGB9
DRGB10
DRGB11
DRGB12
DRGB13
DRGB14
DRGB15
DRGB16
DRGB17
DRGB18
DRGB19
DRGB20
DRGB21
DRGB22
DRGB23
DRGB24
DRGB25
DRGB26
DRGB27
DRGB28
DRGB29
DRGB30
DRGB31
Ball/
pin #
AL7
AH8
AJ8
AJ2
AK3
AL3
AH5
AJ4
AL4
AK4
AJ5
AF2
AF1
AG3
AG4
AH1
AH2
AH3
AJ1
AH11
AJ11
AK10
AL10
AJ10
AH10
AL9
AK9
-
-
-
-
-
-
Supply
Group
Voltage
Note
J1000 CONNECTOR - ODD 1-69
Pin
Pin Name
J1000.1
J1000.3
J1000.5
J1000.7
J1000.9
VIP_D0
VIP_D2
VIP_D4
VIP_D6
VIP_VSYNC
J1000.11
J1000.13
J1000.15
J1000.17
DGND
VIP_CLK
DGND
LVDS_I_N1
Internal Connections
Primary
Secondary
ALX.VID0
ALX.VID2
ALX.VID4
ALX.VID6
ALX.DEMOD/VIP_V
SYNC
ALX.VIPCLK
FPGA.PR29B
-
J1000.19
LVDS_I_P1
FPGA.PR29A
J1000.21
J1000.23
DGND
LVDS_I_N3
J1000.25
Function
VID0
VID2
VID4
VID6
VIP_VSYNC
Ball/pin #
Pri.
Sec.
AJ15
AK15
AL15
AH13
AD4
-
Supply
Group
Voltage
Note
VIPCLK
LVDS input pair #1 -
AL12
J12
-
VCCIO3
2.5 V
Optional termination resistor (100 Ω)
connected to LVDS_I_P1
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_I_N1
See Section 7.2.1 on page 36 for more
details
-
LVDS input pair #1
+
J13
-
VCCIO3
2.5 V
FPGA.PR33B
-
LVDS input pair #3 -
L14
-
VCCIO3
2.5 V
LVDS_I_P3
FPGA.PR33A
-
LVDS input pair #3
+
L15
-
VCCIO3
2.5 V
J1000.27
J1000.29
DGND
LVDS_IO_N0
FPGA.PL15B
-
unused
D1
-
VCCIO7
2.5 V
J1000.31
LVDS_IO_P0
FPGA.PL15A
-
unused
C1
-
VCCIO7
2.5 V
J1000.33
J1000.35
DGND
LVDS_IO_N2
FPGA.PL19B
-
unused
H1
-
VCCIO7
2.5 V
J1000.37
LVDS_IO_P2
FPGA.PL19A
-
unused
G1
-
VCCIO7
2.5 V
J1000.39
J1000.41
DGND
LVDS_IO_N4
FPGA.PL23B
-
unused
K6
-
VCCIO7
2.5 V
Optional termination resistor (100 Ω)
connected to LVDS_I_P3
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_I_N3
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_P0
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_N0
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_P2
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_N2
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_P4
See Section 7.2.1 on page 36 for more
details
J1000.43
LVDS_IO_P4
FPGA.PL23A
-
unused
H5
-
VCCIO7
2.5 V
Optional termination resistor (100 Ω)
connected to LVDS_IO_N4
See Section 7.2.1 on page 36 for more
details
J1000.45
J1000.47
DGND
LVDS_IO_N6
FPGA.PL28B
-
LVDS input pair -
K1
-
VCCIO6
2.5 V
J1000.49
LVDS_IO_P6
FPGA.PL28A
-
LVDS input pair +
K2
-
VCCIO6
2.5 V
Optional termination resistor (100 Ω)
connected to LVDS_IO_P6
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_N6
See Section 7.2.1 on page 36 for more
details
J1000.51
J1000.53
DGND
LVDS_IO_N8
FPGA.PL32B
-
unused
N1
-
VCCIO6
2.5 V
J1000.55
LVDS_IO_P8
FPGA.PL32A
-
unused
M1
-
VCCIO6
2.5 V
J1000.57
J1000.59
DGND
LVDS_IO_N10
FPGA.PL37B
-
unused
P2
-
VCCIO6
2.5 V
J1000.61
LVDS_IO_P10
FPGA.PL37A
-
unused
R1
-
VCCIO6
2.5 V
J1000.63
J1000.65
J1000.67
J1000.69
DGND
LVDS_O_N1
LVDS_O_P1
DGND
FPGA.PR35B
FPGA.PR35A
-
-
-
L12
L13
-
-
VCCIO3
VCCIO3
2.5 V
2.5 V
-
Optional termination resistor (100 Ω)
connected to LVDS_IO_P8
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_N8
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_P10
See Section 7.2.1 on page 36 for more
details
Optional termination resistor (100 Ω)
connected to LVDS_IO_N10
See Section 7.2.1 on page 36 for more
details
J1000 CONNECTOR - ODD 71-139
Pin
Pin Name
LVDS_O_N2
Internal Connections
Primary
Secondary
FPGA.PR32B
-
J1000.71
Function
unused
Ball/pin #
Pri.
Sec.
K13
-
Supply Group
Voltage
Note
VCCIO3
2.5 V
-
VCCIO3
2.5 V
See Section 7.2.1 on page
36 for more details
See Section 7.2.1 on page
36 for more details
J1000.73
LVDS_O_P2
FPGA.PR32A
-
unused
K14
J1000.75
J1000.77
DGND
LVDS_O_N3
FPGA.PR30B
-
unused
K11
-
VCCIO3
2.5 V
J1000.79
LVDS_O_P3
FPGA.PR30A
-
unused
J11
-
VCCIO3
J1000.81
J1000.83
DGND
LVDS_O_N4
FPGA.PR28B
-
unused
J16
-
VCCIO3
J1000.85
LVDS_O_P4
FPGA.PR28A
-
unused
J15
-
VCCIO3
J1000.87
J1000.89
J1000.91
J1000.93
J1000.95
J1000.97
J1000.99
J1000.101
J1000.103
J1000.105
J1000.107
J1000.109
J1000.111
DGND
DGND
PCI_GNT0#
PCI_GNT1#
PCI_REQ0#
PCI_REQ1#
DGND
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_M66EN
PCI_INTC#
ALX.GNT0#
ALX.GNT1#
ALX.REQ0#
ALX.REQ1#
ALX.CBE0#
ALX.CBE1#
ALX.CBE2#
ALX.CBE3#
ALX.PW1
CS5536AD.GPIO12/AC_
S_IN2/SLEEP_Y
CS5536AD.GPIO13/SLE
EP_BUT
CS5536AD.GPIO7/MFG
PT2_C1/SLEEP_X
CS5536AD.GPIO0
CS5536AD.DEVSEL#
CS5536AD.FRAME#
CS5536AD.IRDY#
CS5536AD.TRDY#
CS5536AD.STOP#
CS5536AD.RESET_OUT
#
CS5536AD.PAR
CS5536AD.MHZ48_CLK
-
FPGA.PB26B
FPGA.PB3A
FPGA.PB20A
FPGA.PB22B
FPGA.PB26A
FPGA.PB21A
FPGA.PB24B
GNT0#
GNT1#
REQ0#
REQ1#
CBE0#
CBE1#
CBE2#
CBE3#
PW1
INTC
AA28
AB30
AA29
AB31
AJ22
AL26
AH27
AH31
AJ17
J3
-
J1000.113
PCI_INTD#
-
INTD
F2
-
J1000.115
PCI_INTB#
FPGA.PB28A/PB
CLKT5
FPGA.PB25B
FPGA.PB23A
FPGA.PB25A
FPGA.PB4A
FPGA.PB27A
FPGA.PB4B
FPGA.PB21B
INTB
C2
J1000.117
J1000.119
J1000.121
J1000.123
J1000.125
J1000.127
J1000.129
J1000.131
PCI_INTA#
DGND
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_RST#
INTA
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
RESET_OUT#
J1000.133
J1000.135
J1000.137
J1000.139
PCI_PAR
DGND
CPU_48M_CLK
DGND
FPGA.PB23B
-
PAR
MHZ48_CLK
-
2.5 V
2.5 V
2.5 V
-
N9
VCCIO5
3.3 V
P4
P6
P7
P8
R4
VCCIO5
3.3 V
N8
VCCIO5
3.3 V
T8
VCCIO5
3.3 V
R2
R11
U9
R10
T10
T11
A5
T7
R6
R7
T3
R8
T4
T5
VCCIO5
3.3 V
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
U10
N17
-
T6
-
VCCIO5
3.3 V
See Section 7.2.1 on page
36 for more details
See Section 7.2.1 on page
36 for more details
See Section 7.2.1 on page
36 for more details
See Section 7.2.1 on page
36 for more details
J1000 CONNECTOR - EVEN 2-70
Pin
Pin Name
J1000.2
J1000.4
J1000.6
J1000.8
J1000.10
J1000.12
VIP_D1
VIP_D3
VIP_D5
VIP_D7
DGND
LVDS_I_N0
Internal Connections
Primary
Secondary
ALX.VID1
ALX.VID3
ALX.VID5
ALX.VID7
FPGA.PR27B
-
J1000.14
LVDS_I_P0
FPGA.PR27A
-
J1000.16
J1000.18
DGND
LVDS_I_N2
FPGA.PR31B
J1000.20
LVDS_I_P2
J1000.22
J1000.24
Function
Ball/pin #
Pri.
Sec.
AK15
AH13
AK13
AK12
H13
-
Supply
Group
Voltage
Note
VCCIO3
2.5 V
LVDS input pair #0
+
J14
-
VCCIO3
2.5 V
Optional termination resistor (100
Ω) connected to LVDS_I_P0
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_I_N0
See Section 7.2.1 on page 36 for
more details
-
unused
K16
-
VCCIO3
2.5 V
FPGA.PR31A
-
unused
K15
-
VCCIO3
2.5 V
DGND
LVDS_I_N4
FPGA.PR48B
-
LVDS input pair #4 -
N14
-
VCCIO3
2.5 V
J1000.26
LVDS_I_P4
FPGA.PR48A
-
LVDS input pair #4
+
N13
-
VCCIO3
2.5 V
J1000.28
J1000.30
DGND
LVDS_IO_N1
FPGA.PL17B
-
unused
F1
-
VCCIO7
2.5 V
J1000.32
LVDS_IO_P1
FPGA.PL17A
-
unused
F2
-
VCCIO7
2.5 V
J1000.34
J1000.36
DGND
LVDS_IO_N3
FPGA.PL21B
-
unused
H3
-
VCCIO7
2.5 V
J1000.38
LVDS_IO_P3
FPGA.PL21A
-
unused
H2
-
VCCIO7
2.5 V
LVDS input pair #0 -
Optional termination resistor (100
Ω) connected to LVDS_I_P2
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_I_N2
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_I_P4
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_I_N4
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_P1
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_N1
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_P3
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_N3
See Section 7.2.1 on page 36 for
more details
J1000.40
J1000.42
DGND
LVDS_IO_N5
FPGA.PL26B/PCLKC
6
-
LVDS input pair -
J1
-
VCCIO6
2.5 V
J1000.44
LVDS_IO_P5
FPGA.PL26A/PCLKT6
-
LVDS input pair +
J2
-
VCCIO6
2.5 V
J1000.46
J1000.48
DGND
LVDS_IO_N7
FPGA.PL30B
-
LVDS input pair -
L2
-
VCCIO6
2.5 V
J1000.50
LVDS_IO_P7
FPGA.PL30A
-
LVDS input pair +
L1
-
VCCIO6
2.5 V
J1000.52
J1000.54
DGND
LVDS_IO_N9
FPGA.PL35B
-
unused
N2
-
VCCIO6
2.5 V
J1000.56
LVDS_IO_P9
FPGA.PL35A
-
unused
P1
-
VCCIO6
2.5 V
J1000.58
J1000.60
DGND
LVDS_O_N0
FPGA.PR37B
-
unused
N16
-
VCCIO3
2.5 V
J1000.62
LVDS_O_P0
FPGA.PR37A
-
unused
N15
-
VCCIO3
2.5 V
J1000.64
J1000.66
J1000.68
J1000.70
DGND
PCI_AD0
PCI_AD1
PCI_AD2
ALX.AD0
ALX.AD1
ALX.AD2
FPGA.PB30B
FPGA.PB34A
FPGA.PB30A
AD0
AD1
AD2
AJ19
AH19
AL20
L10
L11
M9
VCCIO4
VCCIO4
VCCIO4
3.3 V
3.3 V
3.3 V
Optional termination resistor (100
Ω) connected to LVDS_IO_P5
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_N5
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_P7
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_N7
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_P9
See Section 7.2.1 on page 36 for
more details
Optional termination resistor (100
Ω) connected to LVDS_IO_N9
See Section 7.2.1 on page 36 for
more details
See Section 7.2.1 on page 36 for
more details
See Section 7.2.1 on page 36 for
more details
J1000 CONNECTOR - EVEN 72-140
Pin
Pin Name
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
DGND
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
DGND
Internal Connections
Primary
Secondary
ALX.AD3
FPGA.PB36A
ALX.AD4
FPGA.PB34B
ALX.AD5
FPGA.PB46B
ALX.AD6
FPGA.PB32B
ALX.AD7
FPGA.PB36B
ALX.AD8
FPGA.PB45A
ALX.AD9
FPGA.PB32A
ALX.AD10
FPGA.PB33B
ALX.AD11
FPGA.PB46A
ALX.AD12
FPGA.PB45B
ALX.AD13
FPGA.PB38B
ALX.AD14
FPGA.PB44B
ALX.AD15
FPGA.PB29B
-
J1000.72
J1000.74
J1000.76
J1000.78
J1000.80
J1000.82
J1000.84
J1000.86
J1000.88
J1000.90
J1000.92
J1000.94
J1000.96
J1000.98
J1000.10
0
J1000.10
2
J1000.10
4
J1000.10
6
J1000.10
8
J1000.11
0
J1000.112
J1000.114
J1000.116
J1000.118
J1000.120
J1000.122
J1000.124
J1000.126
J1000.128
J1000.130
J1000.132
J1000.134
J1000.136
J1000.138
J1000.140
PCI_AD16
ALX.AD16
PCI_AD17
Function
Supply
Group
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
Voltage
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
-
Ball/pin #
Pri.
Sec.
AK20
M11
AK19
M12
AH21
M13
AJ21
N10
AL19
N11
AK22
N12
AL22
P10
AK23
P11
AH22
P13
AL23
P14
AL25
P15
AH24
P16
AJ24
R10
-
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
FPGA.PB31B
AD16
AJ28
R11
VCCIO4
3.3 V
ALX.AD17
FPGA.PB35B
AD17
AK28
R13
VCCIO4
3.3 V
PCI_AD18
ALX.AD18
FPGA.PB37B
AD18
AL29
R14
VCCIO4
3.3 V
PCI_AD19
ALX.AD19
FPGA.PB38A
AD19
AJ30
R15
VCCIO4
3.3 V
PCI_AD20
ALX.AD20
FPGA.PB44A
AD20
AK29
R16
VCCIO4
3.3 V
PCI_AD21
PCI_AD22
PCI_AD23
DGND
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
DGND
EXT_14M_CLK
DGND
ALX.AD21
ALX.AD22
ALX.AD23
ALX.AD24
ALX.AD25
ALX.AD26
ALX.AD27
ALX.AD28
ALX.AD29
ALX.AD30
ALX.AD31
-
FPGA.PB28B
FPGA.PB31A
FPGA.PB33A
FPGA.PB35A
FPGA.PB37A
FPGA.PB5B
FPGA.PB5A
FPGA.PB24A
FPGA.PB3B
FPGA.PB20B
FPGA.PB22A
-
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
-
AJ31
AH30
AH29
AG29
AG28
AF30
AE28
AF31
AE30
AE31
AD29
-
R9
T11
T12
T13
T14
L8
L9
M8
N5
N6
N7
-
VCCIO5
VCCIO4
VCCIO4
3.3 V
3.3 V
3.3 V
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
-
-
-
-
-
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Note
DAVE
7 Resource allocation and FPGA notes
7.1 Resource allocation
This section describes how the resources are allocated in terms of memory regions and IRQs.
7.1.1 Simplified memory map
Memory mapping is dynamically performed by OpenFirmware during system initialization. As general rule,
system RAM shall be mapped at virtual address 0. About PCI bus, memory mapping depends on how many
devices are detected during enumeration. For the device implemented in FPGA the scheme depicted in Fig. 8
applies.
BAR0 (1 MB)
configuration
1 MB
BAR1 (256 MB)
Function 0 (4 MB)
128 MB
Function 1 (4 MB)
Function 2 (4 MB)
...
Function 30 (4 MB)
Reserved (4 MB)
Local bus CS0 (user programmable)
128 MB
Local bus CS1 (user programmable)
Local bus CS5 (user programmable)
Fig. 8: FPGA PCI device memory mapping
Whole memory space devoted to FPGA is divided in two main regions whose base address is defined by BAR0
and BAR1 respectively4. Region 0 is 1 MB and is used to map configuration registers. Region 1 is 256 MB and is
split in two 128MB subregions. First subregion provides 32 4 MB areas each of which is associated with one of the
integrated peripherals (for example Function 0 is associated to GPIO controller, Function 1 to Ethernet MAC
controller and so on). Second sub region is associated is split in 6 areas. Each areas is associated to one of the 6
chip selects provided by the PCI-to-LocalBus bridge. For more details please see section 7.2.1.1 on page 37.
7.1.2 IRQs
IRQs routing is performed by OpenFirmware during system initialization. IRQ routing and configuration is
extremely flexible as described in section “Programmable Interrupt Control” of CS5536 Databook. Most of the 16
available IRQs are allocated for CS5536 native peripherals. About FPGA, it requires IRQ 11. This means that all
the peripherals integrated in FPGA will share this IRQ. FPGA device drive will handle IRQ sharing. When FPGA
IRQ is issued, it will scan all the peripherals in order to detect which peripheral(s) has (have) requested CPU
attention.
4
BAR stands for Base Address Register.
35
DAVE
7.1.3 Temperature sensor
Neptune module provides on-board National LM86 temperature sensor5. This component allows to measure
local temperature – by the sensor it integrates – and remote Geode die temperature by the differential pins D+/Dthat are connected to Geode internal diode. It connected to the CS5536 I2C bus and its 7-bit address is 0x4C.
ALERT# output is connected to CS5536 GPIO10 pin.
7.1.4 Touch screen controller
Neptune module provides on-board Texas Instruments TSC2007 touch screen controller6. It is connected to
CS5536 I2C bus and its 7-bit address is 0x48. PENIRQ# output is connected to CS5536 GPIO24 pin. Touch
membrane interface pins are available on connector as shown by pinout table in section 6.2 page 20.
7.2 FPGA notes
7.2.1 FPGA external interfaces
This section provides an overview about the building blocks implemented in default FPGA configuration
delivered with Neptune Development Kit (bitstream file is ndk-x.y.x) and how they interface to Neptune
connectors. FPGA, by definition, can be modified in order to implements custom interfaces and
peripherals. User who are interested in FPGA customization are invited to contact technical support at [email protected].
Default bitstream provides a PCI bridge that maps integrated peripherals in the PCI memory space. These
peripherals are (see also Fig. 9 on page 37):
1. 16550-compatible UART (x2)
2. Ethernet 10/100/1000 MAC controller
3. local bus controller
4. LVDS I/O port
5. 8-bit GPIO port
Also FPGA provides RS485 automatic direction signal driver. More details can be found in section 7.2.1.2 on
page 37.
5
6
For more information about this chip please refer to http://www.national.com/mpf/LM/LM86.html.
For more information about this chip please refer to http://focus.ti.com/docs/prod/folders/print/tsc2007.html.
36
DAVE
PCI 32 bit
33/66 MHz
PCI
bridge
RS485 RS485
TXD TX EN
Full 8-wire
RS232
RS485
automatic
TX enable
Full 8-wire
RS232
UART
16550
UART
16550
LVDS
I/O PORT
Interconnection module
Gigabit
Ethernet
controller
GPIO
(1):
External
BUS
interface
GPIO
8051-like
BUS
interface
Local
BUS (1)
Lattice XP2 17
this allows glueless connection with non-PCI devices
Fig. 9: FPGA internal block diagram (default bitstream)
7.2.1.1 Local bus controller
This controller provides a “local bus” composed by the following signals:
•
16-bit data bus
•
16-bit address bus
•
RD# signal (read)
•
WR# signal (write)
•
3 standard chip selects (programmable timing)
•
1 8051-like chip select
This controller allows seamlessly connection to non-PCI devices making them accessible in the PCI
addressing space by Geode processor.
The 8051-like chip select is used to connect devices that provide 8051-like bus such as SJA1000 CAN
controller. This chip select works in conjunction with ALE signal to drive an external latch used to compose the 16bit address. Also a buffer control signal is provided to cope with application that require a further buffer to interface
to 5V logic. By default these signals are mapped as shown in section 8.4 on page 44.
For more details please contact technical support at [email protected].
7.2.1.2 RS485 automatic direction signal driver
The majority of RS485 interface implementations used in industrial applications work with 2-wire cables and
half-duplex communication. For this reason it is necessary to drive a direction signal to alternatively enable
receiver or transmitter of RS485 transceiver. The RS485 automatic direction signal driver implemented in FPGA
37
DAVE
performs this task. By detecting the falling edges of TX UART signal, it shall set the RS485_TX_ENABLE signal to
high for one baud time. This signal, in turn, can be used to enable the transmitter of external RS485 transceiver.
Please note that the supported baud rates are in the range 9600 Bps – 115200 Bps and that it is required the
RS485 cable interface provides proper polarization. This means that, when the transmitter is disabled,
polarization network must guarantee a “1” logic level on the bus. By default, signals used to implement this
feature are mapped on pins PR_GPIO0 and PR_GPIO1 as shown in Fig. 11 on page 41.
For more details please contact technical support at [email protected].
38
DAVE
7.2.2 On-board FPGA JTAG interface
Three pins that are available externally are also used internally to implement FPGA JTAG interface and to
allow processor to download FPGA bitstream. For this reason particular attention must be paid if using these
pins on host board for other functions, especially about GPIO25.
Logically they are connected as shown in Fig. 4. FPGA JTAG interface is enabled by setting GPIO25 low.
When this signal is low, GPIO10, GPIO6 and GPIO27 are connected to FPGA through tri-state buffers (GPIO25 is
also internally pulled-up to 3.3V through 10 kOhm resistor). In case any of these pins is used externally, system
designer must design external circuitry in order to avoid possible electrical conflicts or system malfunctions.
The following list indicates how these pins are pulled up/down internally:
•
GPIO25: 10 kOhm pull-up to 3.3V (always active)
•
GPIO27: 4.7 kOhm pull-up to 3.3V (active when GPIO25 is low only)
Please note that, when on-board flash ID is set to 1, Geode processor is not able to access FPGA JTAG
interface (see also section 8.9 on page 49).
GPIO6 (TDI)
GPIO27 (TMS)
GPIO10 (TCK)
GPIO25 (JTAG_EN)
To External Main
Connectors
Fig. 10: Internal FPGA JTAG connections
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8 Host board design guidelines
This chapter provides several examples (derived from real-life systems) showing how to implement I/O
interfaces and functions on the board hosting Neptune processor module 7. These examples are provided as
reference. Different implementations can/must be used depending on actual host board requirements and
configurations.
The list of the examples provided is the following:
●
●
●
●
●
●
●
●
●
7
UARTS (RS232/RS485)
VGA
Local Bus
Ethernet
USB Host
AC97 Audio
Compact Flash
Second Boot Flash
Geode JTAG
This board is often referred as “host board” or “carrier board”.
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DAVE
8.1 UARTs (RS232/RS485)
Fig. 11 shows a possible solution about UARTs interfaces. The three UARTs depicted work as follow:
•
UART1 (CS5536 native): 2-wire RS232
•
UART2 (CS5536 native): half-duplex RS485 with automatic direction (see also section 7.2.1.2 on page
37)
•
UART3 (FPGA): 8-wire RS232
Fig. 11: UARTs reference schematic
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DAVE
8.2 VGA
Fig. 12: VGA reference schematic
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8.3 Local bus (standard chip select)
The example of Fig. 13 shows how to connect a device (a SMSC LAN9217 ethernet controller in this case) to
local bus through CS0.
Fig. 13: Standard local bus chip select reference schematic
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DAVE
8.4 Local bus (8051-like chip select)
Fig. 14: 8051-like local bus chip select reference schematic
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8.5 Ethernet
Fig. 15 shows reference schematic for Ethernet interface. Please note that it is strongly recommended to
implement a PCB copper keepout area under the RJ45 connector as shown in Fig. 16.
Fig. 15: Ethernet reference schematic
Fig. 16: Ethernet PCB copper keepout area
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DAVE
8.6 USB host
Fig. 17: USB host reference schematic
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8.7 AC97 audio
Fig. 18: AC97 codec reference schematic
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8.8 CompactFlash
Fig. 19: CompactFlash reference schematic
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DAVE
8.9 Second boot flash (dual-boot function)
Fig. 20: External LPC flash reference schematic
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DAVE
8.10 Geode JTAG
The following picture shows processor JTAG interface implementation. Please note the use of jumper J16. In
case of debug performed via JTAG interface, this jumper must be closed in order to halt the processor and to
allow debugger to take control of it.
Fig. 21: Geode JTAG reference schematic
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9 Naming, order codes and standard releases
Each Neptune module report a marking code label on top side that identify the specific model according to
order code.
Product: Neptune
Code structure
DN
p
s
Family
Processor
DDR
RAM Flash NAND
memory
n
DN= Dave
Neptune
D = LX700
(433Mhz)
8 =
256MB
E = LX800
(500Mhz)
9 =
512MB
f
c
t
n
iiii
FPGA
Connectors
Temperature
range
Submodel
Identifier
1= 17 Kluts, LVDS
input Port
0 = full
connectors
C = commercial
(0/+70°C)
See table
below
Combined with other
fields, identifies
univocally the product
2= 17Kluts NO
LVDS, GPIO Port
0 = 2
connectors
I =
industrial(-40/
+85°C)
size
F = LX900
(600Mhz)
0=NO NAND,
NO NAND
CONTOLLER
2=128Mbyte
A=1Gbyte
3= 30 Kluts, LVDS
input Port
4= 30 Kluts, NO
LVDS, GPIO Port
Submodel
Description
0
CS021008A
Valid combinations (for combinations not listed here please contact our sales department)
DNE8210C0R
Geode LX800 (500MHz), 256MB RAM, 128 MB NAND Flash, 17Kluts, LVDS input port,
Commercial temperature range, Rohs compliant
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10 Agency approvals
The following tests have been considered inherent and applicable:
•
•
•
•
•
•
EN 55022
EN 61000-4-3
EN 61000-4-4
EN 61000-4-4
EN 61000-4-6
EN 61000-4-6
:
:
:
:
:
:
Emission of radiated disturbances tbd
Immunity to RF electromagnetic fields tbd
Immunity to fast transient bursts (mains) tbd
Immunity to fast transient bursts (communication lines) tbd
Immunity to RF conducted disturbances (mains) tbd
Immunity to RF conducted disturbances (communication lines) tbd
Test reports (tbd) available on request.
11 Support
To contact technical support, please send an e-mail to address [email protected]
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