Application Report
SPRA975B − May 2004
Interfacing an LCD Controller to a DM642 Video Port
Adit Sahasrabudhe
DSP Field Applications
ABSTRACT
There is an increasing demand to bring video and image processing capabilities to devices
like video IP phones, cellular phones, and personal data assistants (PDAs). The images are
brought to the user on liquid crystal displays that usually use thin film transistor (TFT)
technology. These LCD devices require very specific timings and row/column formatting that
can make them difficult to directly interface. For this reason, we recommend that you use an
LCD controller. Most LCD controllers require little more input than raw RGB data. Some
require horizontal and vertical sync signals, while others remove even that need. LCD
controllers take care of any timing requirements and row/column formatting.
With their ability to output raw RGB data and horizontal/vertical sync signals, the DM642’s
video ports have the necessary functionality to seamlessly interface to TFT LCD controllers.
Therefore, we have decided to show how to interface the DM642’s video ports to an LCD
controller, instead of directly to an LCD module. This application report details how to
program the DM642’s video ports to meet LCD controller requirements.
Specific examples will be provided using the NEC S1L50282F23K100 LCD controller
interfacing to the NEC NL2432HC22-22A LCD module. Hardware schematics and software
driver collateral is also included.
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 DM642 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 NEC S1L50282F23K100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Power-ON Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Video Port to S1L50282F23K100 Interface Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.2 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Achieving Higher Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Video System Hardware Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Appendix A S1L50282F23K100 Daughtercard Schematics for DM642 EVM . . . . . . . . . . . . . . . . 11
List of Figures
Figure 1. General System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Trademarks are the property of their respective owners.
1
SPRA975B
Figure 2. LCD Controller and Module Power-ON Sequencing Requirement . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Data Enable Signal Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Display Area with DE Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure A−1. Schematic Title Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure A−2. Power Supply Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure A−3. LCD Backlight Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure A−4. DM642 EVM Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure A−5. Video Port Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure A−6. S1L50282F23K100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure A−7. Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
List of Tables
Table 1. Video Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. NEC S1L50282F23K100 Input and Output Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. DM642 Video Port to THS8200 Hardware Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1
Introduction
This application report describes how to connect an LCD controller to a DM642 video port. The
design consists of an NEC S1L50282F23K100 LCD controller. We also use an NEC
NL2432HC22-22A LCD module that interfaces to the controller only, not the DM642. The
S1L50282F23K100 has an 18-bit digital RGB interface which can provide a target resolution in
landscape or portrait of 240x320 or 320x240, respectively. The NL2432HC22-22A is an
amorphous silicon transflective TFT LCD display which supports 262,144 colors at a resolution
of 320x240.
2
Design Specifications
The architecture used to interface the video port and the S1L50282F23K100 is shown in the
diagram below. We have added the NL2432HC22-22A into the diagram as well for
completeness.
2
Interfacing an LCD Controller to a DM642 Video Port
SPRA975B
DM642
NL2432HC22−22A
S1L50282F23K100
Video Port
RAI5
RAI4
RAI3
RAI2
RAI1
RAI0
VD19
VD18
VD17
VD16
VD15
VD14
VD13
VD12
GAI5
GAI4
GAI3
GAI2
GAI1
GAI0
VD9
VD8
VD7
VD6
VD5
VD4
VD3
VD2
BAI5
BAI4
BAI3
BAI2
BAI1
BAI0
VCLK2 (VCLKOUT)
6
RAO[5:0]
D0[5:0]
6
GAO[5:0]
BAO[5:0]
D1[5:0]
6
D2[5:0]
H Driver
INV
HCK
INV
HCK
HSP
DLP
PC
HOE
HSP
STB
POL
V Driver
VCK
VCK
VSP
VSP
VOE
VOE
DCK
VCTL0 (HSYNC)
DE
OEN
POC
OEN
VCC
INVSE
HDRSE
PCI
PCSE
PANS
DSE
CKS
HOEPW
Figure 1. General System Architecture
2.1
DM642 Video Port
The video port peripheral is an 8/10/16/20-bit parallel video capture or video display interface.
Each video port has a channel A and channel B. Either both channels must be inputs or both
must be outputs. When configured for 8/10-bit BT.656 mode, the capture can input two separate
channels on A and B. The channels can be used together to create a single 16/20-bit
input/output. For example, the A display port can be used to output 16/20-bit raw RGB data. It is
this raw data output capability which we are going to take advantage of in this application report.
Interfacing an LCD Controller to a DM642 Video Port
3
SPRA975B
In addition to being able to receive and transmit a variety of data formats, the video port
peripheral has a separate clock for each channel and can supply a range of control signals like
active video, horizontal and vertical sync, and composite sync, to name a few.
For more information on control signals, supported standards, and general video port operation,
please see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference
Guide (SPRU629).
Table 1. Video Port Signals
Signal Name
Description
VD[19:12]
Upper bits of Video Data Out
VD[9:2]
Lower bits of Video Data Out
VCLK2 (VCLKOUT)
Video Port output clock
VCTL0 (AVID)
Active Video
NOTE: This is only a list of video port pins used in this design. For a complete listing,
please see SPRU629. Also, VD[11:10, 1:0] are only used in 10/20-bit mode. They
allow for fractional values used in BT.656 operation. When in 8/16-bit mode, they
are ignored.
2.2
NEC S1L50282F23K100
The NEC S1L50282F23K100 is an LCD controller used to interface to QVGA/HVGA LCD
modules. This controller, like other LCD controllers, is used to drive the horizontal and vertical
gates on an LCD module, adjusting the row/column formatting as is necessary. While doing this,
it is also used to control the distinct timing required between data and control signals. The input
and output data format is 6-bit x 3 (RGB) parallel.
This particular controller was used because of the low number of input signals required for
operation. The input and output signals are described in Table 2.
4
Interfacing an LCD Controller to a DM642 Video Port
SPRA975B
Table 2. NEC S1L50282F23K100 Input and Output Signal Descriptions
Signal Name
I/O
Description
RAI[5:0]
I
6-bit red value, 2.5MHz
GAI[5:0]
I
6-bit green value, 2.5MHz
BAI[5:0]
I
6-bit blue value, 2.5MHz
DCK
I
Clock, 5MHz
DE
I
Data Enable, 18.75kHz − Used to signify when data is enabled for every
horizontal line
OEN
I
Output Enable, DC – Enable the horizontal and vertical gate driver output
POC
I
Power on Clear – Enables or disables device reset (0: reset; 1: reset off)
RAO[5:0]
O
6-bit red value
GAO[5:0]
O
6-bit green value
BAO[5:0]
O
6-bit blue value
INV
O
Output data inversion signal, 2.5MHz – Allows you to invert the data going to
the LCD module
HCK
O
Clock for horizontal gate driver
HSP
O
Horizontal driver start pulse
DLP
O
Horizontal driver latch pulse
PC
O
Polarity Change
HOE
O
Source-driver output enable
VCK
O
Vertical driver clock
VSP
O
Vertical driver start pulse
VOE
O
Vertical driver output enable
INVSE
I
Not used here, please see the product data sheet.
HDRES
I
Not used here, please see the product data sheet.
PCI
I
Not used here, please see the product data sheet.
PCSE
I
Not used here, please see the product data sheet.
PANS
I
Not used here, please see the product data sheet.
DSE
I
Not used here, please see the product data sheet.
CKS
I
Not used here, please see the product data sheet.
HOEPW
I
Not used here, please see the product data sheet.
Interfacing an LCD Controller to a DM642 Video Port
5
SPRA975B
2.2.1
Power-ON Sequencing
The following supply voltage timings should be met for the LCD controller and module. Their
voltages are interdependent; therefore, the signals below are specific to either the controller or
the module. See Figure 2 to find out which signal applies to which part.
V
VGON
>90%
OEN VCC
>90%
Logic Signals
t
>0
>0
>0
>0
>0
>90%
Signal
Value
Description− Module
VGON
+15 V
V driver (+) supply voltage − Module
VGOFF
−15 V
V driver (−) supply voltage − Module
VDD
+4.5 V
H driver supply voltage − Module
VCC
+3.0 V
Logic supply voltage − Controller and Module
OEN
+3.0 V
Output enable signal − Controller
VGOFF
Figure 2. LCD Controller and Module Power-ON Sequencing Requirement
2.3
Video Port to S1L50282F23K100 Interface Details
We will now address some of the details involving the output signals from the DM642 video port
to the input of the S1L50282F23K100.
2.3.1
Data Interface
The S1L50282F23K100 requires a 18-bit input (R:G:B → 6:6:6). TI has developed Y:Cr:Cb to
RGB conversion algorithms; however, these algorithms convert to a 16-bit, 5:6:5 RGB format. To
lessen the amount of software development for algorithm modification, appropriate bit-packing,
etc., we decided to use the existing RGB conversion algorithm. To accommodate the difference
in data widths, we tie together the most and least significant bits on the R and B data lines, as is
shown in Figure 1. This is a commonly used scheme in systems where you need to convert a
16-bit output to 18-bits.
2.3.2
Control Interface
DCK:
The DCK input is used to specify the clock for the controller.
6
Interfacing an LCD Controller to a DM642 Video Port
SPRA975B
DCK Implementation
The video port can generate a clock signal on its VCLK2 pin. We use this signal to provide the
controller a 5MHz clock.
DE:
The DE signal is used to generate an internal horizontal and vertical sync. This sort of scheme is
referred to as virtual timing. It does not require the CPU to provide timing information to the LCD
Controller; but only to provide an active data signal with a few timing constraints. These
constraints are defined in Figure 3.
Vsync
tvp
tvb
320H (Fixed)
1H
tvf
Hsync
DE
R0−R5
G0−G5
B0−B5
D(X,0)
D(X,Y)
D(X,319)
Invalid
DE
R0−R5
G0−G5
B0−B5
D(X,0)
Invalid
D(X,0)
D(X,0)
D(X,0)
Hsync
240CLK (Fixed)
thb
thf
thp
1CLK
CLK
DE
R0−R5
G0−G5
B0−B5
Invalid
D(0,Y) D(1,Y)
D(239,Y)
Invalid
Figure 3. Data Enable Signal Timing Requirements
Interfacing an LCD Controller to a DM642 Video Port
7
SPRA975B
The above series of timing diagrams can be summarized using the following picture:
240 dots
Invalid
Display Area
240 x 320
320
Lines
Figure 4. Display Area with DE Signal
While the data for the display area is being outputted, the data enable (DE) signal should be
high.
DE Implementation
The DM642 video ports can output an active video control signal on pin VCTL0. This signal is
high while the video port is outputting data for the current frame. This corresponds exactly to the
definition of what the DE signal should be as described above.
OEN:
The OEN input is used to enable the output of the horizontal and veritcal gate drivers to the LCD
module. In our design, we want the output to be enabled at all times, so we simply tie this signal
high.
OEN Implementation
There is one consideration with this signal and that is its timing requirement with the rest of the
power supply voltages. The OEN signal nees to be the last driven voltage in a sequence. The
idea behind this is that you want the LCD module to be up and running before the controller
starts sending it data. To achieve this, you use the TPS3801−01. The design can be seen in
Appendix A.
POC:
The POC input specifies device reset.
POC Implementation:
For our purposes, the device will come out of reset on power up, but it will always be ready
subsequently; therefore, we also tie this signal high.
8
Interfacing an LCD Controller to a DM642 Video Port
SPRA975B
2.4
Achieving Higher Resolutions
The DM642 video ports have the ability to interface to much higher resolution LCDs like SVGA
(800 x 600) and XVGA (1024 x 768). This is done simply by changing the values in the video
port display registers to reflect a larger viewing area and appropriately modified SYNC and
blanking intervals. It should be noted however, that with this particular NEC LCD controller, the
highest achievable resolution is HVGA (640 x 240). To achieve the higher resolutions on larger
LCD modules, you would need a different LCD timing controller. In fact for the larger LCD
modules, the timing controller is usually built into the device; therefore, the DM642 video port
would interface directly to the LCD module.
3
Video System Hardware Design Guidelines
To achieve good performance within the video system, some general guidelines have been
listed below. These guidelines are given in a checklist format for ease of implementation. These
techniques provide a starting point for creating a low-noise video system. Signal integrity
analysis should be done using IBIS modeling in order to help obtain optimum signal integrity and
performance.
Table 3. DM642 Video Port to THS8200 Hardware Design Checklist
Completed
j
j
j
j
j
j
j
j
j
j
Description
Power Supplies
Analog and digital power supplies should be separated.
The power supplies should have a high power supply rejection ratio (PSRR).
Multiple connections between the separate ground planes generate current loops, which
must be avoided.
Decoupling/Bypass Capacitance
Multiple decoupling capacitors should be located as close as possible to all digital ICs,
especially the video DAC and DSP.
As many 0.1-µF capacitors with low ESL/ESR should be placed near the ICs as feasible.
Bulk capacitors, on the order of 10-µF, should also be used to help filter power supply
fluctuations.
Signal Integrity
Serial termination may be necessary on all data busses, address busses, and/or
control/clock signals. Longer traces (>1.5 in.) generally require serial termination. Shorter
traces may not require termination, but
IBIS analysis can provide insight as to proper sizing and placement of termination resistors.
High speed interfaces should be kept within a reasonable length. Buses and control signals
should not vary greatly in length.
Clock lines have proper termination and do not branch off several times on a given net.
Interfacing an LCD Controller to a DM642 Video Port
9
SPRA975B
4
Conclusion
This application report demonstrates a glueless interface between a DM642 video port and an
LCD controller. The proper selection of LCD module will allow a glueless interface from the
controller to the module, as well. This design and the schematics in Appendix A have been
tested with hardware and attached software. It should be noted that this design is very specific
to the chosen NEC LCD controller and module. While the control signals reuired for most
modules will allow for DM642 video ports to be a glueless interface, so modules might require a
particular combination of control signals that could make the connection more difficult. A future
application report will contain a working example application with software.
5
References
1. TMS320DM642 Data Manual (SPRS200)
2. TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide
(SPRU629)
3. LCD Controller Type: S1L50282F23K100 (DOD-N-0195)
4. TFT Color LCD Module Type: NL2432HC22-22A (DOD-PD-0073)
5. TPS2034 Power-Distribution Switch (SLVS190)
6. Low Power DC/DC Boost Converter (SLVS413)
7. Constant Current LED Driver (SLVS441)
8. TPS77601, Fast-Transient-Response 500-mA LDO Voltage Regulator (SLVS232)
10
Interfacing an LCD Controller to a DM642 Video Port
SPRA975B
Appendix A
S1L50282F23K100 Daughtercard Schematics for DM642 EVM
Appendix A contains preliminary schematics for the S1L50282F23K100 LCD Controller
daughtercard for the DM642EVM. These schematics have yet to be tested, and they should only
be used as an example of how to interface a DM642 video port to an LCD controller. While we
have chosen the S1L50282F23K100 in our design, the general scheme is applicable to a variety
of devices.
The schematics are also inclued in PDF format within the attached .zip file.
Interfacing an LCD Controller to a DM642 Video Port
11
12
Interfacing an LCD Controller to a DM642 Video Port
CAPACITANCE VALUES ARE IN MICROFARADS
BOARD PROPERTIES
2)
3)
J. THERMAL RELIEFS SHOULD NOT BE USED
RELIEFS
0.4
0.3
0.2
0.1
12/01/2003
02/27/2004
Assigned part numbers to
diodes in power supply
design.
Switched labeling of pins 4
and 5 on TPS76301, connected
pin 2 on TPS61040 to ground,
changed C15 to be a polar Cap.
AAS
AAS
AAS
AAS
Approved
Title: LCD Daughtercard for DM642 EVM
Description: Title
Doc. #: SPRA975
0.4
Rev.:
1
Page:
of 7
Date:
Tuesday, April 20, 2004
TI
11/25/2003
10/20/2003
Date
Changed R57 Value, Added
R61 and R62, Deleted L1
Preliminary Schematics
Completed
Description
Revision History
Figure A−1. Schematic Title Page
75 OHM MATCHED IMPEDANCE FOR ANALOG LINES
I. U13 HAS A PowerPAD THAT IS CONNECTED THROUGH PIN 21
H. APPROXIMATE BOARD SIZE 5.125 x 3.125 INCHES
G. MINIMUM VIA SIZE 10/19 MILS
F. MINIMUM TRACE WIDTH/SPACING 4 MILS
E. FR4 BOARD MATERIAL
D. INNER LAYERS 1.0 OZ CU
C. OUTER LAYERS 0.5 OZ CU & 0.5 OZ AU PLATING
B. 50 OHM MATCHED IMPEDANCE FOR DIGITAL LINES.
A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE PARTS SHALL NOT USE THERMAL
RESISTANCE VALUES ARE IN OHMS
1)
Notes:
1) Title, Contents, Revision History, and Notes
2) Power Supply
3) LCD Backlight Circuit
4) DM642 EVM Daughter Card Connectors
5) Video Port Clock
6) Video Port to S1L50282F23K100 LCD Controller
7) Power Supply Decoupling
Table of Contents
Rev.#
S1L50282F23K100 LCD Controller Daughter Card for the DM642 Evaluation Module
TI
SPRA975B
5V_VCC_FILTERED
C5
10uF
R50
10k
C6
1uF
C23
1uF
C7
0.1uF
U23 EMI Filter EXC−CET103U
5V_VCC_FILTERED
5V_VCC
OUT
Gnd
Gnd
NC
NC
NC
NC
NC
/EN1
IN
IN
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
OUT
OUT
PG
1
2
3
9
10
11
12
19
13
14
16
R60
169k
R48
475k
R51
10k
C8
10uF
D2
GREEN
R52
110
C24
4.7uF TPSC475K035R0600
C12
4.7uF
4.5V_LCDVDD
C9
100uF
OEN
C10
22uF
R61
10k
4
5
6.8uH
C11
0.1uF
EN
Vin
GND
FB
SW
U15
TPS61040
L2
Figure A−2. Power Supply Design
NOTE: Connect Power Pad
to Ground through
vias
21
20
18
17
15
8
4
5
6
7
VDD_ENABLE
4
5
U13
TPS77601
EN NC/FB
GND
IN
VDD_ENABLE
3
2
1
U22
TPS76301
TP7
4.5V_VDD
1
2
3
2
3
1
R59
6.49k
R58
10k
GND
GND
3V_VCC
Vcc
RESETSENSE
U17
TPS3801_01
4
5
D3 MBR0530
C14
1uF
MBR0530
3V_LCDVCC
C13
1uF
TI
4.7uF
C15
R56
2.1k
R55
20k
TP8
TP9
VGON
VGOFF
Title: LCD Daughtercard for DM642 EVM
Description: Power
Doc. #: SPRA975
0.4
Rev.:
Page:
of 7
2
Date:
Tuesday, March 02, 2004
C19
22pF
3V_VCC
C16
0.1uF
R54
133k
R53
1.5M
D4
MBR0530
D5
SPRA975B
Interfacing an LCD Controller to a DM642 Video Port
13
14
TP1
4.5V_LCDVDD
R62
10k
C17
4.7uF
Interfacing an LCD Controller to a DM642 Video Port
SW
FB
GND
Rs
LED
CTRL OVP
Vin
2
1
7
8
R57
21
D6
Zetex ZHCS400
Figure A−3. LCD Backlight Circuit
4
6
5
3
U21
TPS61042
L3
6.8uH Sumida CDRH3D16−6R8
TI
VCathode
Title: LCD Daughtercard for DM642 EVM
Description: Backlight
Doc. #: SPRA975
Rev.:
0.4
Page:
3
of 7
Date:
Tuesday, March 02, 2004
C18
1uF
VAnode
SPRA975B
VP2CTL0_AVID
VP2CLK0_VCLKIN
VP2CLK1_VCLKOUT
5V_VCC
3.3V_VCC
VP2D2
VP2D8
VP2D6
VP2D4
VP2D12
VP2D18
VP2D16
VP2D14
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
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65
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81
83
85
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89
2
4
6
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82
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90
2
4
6
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10
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52
54
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58
60
62
64
66
68
70
72
74
76
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80
82
84
86
88
90
TFM145 −02−S−D−LC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
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61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
DC_P1
J1
J3
VP2D3
VP2D9
VP2D7
VP2D5
VP2D13
VP2D19
VP2D17
VP2D15
3.3V_VCC
5V_VCC
3.3V_VCC
TFM145−02−S−D−LC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
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81
83
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89
2
4
6
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24
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30
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36
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52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
DC_P2
J2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
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60
62
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66
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72
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80
82
84
86
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90
TFM145 −02−S−D−LC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
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53
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57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
Figure A−4. DM642 EVM Daughter Card Connectors
DISPLAY_EN
DC_P3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
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80
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84
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90
2
4
6
8
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62
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66
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90
1
3
5
7
9
11
13
15
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19
21
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25
27
29
31
33
35
37
39
41
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45
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49
51
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55
57
59
61
63
65
67
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75
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79
81
83
85
87
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1
3
5
7
9
11
13
15
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19
21
23
25
27
29
31
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35
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39
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49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
VP2D[0..19]
TI
Title: LCD Daughtercard for DM642 EVM
Description: DM642 EVM Daughtercard Connector
Doc. #: SPRAxxx
0.4
4
Rev.:
Page:
of 7
Friday, April 23, 2004
Date:
SPRA975B
Interfacing an LCD Controller to a DM642 Video Port
15
1
2
16
4
3
3.3V_VCC
Interfacing an LCD Controller to a DM642 Video Port
VP2CLK0_VCLKIN
Figure A−5. Video Port Clock
CMX309FBC5.000MTR
En Vcc
Gnd Out
U25
TI
Title: LCD Daughtercard for DM642 EVM
Description: Video Port 2 Clock
Doc. #: SPRA975
of 7
Rev.:
0.4
5
Page:
Date:
Tuesday, March 16, 2004
SPRA975B
OEN
3V_LCDVCC
VP2CTL0_AVID
VP2CLK1_VCLKOUT
TP3
3V_LCDVCC
VP2D[0..19]
TP4
TP5
TP6
VP2D2
VP2D3
VP2D4
VP2D5
VP2D6
20
100K
R18
R19
R15
20
20
20
R14
R16
R13
R11
R9
R7
R4
R2
R17
20
20
20
20
20
20
20
R12
VP2D7 R6
VP2D8
VP2D9 R8
VP2D12
VP2D13 R10
VP2D14
VP2D15 R1
VP2D16
VP2D17 R3
VP2D18
VP2D19 R5
TP2
C1
0.1UF
POWER ON CLEAR
OUTPUT ENABLE
DATA ENABLE
PIXEL CLK
20
20
20
20
20
20
20
30
29
78
27
25
75
76
71
77
73
72
70
79
69
8
6
5
4
3
2
15
13
12
11
10
9
23
22
19
18
17
16
POC
OEN
TSTEN
DE
DCK
INVSE
HDRES
PCI
PCSE
PANS0
PANS1
DSE
CKS
HOEPW
BA10
BA11
BA12
BA13
BA14
BA15
GA10
GA11
GA12
GA13
GA14
GA15
RA10
RA11
RA12
RA13
RA14
RA15
U10
S1L50282F23k100
VDD_Q4
VDD_Q3
VDD_Q2
VDD_Q1
74
61
54
41
31
21
14
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSP
VOE
VCK
BO0
BO1
BO2
BO3
BO4
BO5
GO0
GO1
GO2
GO3
GO4
GO5
RO0
RO1
RO2
RO3
RO4
RO5
INV
PC
DLP
HOE
INH
HCK
HSP
R45
R46
66
67
200
R42
200
200
200
200
R40
R44
200
200
R38
200
R36
200
200
200
200
100
200
200
R43
R41
R39
R37
R35
R33
R31
R29
R27
R25
R21
200
200
200
200
200
200
200
200
200
200
200
VCathode
VAnode
VGOFF
VGON
C2
56pF
4.5V_LCDVDD
C21
0.1uF
3V_VCC
R34
R32
R30
R28
R26
R24
R22
R20
65
42
43
44
45
46
48
49
50
51
52
53
55
56
57
58
59
62
63
34
32
35
33
36
39
37
C22
0.1uF
Figure A−6. S1L50282F23K100
80
68
64
60
47
40
38
28
26
24
20
7
3V_LCDVCC
100K
VR1
4.5V_VDD
R49
R47
120K
4.5V_VDD
3V_VCC
3V_VCC
C3
4.7uF
B0
B1
B2
B3
B4
B5
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
R5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ribbon to LCD
Panel.
3.5 x 2.75
inch area
should be
left for
panel to be
placed.
Touch Panel − Not Used
Title: LCD Daughtercard for DM642 EVM
Description: S1L50282F23K100 LCD Controller
Doc. #: SPRA975
0.4
6
Rev.:
Page:
of 7
Date:
Tuesday, March 02, 2004
TI
Back light power
GND
COM
V0
V1
V2
V3
V4
GAM
VCOM
NC
INV
POL
STB
AP
Vcc
HCK
HSP
GND
D20
D21
D22
D23
D24
D25
D10
D11
D12
D13
D14
D15
D00
D01
D02
D03
D04
D05
GND
Vdd
VCK
VGOFF
VOE
VGON
VSP
GND
YU
XR
YD
XL
CATHODE
ANODE
CN1
FH12−50S−0.5SH(05)
Supplied by Hirose Electric Co.
SPRA975B
Interfacing an LCD Controller to a DM642 Video Port
17
3V_LCDVCC
18
C20
0.01
C26
0.01
C28
0.01
C30
0.01
C4
0.01
C25
0.01
C27
0.01
Interfacing an LCD Controller to a DM642 Video Port
C29
0.01
VDD_Q4
VDD_Q3
VDD_Q2
VDD_Q1
TI
Title: LCD Daughtercard for DM642 EVM
Description: Power Supply Decoupling
Doc. #: SPRA975
0.4
Rev.:
Page:
7
of 7
Date:
Tuesday, March 02, 2004
Figure A−7. Power Supply Decoupling
C34
0.01
C33
0.01
C32
0.01
C31
0.01
SPRA975B
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