APPLICATION NOTE
An Atlas of ESD Failure Signatures in Vertical
Cavity Surface Emitting Lasers
ABSTRACT
AOC herein describes a collection of material degradation features observed
in Vertical Cavity Surface Emitting Lasers (VCSELs) that have been intentionally
degraded with a range of electrostatic discharge (ESD) stress conditions.
Failure analysis techniques employed include emission microscopy, Focused
Ion Beam (FIB) microscopy and Transmission Electron Microscopy (TEM). The
results have enabled higher confidence in root-cause determination for failed
VCSEL devices.
INTRODUCTION
The application of sophisticated characterization techniques (e.g. emission
microscopy, FIB, and TEM) to understanding VCSEL failure mechanisms has
been well documented1, and analysts continue to add to3 and improve on
these techniques4. Typically, in the absence of gross mechanical or electrical
overstress damage, these techniques often reveal that the active layers of a
failed VCSEL contain a complex patterned dislocation array1,5 . Acting as nonradiative recombination sites these arrays degrade the optical and electrical
properties of the laser device. However, while visually imposing, the dislocation
arrays represent only the final cause, not root cause of failure. Rather, nonradiative recombination of minority carriers at a defect site in the active
layers of a light emitting diode provides a positive feedback mechanism that
typically leads to the self-supporting growth of a dislocation array from that
defect site. Consequently, a single defect such as a dislocation propagating
from the substrate is able to generate a dense dislocation array that covers
the entire active region of the device.
Thus, the goal in the analysis of many failed VCSELs is to find the source
defect of the dislocation array. Once discovered, the next challenge is to
attribute that defect to some outside event, design flaw, or growth anomaly.
The emphasis of this paper is on the characterization of defects caused by
outside events, primarily Electrostatic Discharge (ESD) and minor Electrical
Overstress (EOS) events. The data shown below was generated with AOC’s
14um oxide confined devicesi though the principles described are applicable
to other VCSEL designs.
i
Human Body Model and Machine Model pulses were generated using an Oryx 700 System.
BACKGROUND
The 2004 annual Electrostatic Discharge Association (ESDA)
Symposium included no obvious representation from the
optical semiconductor device community in either the tutorial
or technical programs. Nevertheless, optical devices are susceptible to ESD events and many of the concepts discussed in the
ESDA community are as applicable to the manufacturers and
users of VCSELs as they are to the silicon IC industry6. The
following data show a range of material degradation features
in oxide confined VCSELs intentionally exposed to ESD under
laboratory conditions, the characteristics of which depend on
the type of ESD stress applied.
Several texts7,8 describe in detail these various forms of ESD
and AOC has previously shown the application of these
models to the oxide VCSEL9. Briefly, the Human Body Model
(HBM) describes the discharge of a fully charged capacitor
(~100pf ), through an inductor (~10uH) and resistor (~1500Ω)
in series with the device (where the values of the components
used are intended to represent the electrical properties of
the average human). The Machine Model (MM) describes the
discharge of a fully charged capacitor (~100pf ) through a
smaller inductor (~100nH) in series with the device. Here the
component values typify the circuit when a device is contacted
by a charged metal object. In the Charged Device Model (CDM),
the device discharges through a zero ohm, zero inductance
circuit. Figure 1 shows a comparison of the electrical signals
that a device would experience via these models.
Historically, pinpointing the exact cause of ESD damage so
that improved controls can be implemented has proven to be
notoriously difficult. However, if it is possible to determine
which type of ESD event (HBM, MM, or CDM) is associated
with a particular failure, it is then possible to determine how
the part is being exposed to ESD, thereby making it possible
to correct the issue. For example, a failure with HBM-type
damage would lead to better controls on factory employees –
e.g. wrist straps, heel straps, etc. Damage induced by MM
would indict equipment fixtures or handling tools (tweezers
for example). CDM failures would most likely be caused by
automated equipment or improper device handling which
induces charging on the devices. Thus, a means of narrowing
the search for the ESD source can lead to much faster actions
to prevent future failures.
VCSELS DAMAGED BY CHARGED HUMANS –
THE HBM EVENT
The electrostatic discharge pulse from a charged human is
slow and of lower magnitude relative to other models. Under
these conditions, current is restricted by the oxide aperture
and the highest fluxes occur in the active area, near the oxide
aperture9. Reverse bias ESD events dissipate more power than
forward bias events (i.e. due to the fact that the reverse
breakdown voltage is about an order of magnitude greater
than the forward voltage of the device) and thus, the VCSEL
has a lower threshold of damage from reverse bias events.
1.00E-05
Reverse Current (-A)
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
0
5
10
15
Reverse Bias (-V)
Figure 1. Comparison of the signals from three common ESD events.
Image courtesy of Joe Bernier, Intersil Corp.
Figure 2. Reverse Bias IV trace from a device subjected to a RB HBM
event of 500V (red) and a known good device.
Fused quantum
wells
Oxide tip
Figure 5. Cross-section TEM micrograph of device subjected to 500V
RB HBM ESD event.
Figure 3. Electroluminescence image from a device subjected to a
RB HBM event of 500V.
The power dissipation for a reverse bias event should occur in
the plane of the junction as is demonstrated below by the
failure analysis of a device subjected to an event slightly above
the threshold (500V in this case) which causes immediate
output degradation.
Electrical characterization (Figure 2) shows excessive reverse
bias leakage current and sub-threshold forward bias
electroluminescence, or emission, imaging (Figure 3) shows
dark areas in the emission patterns. Both results demonstrate
a degradation of the diode properties of the device. Planview TEM analysis shows that the dark areas observed in the
emission image correspond to large defects (i.e. dislocation
tangles) within the active area of the device (Figure 4). Crosssection analysis of this type of defect (Figure 5) shows that
the quantum well layers have fused in, and adjacent to, the
damage center and that a dense dislocation tangle exists
there. Dislocation tangles and loss of architecture also occur in
other nearby high gallium-containing layers presumably due
in part to the lower melting temperature and greater optical
energy absorption in those lower bandgap layers.
Electrical characterization (Figure 6) of a device subject to a
forward bias HBM ESD event (1800V; just above the threshold
for output degradation) reveals no significant change in the
diode properties of the device. Furthermore, there are no
1.00E-05
Reverse Current (-A)
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
0
5
10
15
Reverse Bias (-V)
Figure 4. Plan-view TEM micrograph showing the oxide and
quantum well active layers from a reverse bias HBM degraded VCSEL.
Figure 6. Reverse bias IV trace from device subjected to a FB HBM
event of 1800V (red) and a known good device.
Oxide tip
Figure 9. Cross-section TEM micrograph of device subjected to FB
HBM event.
Figure 7. Sub-threshold forward-bias electroluminescence image of
device subjected to a FB HBM event of 1800V.
easily recognizable dark area defects in the electroluminescence image (Figure 7). Plan-view TEM analysis (Figure 8)
shows that the damage areas are located close to the oxide
aperture where current densities are expected to be greatest.
The damaged area is smaller relative to the reverse bias case,
presumably due to the lower power dissipation under forward
bias. Cross-section TEM analysis (Figure 9) of a similar defect
shows relatively high mechanical stress (dark contrast) at the
oxide tip and a single dislocation arching through the otherwise preserved active layers. Thus, the forward bias HBM
event may not cause sufficient damage to the active layers
to be reflected in immediate degradation of the electrical
properties, though subsequent operation can extend the
dislocations (i.e. by the growth of an array) in the active
layers and lead to early failure.
Reverse Current (-A)
1.00E-05
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
0
5
10
Reverse Bias (-V)
Figure 8. Plan-view TEM micrograph showing the oxide and
quantum well active layers from a forward bias HBM degraded
VCSEL. The arrow indicates a dislocation tangle.
Figure 10. Reverse bias IV trace from a device subjected to a 100V
MM ESD event (red) and a known good device.
15
DAMAGE CAUSED BY THE VCSEL ITSELF –
THE CDM EVENT
Figure 11. Electroluminescence image from a device subjected to a
100V MM ESD event.
Mishandling of a packaged VCSEL may lead to the triboelectric
buildup of a charge on the device. A CDM event may result
upon subsequent contact with another body at a different
potential. Among ESD events, CDM pulses are of the highest
magnitude and shortest duration. Thus, the power dissipation
is greater than for other ESD models and the damage threshold
for VCSELs is expected to be low. For the high speed of the
pulse, normally insulating elements of the VCSEL (e.g. the
oxide layer) will become more conductive. Furthermore,
SPICE modeling of ESD events in oxide VCSELs has shown
that for a CDM event, the voltage expressed across the oxide
layer is easily sufficient to cause dielectric breakdown9.
To intentionally induce a CDM event for this work, a VCSEL
was charged with an ion gun and subsequently discharged
to a metal block. Electrical characterization (Figure 14)
shows degradation of the diode properties of the device
(e.g. increased reverse bias leakage and a soft-knee) while
the electroluminescence image (Figure 15) shows no significant dark area defects. This data suggests that there is some
degradation of the active layers of the device but does not
indicate the location. However, plan-view TEM analysis (Figure
16) shows numerous damage sites in the oxide. The damage
occurs in circles of two different radii which may reflect an
initial discharge pulse (larger circle) and a subsequent pulse
from the metal block back to the chip (smaller circle). The
damage-type observed in the circle of greater radius has
never been observed in devices that were subjected to HBM
1.00E-05
Figure 12. Plan-view TEM micrograph of device subjected to
MM ESD event.
Reverse Current (-A)
oxide tip
1.00E-06
1.00E-07
1.00E-08
1.00E-09
After zap
1.00E-10
Before zap
1.00E-11
1.00E-12
0
5
10
15
Reverse Bias (-V)
Figure 13. Cross-section TEM image of a section lifted from the planview membrane shown in Figure 12 (dotted line box).
Figure 14. Reverse bias IV trace from a device subjected to a
relatively strong CDM ESD event (red) and a known good device.
Figure 15. Electroluminescence image from a device subjected to a
relatively strong CDM ESD event.
Figure 17. Cross-section TEM micrograph through a defect caused by
a CDM event.
or MM events. Cross-section TEM analysis of one of these
damage sites in the oxide (Figure 17) shows dielectric
breakdown for which the crystallinity of the site is disrupted
(likely due to local melting and freezing).
The damage extends vertically through the oxide layer even
physically moving a section of the oxide in the image shown.
Other cross-section analyses have shown damage sites that
extend vertically to the active layers of the device which is
consistent with the increased leakage current. In contrast,
cross-section analysis (not shown) of the damage near the
oxide aperture edge shows junction damage similar to, and
in roughly the same location as, damage caused by MM
ESD events.
DAMAGE FROM LONGER DURATION
ELECTRICAL PULSES
Within the broader class of electrical overstress occurrences
(of which the relatively short ESD events comprise a subset)
the more severe cases of abuse are often detected with an
optical microscope (e.g. by the presence of cavities where
the active area should be). However, weaker EOS events
may generate outward characteristics that are similar to
those observed in ESD-degraded devices.
Figure 16. Plan-view TEM micrograph showing the oxide and
quantum well active layers from a CDM degraded VCSEL. The oxide
layer is populated by two circular distributions of damage sites.
Reverse Current (-A)
1.00E-05
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
0
5
10
15
Reverse Bias (-V)
Figure 18. Reverse bias IV trace from a device subjected to a short
pulse EOS event (red) and a known good device.
Electrical characterization (Figure 18) of a device subjected
to 5 minutes of 1% duty cycle 100ns 300mA pulses shows
increased leakage current and a lower breakdown voltage.
Electroluminescence imaging (Figure 19) shows a nonuniform emission pattern with a “dim” area defect. Plan-view
TEM imaging (Figure 20) reveals punched-out dislocations
Figure 20. Plan-view TEM micrograph showing the oxide and
quantum well active layers from a forward bias EOS pulse degraded
VCSEL. Several punched-out dislocations have moved through the
active area, segments of which have experienced recombination
enhanced dislocation growth.
which have undergone some recombination enhanced
dislocation growth. Thus, whereas the ESD causes localized
damage sites, the short pulse EOS event appears to create
a broader thermal stress, that acting on the active area
generates dislocations at the oxide terminus.
ESD IN CUSTOMER-RETURNED DEVICES
Thus far, we have shown how the location and characteristics
of ESD damage in VCSELs depends on the electrical properties
of the ESD source. The data shown (with the exception of the
CDM example) was generated using standardized test circuits.
In the field, VCSELs will be subjected to ESD sources that may
closely resemble these circuit models but there will likely be
some variation in the real-world circuit values from those
specified in the models.
To conclude, we show evidence that the intentionally generated ESD damage mechanisms explored here are found in
field returns and that these ESD damage sites can act as the
nucleation centers for dislocation arrays.
Figure 19. Electroluminescence image from a device subjected to a
short pulse EOS event.
Similarly, the plan-view TEM data shown in Figure 22
demonstrates that a dislocation array can nucleate on
damage created by a what appears to be a CDM ESD event.
SUMMARY
Figure 21. Plan-view TEM micrograph showing the oxide and
quantum well active layers from a field-failed VCSEL that was
subjected to an HBM ESD event.
The plan-view TEM data in Figure 21 shows that the dislocation
array found in a field return device was nucleated on damage
that appears to be due to a reverse bias HBM ESD. The fact
that the centers of the damage occur at the oxide edge
suggests that the power was dissipated in a faster pulse
than the HBM example shown in Figure 4.
Figure 22. Plan-view TEM micrograph of a field-failed device
subjected to a CDM event.
In this paper we have shown how the degradation present
in an ESD damaged oxide VCSEL depends on the electrical
properties of the ESD source and subsequent pulse characteristics. The damage resulting from relatively slow ESD
models (e.g. HBM) occurs well within the oxide confinement
aperture. As the speed of the ESD pulse increases, the
damage occurs in a wider circumference as the impendence
of the oxide layer decreases and as greater bias is expressed
across the oxide layer. In general, the damage can extend
from the mirror layers above the oxide layer though the
quantum wells to the mirrors layers below. Where the damage
does intersect the quantum wells, it is possible for a dislocation
array to grow. Laterally, the dislocation arrays nucleated on
ESD damage sites generally grow towards the active area
where carrier concentrations are high. AOC has not observed
dislocation array growth from the oxide trenches due to ESD
or any other defect.
The ESD failure signatures revealed by this work have been
observed in field returned devices. An understanding of the
failure signatures has improved AOC’s ability to assign a more
precise root cause to those field returned devices. Knowing
which the type of ESD caused the failure has greatly aided in
determining the source of the event and in implementing
appropriate corrective action.
REFERENCES
1
D.T. Mathes, R. Hull, Kent Choquette, K. Geib, A. Allerman,
J. Guenter, B. Hawkins, R. Hawthorne, “Nanoscale
Materials Characterization of Degradation in VCSELs”,
Proc. of SPIE, vol. 4994, pp 67-83, (2003).
2
R. W. Herrick, Degradation in Vertical Cavity Lasers,
Dissertation, Department of Electrical and Computer
Engineering, University of California, Santa Barbara, CA
(1997).
3
R.W. Herrick, “Failure Analysis and Reliability of
Optoelectronic Devices,” published in “Microelectronics
Failure Analysis Desk Reference, 5th ed.,” by ASM
International, Materials Park Ohio, pp. 230-254 (2004).
4
Terence J. Stark, Phillip E. Russell, and Corey Nevers, “3-D
defect characterization using plan view and crosssectional TEM / STEM analysis,” to be published in the
proceedings of ISTFA 2005 (this volume).
5
F. Siegelin, C. Brillert, “Failure Analysis of Vertical Cavity
Surface Emission Laser Diodes”, Proceedings from the
29th International Symposium for Testing and failure
Analysis, p. 426, 2003.
6
J. Krueger, R. Sabharwal, S. McHugo, K. Nguyen, N.X. Tan,
N. Janda, M. Mayonte, M. Heidecker, D. Eastley, M. Keever,
and C. Kocot, "Studies of ESD-related failure patterns of
Agilent oxide VCSELs," Proc of SPIE, vol. 4994, pp. 162-172,
(2003).
7
O. Mcateer, Electrostatic Discharge Control, (Mcgraw-Hill
Publishing Company, 1990).
8
S. Voldman, ESD Physics and Devices, (John Wiley and
Sons, 2004).
9
James K. Guenter, Jim A. Tatum, Robert A. Hawthorne III,
Ralph H. Johnson, David T. Mathes, Bobby M. Hawkins, “A
plot twist: the continuing story of VCSELs at AOC, “ Proc of
the SPIE, vol 5737, pp. 20-34, (2005).
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