COSC3215
Input Capture Output Compare
Time Base
• A 16-bit free running counter is used as a
time base for the IC/OC system.
4:1 MUX
Timer Clock
PACK
PCLK
TIMCLK
PACK/65536
PACK/256
CLK0
CLK1
CLK1 CLK0
Action
0
0
PCLK
0
1
PACLK
1
0
PACLK/256
1
1
PACLK/65536
TOF bit is set when the free running counter changes from
$FFFF to $0000. Reset by writing 1 to it.
It is cleared by any access to the counter if the TFFCA is set
$0004
IC/OC
• The TIM module in HCS12 is equipped
with 8 complete and individual dual
function input capture/output compare
channels.
• Channels are connected via IOC[7:0] pins
which share port T PT[7:0]
• Configures through TIOS register where
IOCn is 1 for output compare, 0 for IC
Input Capture
• The input capture system is a 16-bit binary
stopwatch.
• It can capture the time of a specific, user-defined,
event.
• The event could be falling, rising, or any edge.
• Since the free running counter is used by all the
channels, it is a bad idea to reset it, rather elapsed
time between two events is used.
Input Capture
MCLK
C3I
prescalar
TEN
Free running
counter
TC3H
C3F
CLI
°
IOS3=0
TC3H
16-bit latch
IOC pin 3
Edge detect
EDG3A
EDG3B
Indicates an interrupt condition has occurred,
to clear it write “1” to it.
To enable (1) the corresponding flag from
issuing an interrupt
Input Capture
•
When the user defined event occurs, then
1. The current value of the free running counter
is latched in TCnH/L
2. The associated channel flag CnF is set
3. If the corresponding channel interrupt enable
CnI has been set, the channel will generate an
interrupt event.
Capturing width of a single active
high pulse
•
Assumption
1. The pulse length is less than the rollover time
of the counter.
2. The pulse width is longer than the time it
takes to do steps 4 thorough 7
3. The channel is set as input capture (TIOS)
Capturing width of a single active
high pulse
1. Set the input capture to wait for a rising
edge EDG2B:EDG2A =01
2. Monitor the associated flag C2F
3. When the flag is set, it means event
occurred, and time is latched in TC2H/L
4. Read the value in TC2H/L and store it
somewhere
5. Reset the C2F (write 1)
Capturing width of a single active
high pulse
6. Set the input capture for a falling edge
EDG2B:EDG2A=10
7. Monitor C2F
8. When set, the counter value is latched in
TC2H/L
9. Read the value in TC2H/L and store it
10. Calculate the difference between these 2 values
11. Convert it to time (you know the timer clock)
Output Compare
• It allows the user to generate an output
signal when the value of the free running
counter reaches the value stored in TCnH/L
• That signal could be 0, 1, or toggle
OMn
OLn
Configuration
0
0
Timer disconnected
0
1
Toggle OCn
1
0
OCn set to 0
1
1
Ocn set to high
Output Compare
MCLK
prescalar
TEN
Free running
counter
OMn
16-bit latch
TCnH
OLn
Edge detect
IOC pin 3
IOS3=0
TCnH
C3I
CnF
CLI
°
OC Channel 7
•
•
•
•
Channel 7 has a special control over the OC
Assume register OC7M 1 0 1 1 0 0 0 1
Assume register OC7D 0 1 0 1 0 1 0 1
When TC7 matches TCNT, the logic on the
output pins OCi changes if OC7Mi is 1 and
is changes to OC7Di
• Can be used for PWM (changes twice in a
cycle, one by 7, and one by the port i)
Pulse Accumulator
• 9S12DP256 has twp pulse accumulators,
PAA, and PAB.
• These are connected to TIM inputs 7 and 0
• In order to use the PA, you have to
disconnect channel 7(0)
– 0 in the corresponding TIOS bit
– OM7:OL7 = 00 in TCTL1
– OC7M7 set to 0 in OC7M
Pulse Accumulator
• The pulse accumulator can be configured in
two modes of operation.
– Event counter mode: This mode used to count
events on the PAI pin
– Gated time accumulator mode: In this mode,
PA count pulses from a divide/64 clock. It is
gated because counting is enable when the PAI
is high(low) only. It maintain current count
when disabled.
Interrupt Logic
PAOVI
PAOVF
PAI
PACNT3
PACNT2
PAIF
PAE
PEDGE
Edge detect
From PT7
PACLK/256
16-bit counter
PACLK/65536
PACLK
MCLK
Divide by 64
PAMOD
Pulse Accumulator
•
•
•
•
•
•
•
PAI: PA Interrupt
PAIF: PA Input edge flag
PAOVI: PA Overflow Interrupt
PAOVF: PA overflow flag
PAE: PA Enable
PEDGE: PA edge control
PAMOD: PA mode
Pulse Accumulator
• PAMOD=0
– PEDGE=1: Rising edge on PT7 increments
– PEDGE=0; Falling edge on PT7 increments
• PAMOD=1
– PEDGE=1: PT7 LOW increments(- edge) with
PMOD/64; PAIF is set with trailing rising edge
– PEDGE=0: PT7 HIGH increments (- edge)with
PMOD/64; PAIF is set on trailing falling edge
Event counter mode
Interrupt Logic
PAOVI
PAOVF
PAI
PACNT3
PACNT2
PAIF
PAE
PEDGE
Edge detect
From PT7
PACLK/256
16-bit counter
PACLK/65536
PACLK
MCLK
Divide by 64
PAMOD
Gated time accumulation mode
Interrupt Logic
PAOVI
PAOVF
PAI
PACNT3
PACNT2
PAIF
PAE
PEDGE
Edge detect
From PT7
PACLK/256
16-bit counter
PACLK/65536
PACLK
MCLK
Divide by 64
PAMOD