EDAQ for AIDA and LYCCA
Ian Lazarus
(STFC Daresbury)
Contact: [email protected]
Overview
•
•
•
•
What is AIDA
What is LYCCA
EDAQ for AIDA and LYCCA
Interconnecting with other EDAQ
AIDA: introduction
Advanced Implantation Detector Array (AIDA)
UK collaboration: University of Edinburgh, University of Liverpool,
STFC Daresbury Laboratory & STFC Rutherford Appleton Laboratory
• SuperFRS
• Exotic nuclei ~ 50 – 200MeV/u
• Implant – decay correlations
• Multi-GeV implantation events
• Subsequent low-energy decays
• Tag events for gamma and neutron detector arrays
Detector: multi-plane Si DSSD array
wafer thickness 1mm
8cm x 8cm (128x128 strips) or 24cm x 8cm (384x128 strips)
Instrumentation: ASIC
low noise (<12keV FWHM), low threshold (0.25% FSR)
20GeV FSR plus ( 20MeV FSR or 1GeV FSR)
fast overload recovery (~ s)
spectroscopy performance
time-stamping
AIDA General Arrangement
Implantation detector for RDT
Slide from Tom Davinson
2 Configurations: 8x8, 8x24cm
AIDA Mechanical
Modular.
CsI and DSSD
For E-dE
Slide from Dirk Rudolph
LYCCA
Initially Mesytec electronics
Later AIDA
AIDA test on LYCCA (64 ch only)
AIDA FEE card (NUSTAR, DeSpec)
Mezzanine:
4x 16 channel ASICs
Cu cover
EMI/RFI/light screen
cooling
FEE width: 8cm
Prototype – air cooling
Production – recirculating coolant
FEE:
4x 16-bit ADC MUX readout (not visible)
8x octal 50MSPS 14-bit ADCs
Xilinx Virtex 5 FPGA
PowerPC 40x CPU core/Linux OS – DAQ
Gbit ethernet, clock, JTAG ports
Power
Octal FADC
(serial out)
12/14bit 50MHz
(2 per ASIC)
Octal FADC
(serial out)
12/14bit 50MHz
(2 per ASIC)
Preamp + shaper
low/high gain.
(16 channels)
Pk
Det
&
Mux
Sliding Scale
Spectroscopy
ADC 14bits
1 to 5us conv.
Control Logic
FEE for AIDA (NUSTAR,
DeSpec)
Part of
FPGA
AIDA ASIC (NUSTAR)
Channel 16
Channel 3
Channel 2
Channel 1
Low & Medium Energy Channel
High-speed buffer
External
sampling ADC
x16
x16
Fast
Discriminator
x10 Slow
Amplifier
Analogue
input
Control
Logic
Slow
Discriminator
Peak
Hold
Preamp
Digital
output
Analogue
output
MUX
Shaper
CMOS
switches
reset
Fast
Discriminator
Peak
Hold
Preamp
Shaper
High Energy Channel
Braga et al. 2009 IEEE NSS conf record, VOLS 1-5 P 1924-8
Layout
7.5 mm
AIDA ASIC:
•625um pitch
•16 channels
•2 channels/strip
•Mux’ed analogue output
•Direct digital output for
external FADC
•2 ranges: 0-20MeV/1GeV
(switchable) and 0-20GeV
(fixed)
•AMS 0.35um CMOS
7.9 mm
October 2009
IEEE NSS
7/15
Connecting new TS software triggered
systems to existing systems
Legacy equipment usually needs an early
coincidence trigger. But TS software trigger has
latency. There are 2 solutions:
Shaper
TFA
System
trigger
logic
h/w
PDS
Discr
Ctrl.
A
D
C
Buffer
Sumbus or pattern out
L1 Trig
L2 Trig
10-100us time difference
Shaper
TFA
PDS
Discr
Ctrl.
TS
A
D
C
Buffer
 Run independently
with common
scalers
 Add extra
“compatibility”
output.
System
trigger
logic
s/w
How to solve the problem
• Solutions(1):
– Standardise on either hardware triggered or
free-running systems?
• Many reasons why we can’t do this:
– Even NUSTAR isn’t all new build- legacy equipment
– Needs investment of effort and money
– Why change what works? (People like what they have;
need a good reason to change, not just “progress”.)
– Free running users like running with no dead time and
don’t want to go back to hardware triggered systems
How to solve the problem
• Solutions(2):
– Modify free-running DAQ systems to
generate early information
•
•
•
•
More connections (1 per channel/ASIC/Si ladder)
More cost
More complexity
Grounding needs care or isolation
How to solve the problem
• Solutions(3):
– Modify hardware triggered systems to share
common scaler/clock with free running DAQ
•
•
•
•
•
•
•
Extra connection (but only 1 set per system)
Small cost
Small change to GUI and slow control
Grounding needs care or isolation
Few extra parameters in each event
Software trigger needs merge + common readout
No data reduction in triggered systems
BUTIS
White Rabbit
VME/PCIe card
Accepted Trig/ Or trig
Clock
FMC
SCALER
Fast NIM trigger/scaler signals
MACB
MBS
MACB
MACB
MACB
AIDA
FEE
AIDA
FEE
MACB
MACB
AIDA
FEE
AIDA
FEE
MACB
AIDA
FEE
AIDA
FEE
MACB
AIDA
FEE
AIDA
FEE
Connecting AIDA/LYCCA to MBS- Option 2 (0nline Merge)
Draft 3 updated 1-3-2011
Conceptual design follows discussion between Ian ,Nik and Stephane at GSI and discussion at DL between Vic, Patrick, Simon and Ian
MBS DAQ
MBS+
AIDA
data
Storage
Merge
(Time
Sort)
Event
builder
Data
Buffer
AIDA DAQ
New connections and blocks shown in red
AIDA
Receiver
PC
100% AIDA
data
Disk
PC
100% data from AIDA (later will use
time windows; initially delay trigger to
wait for AIDA and then send to merge)
Ethernet
PPC
Flip
flop
Buffers
Merge AIDA and
MBS using scaler
Flip
flop
Buffers
Buffer
control
MBS Accepted Trig
MBS control
Disk
FPGA with PPC
Scaler rst_req
Time Stamp
VME scaler
Scaler rst
Clock from FPGA
(10-50MHz)
ADCs
Distance up to 50M
Fast NIM signals
Linked scalers to
correlate 2 systems
Adapter
box
NIM/3.3v
New scaler
dcm
Discrim
pattern
Energy
ADCs
ASICs
AIDA Status
• FEE cards built and tested (for AIDA
and LYCCA)
• FEE including ASICs tested in beam
• Waiting for more beam
• DAQ working (tested in beam)
• VHDL improvements (using PSA option)
• MACB cards 1st batch built and tested