UV-Initiated Surface Preparation and Reaction on Semiconductor Wafer Surfaces
Casey Finstad, Gerardo Montaño, and Anthony Muscat
Department of Chemical and Environmental Engineering
University of Arizona, P.O. Box 210011, Tucson, AZ 85721
Background
As microelectronic devices continue to shrink, the harmful effects of contamination become more pronounced.
With smaller geometries, a contamination-induced defect becomes relatively larger and more significant. With
decreasing gate oxide thickness, metallic contamination is more likely to result in dielectric breakdown. The
candidate high-k gate dielectric materials proposed for the replacement of SiO2 are oxides and alloys (silicates)
containing early transition metal cations from groups IIIA (Y, La), IVA (Ti, Zr, Hf), and VA (Ta) in the periodic
table. These metal oxides and alloys are deposited on Si using physical or chemical processes rather than grown
thermally by consuming part of the surface as is done for a SiO2 gate. Growing the SiO2 gate dielectric from the
substrate ensures a good substrate-to-dielectric interface, and the high temperature oxidizing conditions remove
adventitious carbon. High quality interfaces between silicon and new dielectric materials will likely require more
stringent surface preparation requirements. Additionally, the interface should be smooth and free of metal
contamination. While cleaning steps are becoming more important the ITRS roadmap has called for reduced
consumption of water and energy. The traditional aqueous acid baths currently used by industry are water and
chemical intensive. Wet cleans account for 1/3 of total processing steps, and consume ~60% of all ultrapure water
(UPW).1 At 50 kWh/1000 gallons1 of UPW, this results in significant energy usage as well. Gas phase cleans can
reduce chemical and ultra-pure water consumption by at least 100-1000 times,2,3 and would generate a similarly
reduced volume of waste. Because gas phase cleans are done within vacuum chambers, cleanroom workers would
no longer be exposed to the hazardous vapors emanating from the traditional, open-air acid baths. Gaseous cleans
are also less likely than a liquid bath to add new contamination to a wafer surface.
Replacing liquid cleans with gas phase cleans will make the whole process compatible with vacuum cluster
tools where Reactive Ion Etching (RIE), cleaning, and deposition of high-K material can take place within one
cluster tool, eliminating atmospheric exposure of wafers between steps and reducing the likelihood of
recontamination or oxide growth before deposition. By clustering etching, cleaning, and deposition tools together,
throughput benefits from reduced pump-down cycles. Gas phase processes are also more compatible with single
wafer processing than batch processes, and single wafer processes offer more efficient utilization of reagents and
better integration of many diverse process steps. The disadvantage of single wafer processing has traditionally been
limited throughput, but the move towards 12” wafers is making single wafer processing more competitive due to the
larger wafer area and the dramatic increase in cost of batch tools for 12” wafers.
Proper surface preparation removes contamination and primes the surface for deposition, improving adhesion
between the substrate and the deposited dielectric material. High-k dielectric materials, as well as barrier layers and
electrode materials, are ideal candidates for atomic layer deposition (ALD), which has advantages over chemical
vapor deposition (CVD), plasma enhanced CVD (PECVD), or sputtering, because it forms smooth, conformal layers
independent of surface geometry. Conformality and thickness control are achieved by dividing the deposition
reaction into two or more self-limiting half reactions between gas-phase precursors and the substrate surface. Each
half reaction proceeds, in principle, until the surface is saturated,4,5 so growth is limited by surface adsorption and
reaction, rather than reactant fluxes. This preserves conformality, even within high aspect ratio features. For
example, conformal layers of HfO2 are grown by first reacting a hydroxyl-terminated HfO2 surface with HfCl4,
OH
OH
OH
OH
Cl
Hf
O
O
Cl
Cl
Hf
O
Cl
HfCl4
Cl
Cl
Hf
O
O
Hf
O
O
O
HCl
Hf
O
OH
Cl
OH
HCl
HCl
OH
HfCl4
OH
H2O
O
Hf
O
O
HfO2
Si Substrate
Figure 1: Deposition of HfO2 by ALD using HfCl4 and H2O as precursors. Conformal deposition is
ensured by dividing the reaction into two self-limiting half reactions. Each half reaction activates the
surface for the subsequent half reaction.
adding Hf and resulting in a Cl-terminated surface (Fig. 1). This is followed by water to displace the chlorine atoms,
add oxygen to the film, and regenerate a hydroxylated surface. ALD also presents the possibility for easy recycling
of precursor material to minimize waste.
To initiate an ALD sequence, the substrate must be reactive with the precursor (HfCl4, ZrCl4, TiCl4), for which
hydroxyl terminated silicon is ideal. The metal chloride displaces the hydrogen, resulting in silicon-oxygen-metal
bonds which become the interface between the substrate and dielectric. One approach to generate hydroxyl
termination on bare silicon is to terminate the surface with a leaving group that is easily displaced by water.
Chlorine has been used, but bromine or iodine are potentially more efficient leaving groups because of their larger
size. Fluorine forms very strong bonds and is a poor leaving group.
Surface Preparation
A potential cleaning sequence combines a hydrofluoric acid/water vapor (HF/H2O) step for oxide removal with
an ultraviolet/chlorine (UV/Cl2) step for metal and organic removal. Gas phase UV/halogen processes can also be
used to manipulate the surface termination of the Si substrate, which can promote the deposition of high-k films. A
model gas phase pre-gate deposition cleaning sequence was studied in a research cluster apparatus using integrated
gas phase UV/Cl2 and HF/H2O process steps. An unpatterned wafer was coated with photoresist, developed, reactive
ion etched in a fluorocarbon plasma for 1 min, and oxygen ashed for 24 min. to mimic the gate are definition
process. The wafer was then diced into 1 x 1 cm samples and loaded for cleaning. An initial gas phase HF/H2O
exposure (100 Torr, 27°C, 80 sccm HF, 35 sccm H2O for 200 s) was necessary to remove oxide and expose the
organic contamination. UV/Cl2 exposures (100 Torr, 10 sccm Cl2, 90 sccm N2, illuminated by 200 W Hg-Xe lamp)
at 90°C for 15 min were then effective in removing nearly all of the organic contamination, as indicated by the loss
of the carbon XPS peak at 284.8 eV in Fig. 2. Chlorine (270.0 eV) displaced fluorine, which was left by the HF/H2O
step. For comparison, a sample cleaned by standard liquid processing (dilute HF: 0.5% HF for 1 min, Piranha: 4:1
H2SO4:H2O2 at 110°C, for 10 min) is shown. The results indicate that gas phase processing may be viable for cleans
immediately prior to the deposition of gate dielectric films and may enable new surface termination strategies by
replacing fluorine termination with a chlorine surface.
A combination of ultraviolet light and chlorine gas (UV/Cl2) has been shown to be an effective clean for
metals removal, however, the process generally requires elevated temperatures that also promote unacceptable
roughening of the surface by etching silicon. Chlorine does not spontaneously etch silicon below 300°C, but under
UV illumination, silicon etches at temperatures as low as 80°C.6 The removal of metal from silicon has been studied
by artificially dosing silicon samples with copper and observing removal by XPS. By studying the fundamentals of
Gas Phase
F 1s
O 1s
Liquid Phase
C 1s
Cl 2s
F 1s
O 1s
x 0.1
x 0.1
Arbitrary Counts
Initial
1st HF/H2O
C 1s Cl 2s
Initial
1st Dilute HF
1st UV/Cl2
Piranha
2nd HF/H2O
2nd Dilute HF
x 0.1
2nd UV/Cl2
690 680
540 530
290 280 270 260
Binding Energy, eV
690 680
540 530
290 280 270 260
Binding Energy, eV
Figure 2: XPS spectra comparing model gas phase cleaning sequence to traditional liquid cleaning process. The decreasing
carbon 1s peak indicates the removal of organic contamination, while the decreasing oxygen 1s indicates oxide removal (note
scale factors). UV/Cl2 processes displaced fluorine surface termination with chlorine. Liquid processing left surface with slight
fluorine coverage.
F F F
-OH
SiO2
-OH
-OH
IR
Silicon
l=330nm
b.
Cl •
F F F
SiO2
Cl
-C
l
Cl •
•
Cl
Silicon
c.
Cl Cl Cl
SiO2
Silicon
-OH
-OH
-OH
d.
SiO2
e.
SiO2
-OH
Silicon
-OH
-OH
Resistless deposition of high-k dielectrics
To initiate ALD, the surface termination of the silicon is an
important consideration. This study will also examine
UV/halogen chemistries for their ability to manipulate the
surface termination of silicon wafers, better preparing the wafer
surface for subsequent deposition of high-K gate dielectrics. Gas
phase cleans that simultaneously remove contaminants and
activate the surface for subsequent high-k deposition will have a
further advantage over aqueous acid liquid cleans. Key to the
first step of deposition is preparing the surface with a suitable
leaving group that will react with the first exposure of ALD
precursor. The leaving group serves to satisfy the surface
silicon’s bonding requirements and also participates in the
double displacement reactions typically used in ALD techniques.
In Fig. 1, chlorine and hydrogen are leaving groups, forming
HCl.
Gate oxide is currently grown using the bare Si at the
bottom of vias created by reactive ion etching of field oxide. The
switch in processing to a deposited high-k dielectric, however,
requires an additional patterning step to define the gate region.
An alternative approach to the conventional subtractive
processing sequence is to prime the silicon surface in order to
deposit high-k dielectric material only on the silicon, leaving the
exposed field oxide surfaces free of the high-k material (Fig. 3).
This eliminates the need for subsequent photoresist masking,
plasma etching, and cleaning steps in the subtractive process
flow, reducing resource consumption and cost. The biggest
drawback of ALD has been its slow deposition rate compared to
CVD, PECVD, and sputtering. By eliminating the need for
subsequent processing steps to subtractively pattern the
dielectric, however, selective ALD compensates for its slower
deposition rate. Selective ALD also overcomes the technical
problems associated with etching novel high-k materials.
We are currently investigating halogen chemistry as a route
to silicon surface priming based on two experimental results: (1)
halogens react with silicon exposed to UV light; (2) iodine and
chlorine do not react with thermal oxide (Fig. 4). Because
chlorine radicals are capable of etching silicon, the effect of
UV/Cl2 surface treatments on the roughness of the silicon should
be quantified. If UV/Cl2 results in unacceptable roughening, then
alternatives such as the less aggressive UV/Br2 and UV/I2
processes will be examined.
a.
-OH
the reaction mechanism, the goal is to promote the cleaning
reaction while suppressing the etching reactions. In the specific
case of copper, the reaction with chlorine is spontaneous,
forming CuCl2, the most thermodynamically stable, but least
volatile form of copper chloride. At elevated temperatures
(greater than ~150°C), the CuCl2 decomposes to CuCl, which
desorbs from the wafer surface.7 UV light at 254 nm2,7,8 and
electron beams have been used to reduce CuCl2 to CuCl, the
limiting step preventing low temperature (less than 80°C) copper
removal.
HfO2
Silicon
Figure 3: Process sequence illustrating possible
route to resistless deposition. (a.) Wafer is
annealed to drive off hydroxyl groups initially
present in the oxide to prevent their reactions
with precursor in step d. (b.) UV/Cl2 removes
organics and metals and displaces fluorine
from the silicon surface. (c.) Chlorine leaving
group terminates the bare silicon before H2O
exposure. (d.) Hydroxyl groups react with
HfCl4 as in Fig 1. (e.) Selective Atomic Layer
Deposition (ALD) proceeds, building up high-k
material over bare silicon regions and not on
oxide regions.
1
2
3
4
5
6
7
8
Si 2s
Si 2s
Cl 2p
F 1s
Arbitrary Counts
Summary
By understanding the UV-assisted mechanisms
Bare Silicon
for contaminant removal from wafer surfaces, the
Initial
UV/halogen chemistries can be used to replace the
aqueous SC1 (HCl/H2O2) and piranha (H2SO4/H2O2)
Final
chemistries currently used by industry to remove
1400Å
metallic and organic contaminants. A ready niche
Silicon
Dioxide
Initial
application would be a cleaning sequence prior to the
deposition of novel high-K gate dielectrics, taking
Final
advantage of the vacuum compatible nature of gas
phase cleans allowing surface preparation and gate
690
675
195
180
165
150
deposition to be performed within the same
Binding Energy, eV
processing
tool. Eliminating aqueous cleaning
Figure 4: On bare silicon, UV/Cl2 displaces the partial fluorine
chemistries can significantly reduce water, energy,
surface termination with a saturated chlorine termination. On
thermal oxide, there is no effect.
and chemical consumption, resulting in a significant
cost savings. Most significantly, the UV/halogen
chemistries can prime silicon surfaces for selective deposition of high-k dielectrics by ALD, replacing the resource
intensive subtractive processes otherwise necessary for deposition and patterning of these new materials.
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