A 10Gb/s Eye-Opening Monitor
in 0.13µm CMOS
B. Analui1, A. Rylyakov2, S. Rylov2,
M. Meghelli2, and A. Hajimiri1
1.
2.
California Institute of Technology, Pasadena, CA
IBM T. J. Watson Research Center, Yorktown Heights, NY
Outline
Adaptive Equalization
• Motivation
• Eye-Opening Monitor
– Concept
– Architecture
• Prototype Measurement
• Conclusion
Modal Dispersion
Multi-mode Fiber (MMF)
BER > 10-5
Output of over 800m MMF @ 10Gb/s
Modal Dispersion is the dominant source of ISI in MMF
Equalization
MMF
coefficients
in
BER ≈ 10-5
out
3-tap Transversal (FIR) Filter
BER < 10-12
*H.
Wu, et al. [ISSCC’03]
*S.
Reynolds, et al. [ISSCC’05]
Adaptive Equalization
Advantages of Adaptability
• Equalization of unknown channel response
in
error
– MMF: fiber length or launch condition
•
Adjustments to channel response variations
out
Why is LMS Undesirable?
Cki = Cki −1 + δ ⋅ error i −1 ⋅ xki −1
LMS Adaptation
•
error is a function of decision Æ Convergence issues in high BER
•
Internal loading of the FIR filter
Eye-Opening Monitor (EOM)
Data
Objective:
An architecture that evaluates
the received signal quality
New
coefficients
Clock
Adaptive Equalizer Architecture
EOM Advantages
in
• Not loading filter internal nodes
• Actual signal quality evaluation
• Choice of algorithm
slow
link
fast link
out
Monitoring Technique
EOM is designed such that it can provide:
• Horizontal Eye Diagram Opening
• Vertical Eye Diagram Opening
• Two-Dimensional Map of the Eye Diagram
Any data transition inside a
rectangular mask is counted as error
Mask Error Rate (MER)
MER ≡
Eye monitoring algorithm (I) :
Adjust mask size
Count & Record
errors
error count
total transitions
Eye Opening is
the mask size
for a given MER
2D Eye Diagram Error Map
Effective Eye Opening:
Combination of the masks
with the same MER
10-3
Effective Eye Opening
for various MERs
10-4
10-5
10-6
10-7
MER
MER
Effective Eye Opening
2D Map of the Eye
The algorithm can judge signal quality based on the 2D error map.
Mask Error Detection
Variable comparator
references
VH
Mask
VL
error = SH ⊕ SL
φearly
XOR
m: Mask
0
1
0
0
1
m
m
m
m
m
0
φlate
Variable sampling phases
1
m
m
SH,early
SL,early
SH,late
SL,late
right and left sides of the
mask move independently
Asymmetric eye diagrams
are captured
te
φ la
rly
φ ea
Mask Shape Sweep
VH
VL
Sampling Clocks
• 1 control signal steps reference voltages (vertical opening)
• 2 control signals independently step sampling phases (horizontal opening)
Total number of masks that can be measured:
e.g. 600 with off-chip references
7 x ( 15 + 15 ) = 210
7-level
differential
DAC
15-level
Phase rotator
100ps
30
= 3.4ps phase resolution @ 10Gb/s
Vertical Opening-Comparator
data
VH
VL
data
VH
VB
CML
Buffer
VL
data
VB
VB
Comparator
DAC
Swapping references
Vcontrol
next_ref
vertical
opening
control
+VH
VH
VL
s6
s0
s0
-VH
x7
VB
s6
VB
DAC
(shift registers not shown)
-VL
+VL
Horizontal Opening- Rotator
φearly
φlate
φ
I
full-rate
clock
φ
Q
I
Q
15
15
full-rate clock
/2
I
φout
φout
φ1
φ1 φ2
Q
φ2
φearly
φlate
I
s0
s0
s14
x15
VB
VB
Phase Interpolator-core
s14
Each of the φearly and φlate
cover half of the eye
Complete Architecture
MS-DFF1
D1
Q1
DFF
D
data
Q
DFF
D
VH
VL
Q
φlate
φearly
DFF
D
Q
DFF
Q
D
φearly
φ
clock
/2
Q
I
sel0
sel1
error_out
Combine
/M
M=1, 4, 16, 64
clock_out
phase set
registers
Vcontrol
I
late
MS-DFF2
D2
Q2
/512
DAC
next_ref
logic
retime
/16
logic
retime
/16
φlate
φ
early
D
Q
next_φearly next_φlate
horizontal opening
controls
Chip Layout
VL
VH
660µm
next_φlate
Slicer
DFFs
400µm
/2 &
rotators
Data
CMOS
next_φearly
error_out
clock_out
Data
Clock
Outline
Adaptive Equalization
• Motivation
• Eye-Opening Monitor
– Concept
– Architecture
• Prototype Measurement
• Conclusion
Phase Rotator Measurement
clock
delay
Add
Jitter
PRBS Source
Trigger
Spectrum
Analyzer
10.0GHz
Oscilloscope
clock
next_φlate next_φearly
∆t
data
∆t
data
delay line
Oscilloscope
clock_out
EOM chip
VH
VL error_out
Power Supply
clock
10GHz
next_φlate 3MHz
Accumulated clock_out
~50ps
40ps
φlate covers half of the eye
80mV
Qualitative Eye Opening
4
,1
te
φ la
,0
te
φ
φ
φ la
• error_out frequency (MER)
increases as mask gets wider
,0
120mV
ea
rly
VH - VL
,1
10GHz
ea
rly
clock
4
10Gb/s 231-1 with 40ps peak-to-peak jitter
20ps
no-error zone
error_out (zoomed)
500mv
500mv
error_out
next_φearly 0
next_φlate
Error frequency increases
10µs
50µs
15
150mv
next_φearly
next_φlate
Measured Eye Opening
Measured eye opening for different input jitter
MER =
freq(error _ out ) × div _ ratio
0.5 × Bit Rate
Measured Eye Opening [ps]
Limited by delay resolution
70
60
50
40
30
20
10
0
MER
1%
0.50%
0.1%
Desired monotonic response
0
10
20
30
40
Peak to Peak Jitter [ps]
50
60
Measured 2D Error Map
PRBS Source
10Gb/s 231-1 with 40ps Jitter
Pulse Generator
GPIB BUS
12.5GHz
maximum mask
size
Controller
Jitter
clock
next_φearly
next_φlate
dataB
data
20ps
150mv
5’ SMA
Cable
Error diagram
25
25
-3
-3
-4
-4
00
-5
-5
-25
-25
-6
-6
VH
000,000,000 Hz
VL error_out
Power Supply
-2
-2
Log(MER) [10-x]
vertical mask size [mV]
50
50
EOM chip
Frequency Counter
φearly and φlate are stepped separately
to capture asymmetrical eye shape
horizontal mask size [UI]
-50
-50
00
0.5
0.5
11
~70dB MER dynamic range
MER vs. BER
vd
VH
VL
0
0
log10MER
-2
-4
-6
-8
-10
vd=0.8
 1 
BER = Q

 2σ 
vd=0.6
MER = Q(
vd=0.4
≅ Q(
vd=0.2
-10
1
1+ vd
1− vd
)
) − Q(
2σ
2σ
1− vd
)
2σ
prob{(0 + noise ) ≤ VH }
prob{(0 + noise ) ≥ VL }
-5
log10BER
0
Comparators’ Impact
The expected MER when input BER is 10-12
with comparator noise and gainxbandwidth limitation
A(t)
0.6
G=2.5 f-3dB=8GHz
0.5
VH
-2
Input BER=10-12
-4
vd
0.3
-6
0.2
-8
0.1
20
40
t [ps]
60
Log(MER) [10-x]
0.4
VL
t
MER = prob{SH ≠ SL }
 A(t ) + v d
 A(t ) − v d  
 ⋅ 1 − Q
≅ Q
 2σ L
 2σ H  



80
VH comparator
VL comparator
15
12.5Gb/s 231-1 w/ 57ps SJ & 5ft SMA cable
Sampling threshold [mV]
-0.5
10
-0.6
5
-0.7
0
-0.8
-5
-0.9
-1
-10
-15
0
before 10% digital error
-0.4
horizontal mask size [UI]
0.5
after 10% digital error
Sampling point [UI]
Sampling point [UI]
Measured by commercial BERT
Unlike in a BERT, digital errors do not affect the EOM operation
-1.1
1
Log(MER) [10-x]
40mv 20ps
vertical mask size [mV]
input eye
Measured by the EOM
Performance Summary
1-12.5Gb/s
MER
Dynamic Range
68dB
Input
Dynamic Range
50mV-500mV
Supply
1-1.5V
Total Current
275mA
Process
0.13µm CMOS
1.7mm
Data Rate
1.7mm
The EOM die photograph
Conclusion
• Eye-Opening Monitor:
–
–
–
–
2-dimensional map correlated to signal quality
Various optimization algorithms
Evaluates actual signal quality
Special sequences are NOT necessary
• CMOS implementation of the architecture
achieves 70dB error dynamic range and
operates to 12.5Gb/s
Acknowledgements
• Jose Tierno, Thomas Zwick, Mike Beakes,
Beakes IBM T J Watson Research Lab.
• John Ewen, JDSU
• Jeremy Schaub, Petar Pepeljugoski, Dan Friedman, Sudhir Gowda, Jeff
Kash, Mehmet Soyuer, Modest Oprysko, IBM T J Watson Research Lab.
• IBM Microelectronics
• Lee Center for Advanced Networking, Caltech