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Optimization of nanoscale silicon waveguide fabrication
Yao Chen1,2, Junbo Feng1, Zhiping Zhou1,3,4, Jun Yu2, Christopher J. Summers5, David S. Citrin4,6
1
Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, Hubei 430074, China
2
Department of Electronic Science & Technology, Huazhong University of Science and Technology, Wuhan, Hubei 430074, China
3
State Key Laboratory on Advanced Optical Communication Systems and Networks, Peking University, Beijing, 100871, China
4
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta Georgia 30332-0250, USA
5
6
School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta Georgia 30332-0245, USA
Unité Mixte Internationale 2958 Georgia Tech-CNRS, Georgia Tech Lorraine, 2, rue Marconi, 57070 Metz, France
Corresponding email: [email protected]
Abstract: A simple and effective technique was developed to improve the nanoscale silicon
waveguide fabrication. 40 nanometer features with smooth and vertical sidewall are demonstrated.
With this technique, nanoscale silicon grating coupler was obtained.
©2008 Optical Society of America
OCIS codes: (220.4241) Nanostructure fabrication; (230.7370) Waveguides; (240.5770) Roughness
1. Introduction
Nanoscale silicon waveguide has attracted considerable interests because it is compatible with the mature CMOS
technology and it has potential applications in nanophotonic and nano-optoelectronic devices, such as grating
couplers, modulators, solar cells, optical biosensors and so on.
Fabrication of nanoscale silicon waveguide requires smooth sidewall, vertical profile, and minimum line-width
fluctuation in nanometer dimensions. The methods vary [1-3], but, recently the process of e-beam lithography
followed by wet or dry silicon etching has stimulated a significant amount of research [4-6].
In the present work, a new technique comprising e-beam lithography and optimized chlorine based inductively
coupled plasma (ICP) etch process was developed which meets the requirement of nanoscale silicon waveguide
with anisotropic profile and smooth sidewall morphology without any post etch process. The etch mechanism for
silicon under chlorine plasma, which aims at high speed etch with vertical profile and smooth sidewall, was
discussed in detail. Subsequently the newly developed technique was applied to fabricate a nanoscale silicon grating
coupler with fine features of 40nm.
2. Experiment
Bare silicon and SOI wafers which consist of a 320 nm-thick silicon top layer and a 1 um-thick buffer oxide
insulator layer were used as substrates. Firstly, negative tone e-beam resist HSQ was spin-coated on the substrates
and baked under 100, 200 and 350oC, one minute each on hot plate. Exposure was done by JEOL JBX-9300FS EBL
System with 100KV accelerating voltage. The exposure beam current was 2nA and doses were varied according to
different pattern sizes and densities. The etch process for patterning silicon with nanometer dimensions was
developed using a Plasma-Therm ICP tool. Both ICP coil power and bias power, which separately control
generation and direction of reactive ions, operate at radio frequency. Chlorine was the only gas used in the process
and back side helium maintained the sample temperature at 25oC. All results of e-beam lithography and etch profile
were inspected by Zeiss Ultra60 SEM with resolution down to 1nm.
In e-beam lithography process, exposure doses were optimized for patterning dense grating structures and a
high concentration developer of TMAH (25%) was applied to define steep resist profile of lines and spacings down
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to 40nm in width. Fig. 1 shows a cross section view of HSQ grating patterns after development, in which the
charge effect caused by the non-conductive e-beam resist is also displayed in the background.
Fig.1. Cross section view of HSQ grating
Fig. 2. Striation roughness on silicon
Fig. 3. Grass shape roughness on silicon
sidewall induced by ion bombardment
caused by an insufficient bias power
The etching is based on a mechanism including chemical absorption reaction and ion-assisted reaction [7].
Normally chemical absorption etching is slow in undoped silicon using chlorine. The etch rate is mainly controlled
by the bias power which induces ion bombardment to the etch surface and enhances the ion-assisted reaction. Under
conditions of sufficient radicals and active ions provided by ICP coil power, a high bias power results in higher etch
rate and steeper sidewall profile by increasing the energy of reactive ions hitting the substrate. However, ion
bombardment also induces striation type roughness on silicon sidewall as shown in Fig. 2, which may cause severe
scattering loss of silicon waveguide. This sidewall roughness was 20-30nm by standard process.
To reduce the striation roughness and maintain a high etch rate and steep sidewall profile, we increase the
chlorine flow rate and the ICP coil power to induce more fresh radicals and active ions in the chamber while
decrease the bias power. This helps to enhance the chemical absorption etching while weaken the ion-assisted
reaction. Further decreasing the bias power will cause problem of directing reactants to the etch surface and leave
grass shape unetched silicon roughness (as shown in Fig. 3) on substrate surface with ultra slow etch rate.
3. Results and discussion
An optimized process was developed by compensating the two etch mechanisms with chlorine flow rate of 50sccm,
ICP coil power of 500W and bias power of 30W under a pressure of 5mT. The etch rate is around 160nm/min and
the resultant sidewall profile is shown in Fig. 4, in which the striation roughness was greatly reduced. The insert
picture in Fig. 4 is a top-view of the edge of silicon waveguide, indicating the less than 10nm roughness, which
demonstrates nanometer line-width fluctuation was achieved.
Fig. 4. Detail profile of etched silicon sidewall
using optimized etch process
Fig. 5. Silicon grating coupler
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Nanoscale silicon grating coupler is a fundamental device for nano-optoelectronic systems. However, few
fabrication processes were reported to realize it since it requires minimum line-width fluctuation in nanometer
dimensions in a high pattern density. A nanoscale grating coupler was designed to have ridges and spacings with
different widths in steep profile [8, 9]. The structure fabricated using the above developed technique is shown in Fig.
5, indicating the smallest ridge and spacing of 40nm in width are achieved.
It is worthy to notice that the developer for HSQ resist in e-beam lithography process is 2.5% TMAH, and the
high concentration developer, which helps to increase contrast of the resist while decreasing its sensitivity, is
necessary for patterning nanoscale patterns in a high density fashion. In ICP process, the chamber pressure was
changed to adjust the strength of ion bombardment to the substrate, because it changes the mean free path of the
radicals and reactive ions inside the chamber. In our experiment, we observed strong lag effect which caused ridges
of different heights under a higher pressure, therefore, we maintained the 5mT pressure which is the lowest pressure
the system can afford. By suitably correlating the chemical absorption reaction and ion-assisted reaction, the
process meets the requirements of nanoscale silicon waveguide fabrication.
4. Summary
A simple and effective technique comprising e-beam lithography and reactive ion etching silicon using chlorine
plasma has been investigated to fulfill the requirements of nanoscale silicon waveguide fabrication without any post
etch process. The mechanism of chlorine etching silicon in ICP has been analyzed, and a high etch rate anisotropic
process resulting in smooth sidewall has been obtained. Finally, a nanoscale silicon grating coupler has been
realized by using this technique with the finest features of 40nm. This technique is compatible with the mature
CMOS technology and owns potential applications in nanoscale silicon photonics and optoelectronics.
5. Reference
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