University of Duisburg-Essen
Faculty of Engineering
Institute of Computer Engineering
Prof. Dr. -Ing. A. Hunger
Dr.-Ing. Stefan Werner
Tutorial “Fundamentals of Computer Engineering”
WS 16/17
Boolean Algebra
Task 1
Simplify the following Boolean expressions and minimize the number of
literals:
1.1
1.2
1.3
Task 2
Convert the following expressions into sum of products and product of sums:
2.1
2.2
Task 3
Write the following function in Conjunctive Normal Form and Disjunctive
Normal Form ( Hint: Use the truth table)
University of Duisburg-Essen
Faculty of Engineering
Institute of Computer Engineering
Prof. Dr. -Ing. A. Hunger
Dr.-Ing. Stefan Werner
Tutorial “Fundamentals of Computer Engineering”
WS 16/17
Task 4
4.1
4.2
4.3
4.4
Form respective equations for output X and Y shown in the circuit below.
Construct a truth table based on the output equations.
Minimize the equations formed with the help of the KV-Map.
Draw a minimized circuit and compare it to the original circuit below.
Discuss the result.
University of Duisburg-Essen
Faculty of Engineering
Institute of Computer Engineering
Prof. Dr. -Ing. A. Hunger
Dr.-Ing. Stefan Werner
Tutorial “Fundamentals of Computer Engineering”
WS 16/17
Task 5
The figure below shows a multilevel structure of a full adder constructed with two half adder.
The underlying figure shows the same circuit in its logic form.
Figure a : Block diagram
Figure b : Combinatorial circuit
The propagation delay of the XOR-, AND- and OR- gate of the 74series are given by:
tPLH
tPHL
7408 AND
20ns 12ns
7432 OR
10ns 22ns
7486 XOR
25ns 15ns
University of Duisburg-Essen
Faculty of Engineering
Institute of Computer Engineering
Prof. Dr. -Ing. A. Hunger
Dr.-Ing. Stefan Werner
Tutorial “Fundamentals of Computer Engineering”
WS 16/17
Analyse the full adder in diagram b.
5.1 Complete the following truth table:
xi
yi
ci
J
K
L
si
ci+1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
5.2 Which value must x and y take to activate the path from Cin to the sum (ci Æ si ) and the
path from Cin to Cout (ci Æ ci+1 )?What are the propagation delay ( rising and falling) of
these path?
Hint:Activating a path means that the changes in input state will trigger a change in the
path as well as the level of output state.
Consider for example the first two line of the truth table. (xi , yi) = (0,0) enables the
propagation of ci (LH) Æ si (LH ) as well as ci (HL) Æ si ( HL ) through the XOR gates .
However, this value does not activate the propagation of ci Æ ci+1 (this means that
changes in ci does not trigger a change in ci+1remains the same ) .
5.3 What value must ci and y take to activate the path from x to sum (xi Æ si ) and x to Cout
(xi Æ ci+1 ).What is the propagation delay ( rising and falling) of these path?
5.4 What is the critical path ( primary input to primary output ) and what is the maximum
propagation delay ?
University of Duisburg-Essen
Faculty of Engineering
Institute of Computer Engineering
Prof. Dr. -Ing. A. Hunger
Dr.-Ing. Stefan Werner
Tutorial “Fundamentals of Computer Engineering”
WS 16/17
5.5 Construct an impulse diagram showing the propagation delay along the critical path
( with all auxiliary node). Both the output of the sum as well as the carry should be
included.
Task 6 (Finite state machine)
Develop a FSM for Traffic Light Controller that operates in two different modes:
-
Day mode: Red Æ Red-Yellow Æ Green Æ Yellow Æ Red Æ …
-
Night mode: Yellow Æ All off Æ Yellow Æ …
The user can switch between modes by simply
pressing a Mode button:
-
When pressed (M=1) Æ change mode (every
change starts with yellow).
-
When not pressed (M=0) Æ Remain in actual
mode
Hint: The controller has 6 states to operate, namely 4 day mode states (S0=R, S1=RY,
S2=G, S3=Y) and 2 night mode states (S4=Y, S5=Off)
6.1
Complete the following State Transition Diagram! (add more transitions)
Hint:: There should always be 2 transitions from every state (for M=0 and M=1).
University of Duisburg-Essen
Faculty of Engineering
Institute of Computer Engineering
Prof. Dr. -Ing. A. Hunger
Dr.-Ing. Stefan Werner
Tutorial “Fundamentals of Computer Engineering”
WS 16/17
6.2 Complete the following State Table: (5)
Present State
Mode Input
Next State
Output
S
(Q2,Q1,Q0)
M
S+
(Q2+,Q1+,Q0+)
S0
000
0
S1
001
S0
000
1
S4
100
S1
001
0
S1
001
1
S2
010
0
S2
010
1
S3
011
0
S3
011
1
S4
100
0
S4
100
1
S5
101
0
S5
101
1
(R Y G)
100
6.2 Extract the Output functions R, Y and G as F(Q2,Q1,Q0)!
6.3 Extract the Next State functions of Q2+,Q1+,Q0+ as F(Q2,Q1,Q0,M)!
Hint: Use KV-Map and don’t cares to simplify your
results!
The FSM implementation is done using JK Flip-flop.
S
J
CP
K
Q
_
Q
R
Q n +1 = JQ n + KQ n
6.4 Based on the characteristic function of JK Flip-flop,
find out all the excitation functions of Q2+,Q1+,Q0+
namely: J2, K2, J1, K1, and J0, K0!
6.5 Draw the complete Traffic light Control Circuit implementation!