Equations and Impacts of Setup and Hold
Time
Deepak Kumar Behera and Karthik Rao C.G., Freescale Semiconductor - August 10, 2012
Before getting into any relationships, impacts or equations, let’s first have a brief overview of what
exactly is setup time and hold time.
Setup time is defined as the minimum amount of time BEFORE the clock’s active edge by which the
data must be stable for it to be latched correctly. Any violation in this required time causes incorrect
data to be captured and is known as a setup violation.
Hold time is defined as the minimum amount of time AFTER the clock’s active edge during which
the data must be stable. Any violation in this required time causes incorrect data to be latched and is
known as a hold violation.
For more information on the intra-flop aspects of setup and hold time, see reference [1].
Equations for Setup and Hold Time
Let’s first define clock-to-Q delay (Tclock-to-Q). In a positive edge triggered flip-flop, input signal is
captured on the positive edge of the clock and corresponding output is generated after a small delay
called the Tclock-to-Q. The flip flop can only do the job correctly if the data at its input does not change
for some time before the clock edge (Tsetup) and some time after the clock edge (Thold). Again, the
clock signal which circulates via clock tree throughout the design has its own variability termed as
skew.
From Figure 1 below, we derive equations for setup time and hold time. Figure 1 shows two talking
flops, the first being the launching flop and the second is obviously the capturing flop. We shall
derive equation for setup time for the capturing flop and equation for hold time for the launching
flop. However, the derived equations will be true for either of the flops or for that matter any flops in
the design.
Figure 1. Two Talking Flops Scenario
In the diagram above, at time zero FF1 is to process D2 and FF2 is to process D1. Time taken for the
data D2 to propagate to FF2, counting from the clock edge at FF1, is invariably = Tc2q+Tcomb and for
FF2 to successfully latch it, this D2 has to be maintained at D of FF2 for Tsetup time before the clock
tree sends the next positive edge of the clock to FF2. Hence to fulfill the setup time requirement, the
equation should be like the following.
Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew ------- (1)
Let’s have a look at the timing diagram below to have a better understanding of the setup and hold
time.
Figure 2. Setup and Hold Timing Diagram
Now, to avoid the hold violation at the launching flop, the data should remain stable for some time
(Thold) after the clock edge. The equation to be satisfied to avoid hold violation looks somewhat like
below:
Tc2q + Tcomb ≥ Thold + Tskew ------- (2)
As seen from the above two equations, it can be easily judged that positive skew is good for setup
but bad for hold. The only region where the input can vary is the ‘valid input window’ as shown in
Figure 3.
Figure 3. Valid Input Window
example based on setup/hold equations
Example based on Setup/Hold Equations
Consider Figure 4 consisting of two talking flops. Based on the timing details provided, we can find
out the maximum frequency at which this circuit could work without timing violations.
Figure 4. Timing Details for Two Talking Flops
Since Clock Insertion Delay is common to clock inputs for both flip-flops, it does not constrain the
maximum operating frequency for the given setup. It can be seen that this circuit does not violate
the hold constraint as given in equation (2).
Intuitively, we can look at equation (1) as follows:
(Time available for data to travel from FF1 to FF2) ≥ (Time needed for data to
travel from FF1 to FF2)
Tclk + Tskew ≥ Tc2q + Tcomb + Ts2
Tclk + 0.25ns ≥ 0.1ns + 5ns + 3ns
Tclk ≥ 7.85ns
Thus a minimum Clock Period of 7.85 ns is required to prevent setup violation. This translates to a
maximum operating frequency of 127.4 MHz.
From the above example it is clear that to improve the maximum operating frequency, any of the
following steps can be taken:
1. Decrease Tcomb between talking flops.
2. Increase Tskew if there is scope to do so.
3. Select flops with lower Tc2q and Tsetup.
Another way of looking at this is, reducing the operating frequency of the system helps mitigate
setup violations, if any.
Impact of Setup/Hold constraints on Clock to Q Delay
Since latching circuit in a Flip-Flop is a back to back inverter (o/p of one inverter is i/p to the other
inverter, as shown in Figure 5), the I/O characteristic, as shown in Figure 6, is derived from the
characteristic of single inverter.
For the purpose of explanation, let’s say 0V corresponds to logic LOW and 5V corresponds to logic
HIGH. As seen from the adjacent diagram, if any value other than a perfect 0V or 5V is given as
input to this back-to-back inverter, it will take some latching cycles to produce a stable inverted o/p.
This delay accounts for the C2Q delay.
Figure 5. Back-to-back Inverters for Latching Action
Figure 6. IO Characteristics
If such delays accumulate over flops it may so happen that a data signal is missed by the clock edge
at which it was supposed to be captured.
About the authors:
Deepak Kumar Behera is a design engineer in Freescale Semiconductor, India Pvt. Ltd. with two
years experience in power integrity, signal integrity and package analysis. Karthik Rao C.G. is a
design engineer in Freescale Semiconductor, India Pvt. Ltd. with two years experience in digital IP
design.
Reference
[1] Understanding the basics of setup and hold time