Modeling a Low Cost Wafer Bumping Technique for Flip Chip Application
Modeling a Low Cost Wafer Bumping Technique
for Flip Chip Application
Tennyson A. Nguty and Ndy. N. Ekere
Electronics Manufacture and Assembly Group
Department of Aeronautical, Mechanical, and Manufacturing Engineering
University of Salford
Salford M5 4WT
United Kingdom
Phone: +44 161 295 4696
Fax: +44 161 295 5575
e-mails: [email protected], [email protected]
Abstract
The trend to minimize chip package size and to increase the number of connection to the PCB continues, but current forecasts indicate
that increased chip operating speeds will no longer tolerate the impediment that even minimal packaging and connection methods
impose in the signals flowing to and from the chip. While the Chip Scale Package (CSP) format provides interim solution required by
the industry, more companies are gearing up to achieve volume production of Flip Chip assembly. One of the key parameters that is
critical to achieving volume production of Flip Chip is consistency in solder bump heights, as it will directly impacts the reliability of
the solder joints.
This paper concerns the modeling of the solder bump dimensions (height and diameter) of bumped wafers for solder bumped, and
reflow soldered Flip Chip assemblies. Due to the dominant effects of surface tension, the equilibrium shape of the solder bumps can
be approximated to a truncated sphere. The base of the bump is defined by the geometry and dimension of the under bump metallization (pad). The model incorporates the effects of the deposited solder paste volume, the pad size, and the pitch. This model based
on stencil printing, a potentially low cost method in depositing solder paste, has wide utility, and can be easily adapted to other
component geometries.
Key words:
Flip Chip, Solder Bump Volume, Solder Bump Height, Solder
Bump Diameter, Truncated Sphere, and Wafer Bumping.
1. Introduction and Background
The need to reduce the size of electronic modules (miniaturization) and the development of more sophisticated integrated
circuits (IC) with increasing number of I/Os, make the use of
Flip Chip technology, even in low end products inevitable. The
main benefits of Flip Chip include lower cost when compared to
many standard packages currently in use, improved device performance, smaller space requirement, and better functionality.
There are, currently, several methods in achieving Flip Chip devices7,11 and possible low cost alternatives2,5,6.
Solder bumping technique for Flip Chip assemblies requires
design considerations regarding both bump pitch and sizes. As
component sizes decrease, the constraint on the volume required
for a reliable assembly becomes even greater. From this constraint in the required volume, a wide enough gap, between the
substrate and the die (the stand-off height), must be attained so
that it can be underfilled after the die has been attached to the
substrate. The stand-off height must be wide enough so that the
underfill material can flow evenly and completely fill this gap. If
this height is too narrow, it will not be completely filled which
can lead to failures in the solder joints. Variation in bump heights
on the die can be attributed to a range of factors including how
the solder wets and reacts with the pads.
Accurate prediction of solder bump height is important for
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estimating the reliability of a given joint configuration and, consequently, for designing optimal joints. Solder bump dimensions
are dependent on a range of variables including initial paste volume, pad size, and geometry. The design for manufacturability
needs quantitative guidelines on the geometry and the solder bump
volume. In addition, the stress-related reliability problems are
dependent on the joint profile and height, hence the need to predict bump dimensions. The truncated section of the bump is
confined to the pad, and surface tension effect determining the
final bump shape. This collapsed shape of the solder joint sets
the height of the assembly. As the bump pitch decreases, the
maximum volume of the solder that can be deposited on the pad
also decreases. This is a major concern for PCB board technology regarding the manufacture of smaller pads and tracks. As a
result, it is necessary to optimize the required solder volume for
any bump pitch. Pfeifer9 modeled the bump dimensions whereby
the deposition of solder paste was by electroplating.
In this paper, the authors modeled the dimensions of solder
bumps based on stencil parameters (aperture volume). This is
used to determine the optimum size of stencil parameters required for any bump dimension. Such modeling will be particularly useful to wafer bumping companies that supply bumped
wafers. This will aid engineers in the manufacturing of solder
bumped wafers to match customer requirements and specifications. A major benefit of this approach is that, the stencil printing process is already widely used in the electronics assembly
industry, with low cost, and hence can be easily adapted1,10,12,13.
2. Flip Chip assembly Process
Description and Modeling
In this section, description of the device for the assembly process and some of the analyses involved in the process will be
described.
2.1. Process Description
w
Electrical testing of assembly for functionality, and reliability testing.
A schematic representation of the process route is shown in
Figure 1. In this paper, the authors shall be concentrating on
stages 1 and 2 in the process route (Figure 1) which constitutes
the “wafer bumping” process.
Chip passivation
Solder paste
i.]
Printed solder paste on wafer
ii.]
Reflowed wafer with solder bump shaped
like truncated sphere with height, h1
iv.]
Paste thickness (h2) on substrate after stencil
printing
iii.]
Chip placement on substrate before reflow.
v.]
Flip chip assembly showing the final stand-off
height between chip and substrate. Shape of
joint is a “double truncated sphere”.
Si
Al bond pad
Solder wettable layer (Ni/Au)
h1
Pad on PCB
Solder paste
h2
Figure 1. Schematic of a Flip Chip assembly process route
by stencil printing.
2.2. Process Modeling
To model the wafer bumping process, it is essential to examine the variables that can affect the final bump height. These
variables includes the following factors,
w
Solder paste type (percentage of solder metal content)
w
Solder paste volume (Figure 1)
w
Pad size and geometry on the wafer.
Prior to modeling the solder bump dimensions (height and
diameter), other sub-stages identified in the process route will be
investigated.
(a) Solder Paste Volume Shrink Factor After Reflow
Paste deposition method is through stencil printing. The nominal volume of the aperture in the stencil is given by equation (1),
while x and y define the aperture dimensions with stencil of thickness, h. The volume of paste transfer, Vt, is approximated to be
k-times the volume of aperture, Va. The empirical results show
that k varies between 0.8 and 1.2 approximated to a percentage
of the volume as shown in equation (2).
The deposition of solder paste onto the wafer can be carried
out by a number of ways7,11. The researchers shall be concentrating on stencil printing as the deposition method due to its low
cost potential, and compatibility to current technology. The process route for achieving a Flip Chip assembly by stencil printing
includes the following stages, as shown in Figure 1. These stages
include the following,
w
Printing of solder paste onto the wafer,
w
Reflow soldering to form solder bumps on the wafer,
w
Wafer dicing to obtain chips/die,
w
Printing of solder pastes (or flux) onto PCB pads,
w
Placement of bumped chips onto PCBs,
w
Reflow soldering of assembly (bumped chips on board),
w
Apply underfill between the die and PCB, then cure the
assembly, and
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Modeling a Low Cost Wafer Bumping Technique for Flip Chip Application
Va = o r2 h
=xyh
...circular aperture
.....oblong aperture
(1)
(7)
(2)
Upon reflow, there is a change in volume due to the evaporation of the flux/vehicle system present in solder paste. A simplified form of the relation between Vt and the reflow volume, Vr, is
shown in equation (3), where a is the “shrink factor”.
Vr = a Vt
Solder bump
2R = D
h1
Bump diameter
D = 2R
Pad Diameter
d = 2r
(3)
Note that a, the shrink factor, is less than 1, and will depend
on solder paste type (that is the metal content). The volume of
solder, Vr, can be estimated by direct volume measurement or
from the density of solder. From equation (1), the final volume
can be empirically estimated when the volume of apertures are
known, which is always the case. The empirical studies in this
work so far estimates a in the region of 0.45-0.55, which is similar to the metal content by volume of the solder paste.
(b) Solder Bump Height Prediction
In this sub-section, a model for the final solder bump dimensions in terms of the height and the diameter is presented. This
is achieved by incorporating the shrink factor as discussed earlier. The variables known in this case are the reflow volume, Vr,
through equation (3) and the pad size on the wafer. The objective is to determine the paste volume required to achieve a target
bump height given the constraint in pad size and the pitch on the
wafer without defects. This will provide essential guidelines and
possible limits in solder bump pitch for a given stencil design
(aperture size and thickness).
Due to the surface tension effects and the wettability of the
pads, the shape of the solder bumps after reflow assumes a truncated sphere as shown in Figure 2. In Figure 2, D is the reflow
solder bump diameter, while d is the pad diameter (a circular pad
has been chosen for simplicity), and h1 is the bump height. The
truncated end is defined by the pad diameter, as solder will not
wet the passivation layer. The volume of the truncated solder
bump can be expressed as functions of the parameters R, r, and
h1, as shown in equations (4) - (6 )(see appendix A for the derivation of equation (6)).
(4)
(5)
(6)
The relationships between R, r, and h1, shown in equation (7),
have been used in to derive equation (5).
(i) SEM photograph
(ii) Diagram showing cross section
Figure 2. Solder bump shape8 on pads and a schematic
representation.
Equations (4)-(6) should yield the same values for the solder
bump volume. Since d is always defined, using equations (5)
and (6), the bump height h1, and the diameter D, can be estimated. Changing the paste transfer volume, Vt, as shown in
Figure 3, the diameter and the height, D and h1, respectively, of
the bump can be altered. Three cases have been illustrated in
Figure 3. The amount of solder paste deposited on the pads with
diameter, d is altered through the stencil aperture diameter v.
When v [ d, the pitch of the device is the limiting parameter, else
over printing is carried out with v > d. This results in three
configurations in solder bump shape/size after reflow as shown
in Figure 3.
Stencil aperture
diameter (φ)
φ<d
φ=d
φ>d
Solder paste
Reflow
Solder bump
Pad Diameter
Figure 3. Effects of paste volume on solder bump height
and diameter for a given pad size.
As the printed volume of solder paste increases both R and h1
of the bump increases (see Figure 4 and Tables 1-3). It becomes
a critical factor at Flip Chip pitches (100-150µm) as shown in
Figure 4. It is also a major concern as there are many wafers
designed for wirebonding whereby the gap between pads is very
small. The printed volume has to be optimized so that, adjacent
bumps on the die are defects free (that is not touching). As the
solder volume increases from V to Vi, the distance between adjacent bumps decreases (Figure 4). If this distance is denoted by xi,
(safety gap) then, the pitch of the device can be expressed as
shown in equation (8). The condition for adjacent solder bumps
not to touch is xi > 0, and hence from equation (8), l > 2R.
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l = 2R + xi
(8)
Table 2. Predicted bump dimensions from square stencil apertures
for different wafer pad sizes assuming a paste shrinkage factor of
50%. (* = under-printing where bump and pad diameters are equal.)
xi: Separation distance between bumps
Increased solder volume
from over-printing (VI)
Small solder volume (V)
2R
Solder bump pitch
2R
l
Figure 4. Effect of increasing solder volume on bump
separation distance.
In Tables 1-3, equations (1)-(7) have been used to predict the
bump height and the diameter, for a range of apertures shapes
and sizes on a 2 and 3 mil thick stencil for various pad sizes on a
wafer. Assumptions were made for the transfer ratio of 80% (k
in equation (2)) and the pads on the wafer being very far apart.
The different aperture shapes and sizes can be used depending
on the pad layout (that is the peripheral or full array) and pitch
constraints on the die. The oblong apertures will suit peripherally arranged pads and can provide more paste volume and higher
bump height when required.
Table 1. Predicted bump dimensions from circular stencil
apertures for different wafer pad sizes assuming a paste shrinkage
factor of 50%. (* = under-printing where bump and pad diameters
are equal.)
Table 3. Predicted bump dimensions from oblong stencil apertures for
different wafer pad sizes assuming a paste shrinkage factor of 50%. *
represents under-printing where bump and pad diameters are equal.
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Modeling a Low Cost Wafer Bumping Technique for Flip Chip Application
From Tables 1-3, the following can be concluded,
w For the same pad size, a square aperture, of sides v, will produce a higher bump height for the same stencil thickness when
compared with a circular aperture of diameter v. This is due
to the difference in surface area between a circle and a square.
w For the same volume of paste deposited, larger bump height
will be obtained from circular than square pads. This can be
attributed again to the surface area difference.
Issues relating to the effects of both aspect and area ratios in
the stencil design have been included3,4 in Tables 1-3. The ratio
of area to be printed on the substrate to that of the aperture walls
relates to the area ratio. Meanwhile, the aspect ratio relates the
aperture width to the stencil thickness, h. These expressions
largely determine whether the paste will completely release from
the stencil giving consistent paste deposit volume. The generally accepted guide for stencil design is for area and aspect ratios
greater than 0.66 and 1.5, respectively,3,4 for SMDs shown in
equations (9) and (10), with a square aperture of sides, x.
(b)3 mil thick stencil, 6 mil by 13.5 mil oblong aperture, Area
ratio 0.69
(c) 3 mil thick stencil, 9 mil square aperture, Area ratio 0.75
(d)2 mil thick stencil, 8 mil by 15 mil oblong aperture, Area
ratio 1.30
(e) 2 mil thick stencil, 9 mil by 13.5 mil oblong aperture, Area
ratio 1.35.
The above five choices have aperture width less than the pitch
constraint (12 mil). Options d and e have larger area ratios,
hence option d will be the best choice as it provides a greater
spacing between pads to avoid paste bridging.
As a guide, in cases when more than one possibility is found
from Tables 1-3, other issues have to be considered including the
following,
w Area ratio: the higher the better,
w I/O layout restrictions: Peripheral or full array, and
w Ability to manufacture stencil and cost.
(9)
(10)
Tables 1-3 are considered to be used as a guideline for the
bumping process. The information predicts the dimensions of
the solder bump on an isolated pad. To make use of this Table,
both the pad size and the pitch of the device must be known, as
the pitch determines how big the stencil aperture can be for a
required bump height. If one assume two cases of wafer bumping using Tables 1-3,
3. Summary and Validation of Model
The model has been applied to experimental data collected
for dimensions of bumped wafers by various research groups using stencil printing, and is shown in Table 4.
Table 4. Validation of model from a variety of bumped
wafers.
w Case 1: 12 mil pitch full array layout with 3 mil circular pads
on the wafer and a target bump height of 4.5 mil, the following aperture designs from Tables 1-3 are found,
(a) 2 mil thick stencil, 8.9 mil square aperture, Area ratio 1.11
(b)2 mil thick stencil, 10.1 mil diameter circular aperture, Area
ratio 1.26
(c) 3 mil thick stencil, 7.3 mil square aperture, Area ratio 0.61
(d)3 mil thick stencil, 8.2 mil diameter circular aperture, Area
ratio 0.68
(e) Oblong apertures would not be suitable if the density of the
bumps and a full array device.
It can be seen from Table 4 that the error in the bump height
is quite small (<5%) for the fine pitch applications. In Nguty8,
the bump height error is an order of magnitude higher. This can
suggest that at these sort of aperture geometries (6 mil x 6 mil on
a 3 mil thick stencil), a 50% shrink factor (a in equation (3)) is a
From the above choices, options a or b are suitable designs.
slightly higher estimate.
Due to the pitch restrictions on stencil manufacture, option a
The authors have presented a process model for predicting
might be the best.
the dimensions of solder bumps obtained during wafer bumping
based on stencil parameters. These parameters are either known
w Case 2: Peripherally arranged 3 mil circular pads on 12 mil
or can be measured. It was found that, for the same volume of
pitch, and a bump height of 5 mil is required. From Tables 1paste, the smaller pads on the wafer produced higher bump
3, the following stencil designs are found,
heights. In addition, to achieve higher bump height from the
same volume of paste, it is advisable to have the pad geometries
(a) 3 mil thick stencil, 8 mil by 10.1 mil oblong aperture, Area
with smaller surface area. The data presented will be a vital
ratio 0.74
source of information for companies that provide wafer bumping
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Intl. Journal of Microcircuits and Electronic Packaging
facilities. As part of this on-going work, the researchers hope to
apply this model for wafer bumping of devices at sub 100 mm
pitch by stencil printing. Preliminary results suggest that the
shrinkage factor at these pitches would be less than 50%.
Acknowledgments
The authors would like to acknowledge the support of their
industrial partners [Celestica Limited UK, DEK, Multicore Solders Ltd. UK], and the Engineering and Physical Sciences Research Council [EPSRC], UK who are funding this work under
Grant No. GR/L61767.
About the authors
Tennyson A. Nguty received the B.Sc (Hons) in Maths-Physics from the University of Leicester (UK) in 1991. He later obtained the M. Sc. and Ph.D. Degrees in Applied Optics from the
University of Salford in 1993, and 1997, respectively. He is currently working as a Post Doctoral Research Assistant at the University of Salford, U.K. He is a member of the Institute of Physics (IOP) and the British Society of Rheology (BSR).
Ndy. N. Ekere received the M. S Degree in 1984 and a Ph.D.
Degree in 1987 in Manufacturing Engineering from
Loughborough University of Technology, U.K. and the University of Manchester Institute of Science and Technology, U.K. respectively. He currently holds a Chair in Electronics Manufacturing in the Department of Aeronautical, Mechanical and Manufacturing Engineering, University of Salford, U. K. He is engaged mainly in research into soldering and electronics packaging technology. Prof. Ekere is a Chartered Engineer and a member of the IEE.
References
cations and Stencil Design Guides,” Proceedings of the Surface Mount International, pg. 492, 1994.
5. R. F. Cooley, “Low cost MCM-L Flip-Chip Interconnection
Utilising Gold Ball Bumping,” Proceedings of the International Symposium on Microelectronics, ISHM ‘94, Boston,
Massachusetts, pp. 473-478, 1994.
6. D. J. Hayes and D. B. Wallace, “Solder Jet Printing for Low
Cost Wafer Bumping,” Proceedings of the International Symposium on Microelectronics, ISHM ‘96, Minneapolis, Minnesota, pp. 296-301, 1996.
7. N. Lee, “Soldering For Area Array Packages”, NEPCON
WEST, Anaheim, California, March 1999.
8. T. A. Nguty et al., “Low Cost Flip Chip Assembly,” In the
Press.
9. M. J. Pfeifer, “Solder Bump Size and Shape Modelling and
Experimental Validation,” IEEE Transactions on Components,
Packaging, and Manufacturing Technology – Part B, Vol. 20,
No. 4, pp. 452-457, 1997.
10. S. Popelar and C. A. Erickson, “A Low Cost Wafer Bumping
Process for Flip Chip Applications”, Proceedings of the Annual Emerging Technologies Symposium, Chandler, Arizona,
November 1998.
11. G. A. Rinne, “Solder Bumping Methods of Flip Chip Packaging,” Proceedings of the Electronic Components and Technology Conference, ECTC ‘97, pp. 240–247, 1997.
12.A. J. G. Strandjord, S. Popelar, and C. A. Erickson,
“Commercialisation of a Low Cost Wafer Bumping Process
for Flip Chip Applications”, IMAPS Workshop on Flip Chip
Applications, Braselton, Georgia, March 1999.
13. A. J. G. Strandjord, S. Popelar and C. A. Erickson, “Low
Cost Wafer Bumping Processes for Flip Chip Applications
(Electroless Nickel-Gold / Stencil Printing)”, Proceedings of
the 32nd International Symposium on Microelectronics, IMAPS
’99, Chicago, Illinois, October 1999.
Appendix A
Derivation of an expression for the Solder
Bump volume as a function of the pad and
bump radius.
1. J. H. A driance, M. A. Whitmore, and J. D. Schake, “BumpThe volume of a sphere of radius R (bump radius), can be
ing of Silicon Wafers by Stencil Printing”, Proceedings of the
calculated from V = 4 π R 3 . In order to estimate the volume of the
3
24th IEMT Symposium, Austin, Texas, pp. 313-319, 1999.
bump (Figure A-1) as a function of both r and R, the pad and the
2. K. Boustedt and P. Hedemalm, “The Nordic Flip Chip Project
bump radius, respectively, the volume function has to be inteExperimental Studies,” Proceedings of the 10th European
grated. This solder bump volume Vr can be expressed as a sumMicroelectronics Conference, Copenhagen, pp. 493-498,
mation of VT and VL which represents the volumes of the top half
1995.
and truncated sections, respectively. From the expression of the
3. W. Coleman and R. Myklak, “The Design and Manufacturvolume of a sphere,
ing of Metal Mask Stencils-Meeting the Challenge of Fine
Pitch Technology,” Surface Mount Technology, pg. 26, 1990.
(A1)
4. W. Coleman and K. Aeschliman, “Stencil Printing – AppliThe International Journal of Microcircuits and Electronic Packaging, Volume 22, Number4, Fourth Quarter 1999 (ISSN 1063-1674)
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© International Microelectronics And Packaging Society
Modeling a Low Cost Wafer Bumping Technique for Flip Chip Application
Volume of top
half of sphere VT
R
h
r
Volume of lower
half of sphere VL
Figure A-1. Schematic of solder-bump and dimensions.
From a volume element,
dVL = o y2 dx = o [R2 - x2]dx
(A2)
From Figure A-1, h = R + [R2 - r2]1/2, and equation (A2) becomes,
(A3)
Hence, the volume of the bump, Vr, expressed as a function of the
bump and pad radii R, and r, respectively, can be represented as
follows,
(A4)
This equation is identical to equation (6).
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