MLR INSTITUTE OF TECHNOLOGY
Dundigal, Hyderabad - 500 043
COMPUTER SCIENCE AND ENGINEERING
OBJECTIVE QUESTION BANK
Course Name
Course Code
Class
Branch
Year
Course Faculty
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COMPUTER ORGANIZATION
A40506
II B. Tech II Semester
Computer Science and Engineering
2014 – 2015
Prof.K.L.Chugh, D. Bheekya
OBJECTIVES
To meet the challenge of ensuring excellence in engineering education, the issue of quality needs
to be addressed, debated and taken forward in a systematic manner. Accreditation is the principal
means of quality assurance in higher education. The major emphasis of accreditation process is
to measure the outcomes of the program that is being accredited.
In line with this, Faculty of M L R Institute of Technology, Hyderabad has taken a lead in
incorporating philosophy of outcome based education in the process of problem solving and
career development. So, all students of the institute should understand the depth and approach of
course to be taught through this questioFn bank, which will enhance learner’s learning process.
UNIT I
1. The access method used for magnetic tape is_________
a) Direct
b) Random c) Sequential d) None of the above
2. The difference between memory and storage is that the memory is__________ and
storage is_________
a) Temporary, permanent b) Permanent, temporary
c) Slow, fast
d) None of the above
3. The language that the computer can understand and execute is called ______
a) Machine language
b) Application software
c) System program
d) None of the above
4. The part of machine level instruction, which tells the central processor what was to be
done is
(a) Operation code (b) Address
(c) Operand (d) None of the above
5. The communication line between the CPU, memory and peripherals is called a
a) Bus b) line
c) media
d) none of these
6. The Central Processing Unit:
a) Is operated from the control panel.
b) Is controlled by the input data entering the system
c) Controls the auxiliary storage unit
d) Controls all input, output and processing.
7. The command field corresponds to an operation code that specifies ___ basic types of I/O
operation
a) 2 b) 4 c) 6 d) 8
8. The operations performed on the data in the processor constitutes a _________ stream
a) Instruction
b) data
c) both
d) none
9. The load instruction is mostly used to designate a transfer from memory to a processor
register known as____.
A. Accumulator
B. Instruction Register
C. Program counters D. Memory address Register
10. A group of bits that tell the computer to perform a specific operation is known as____.
A. Instruction code B. Micro-operation
C. Accumulator
D. Register
11. A k-bit field can specify any one of_____.
A. 3k registers
B. 2k registers
C. K2 registers
D. K3 registers
12. The average time required to reach a storage location in memory and obtain its contents
is called_____.
A. Latency time.
B. Access time. C. Turnaround time. D. Response time.
13. _________ Register keeps tracks of the instructions stored in program stored in memory.
A. AR (Address Register)
B. XR (Index Register)
C. PC (Program Counter) D. AC (Accumulator)
14. n bits in operation code imply that there are ___________ possible distinct operators.
A. 2n
B. 2n
C. n/2
D. n2
15. An n-bit microprocessor has_____.
A. n-bit program counter
B. n-bit address register
C. n-bit ALU
D. n-bit instruction registers
16. A Stack-organized Computer uses instruction of _____.
A. Indirect addressing
B. Two-addressing
C. Zero addressing
D. Index addressing
17. In a program using subroutine call instruction, it is necessary______.
A. initialize program counter
B. Clear the accumulator
C. Reset the microprocessor
D. Clear the instruction register
18. The addressing mode used in an instruction of the form ADD X Y, is _____.
A. Absolute B. indirect
C. index
D. none of these
19. Computers use addressing mode techniques for ____________.
(a) giving programming versatility to the user by providing facilities as pointers to
memory counters for loop control
(b) to reduce no. of bits in the field of instruction
(c) specifying rules for modifying or interpreting address field of the instruction
(d) All the above
20. In Reverse Polish notation, expression A*B+C*D is written as
A. AB*CD*+
B. A*BCD*+
C. AB*CD+*
D. A*B*CD+
21. The BSA instruction is______.
A. Branch and store accumulator
B. Branch and save return address
C. Branch and shift address
D. Branch and show accumulator
UNIT II
1. The address of I/O device is communicated using
A. Data buses
B. Data Lines
C. Address bus
D. Status line
2. The command is used to activate the peripheral and to inform it what to do is
a. Control command
b. status command
c. data input command
d. data output command
3. the command that causes the interface to respond by the transforming data from the bus
into one of its register
a. Control command
b. status command
c. data input command
d. data output command
4. In asynchronous data transfer, both sender and receiver accompany a control signal that is
a. Strobe
b. Handshaking
c. Two wire control d. Single wire control
5. The command is used to test various status conditions in the interface and peripherals is
b. Control command
b. status command
d. data input command
d. data output command
6. In the following which mapping uses different address space for memory and I/O?
a. memory mapped I/O
b. Isolated I/O
c. Independent I/O
d. interrupt driven I/O
7. The rate at which serial information is transmitted and is equivalent to the data transfer in
bits per second is
a. Baud rate
b. bit rate
c. control rate
d. strobe rate
8. In the following which uses separate controller for data transfer
a. Programmed I/O b. Interrupt Initiated I/O
c. DMA
d. all the equally efficient
9. In polling, the drawback is
a. Cost is more complex
b. hard ware required
c. time consuming
d. maintenance is more
10. In priority interrupt when two devices interrupt the computer at the same, the computer
services the device
a. With the large length at first
b. With the large length at first
c. With the highest priority at first
d. with the highest priority at first
11. Continuously monitoring I/O devices done in
a. Programmed I/O b. Interrupt Initiated I/O
c. DMA
d. memory mapped I/O
12. A block sequence consisting of a number of memory words is transferred continuously
while a DMA controller is a master of memory bus. This is
a. Polling
b. Daisy Chaining
c. Burst transfer
d. Cycle Stealing
13. The DMA controller acts like
a. Primary Memory b). CPU
c). Cache Memory
d). Router
14. The number of basic I/O commands in IBM 370 computer IOP is
a) 50
b) 6
c) 8
d. 40
15. The number of basic I/O commands in Intel 8089 computer IOP is
a. 50
b) 6
c) 8
d)40
16. The Intel 8089 I/O processor contains the IC package of
a) 64 pins
b)40 pins
c)16 pins
d)32 pins
17. A Processor with Direct Memory Access capability that communicates with I/O devices
is
a) Input Output Processor
b) Data communication processor
c) Data communication programmer
d) Input Output programmer
18. A processor that communicates with remote terminals over telephone and other
communication media in a serial fashion is called
A) Input Output Processor
b) Data communication processor
c) Data communication programmer
d) Input Output programmer
19. The I/O processor in IBM 370 computer is called
a) Router
b) Channel
c) Device
d) Modem
20. The _ _ _ _ _ _ _ _ _ _ architecture represents the organization of a computer containing
a single control unit, a processor unit and a memory unit.
a. SIMD
b)MISD
c)SISD
d)MIMD
21. Interfaces to memory and I/O devices are made through
A. Central Switch
B. Buses
C. Data links
D. All of the above
22. I/O command type
A. Read
B. Control
C. Test
D. All the above
23. This technique for data transfer does not involve the processor
A. Direct Memory access B. Programmed I/O
C. Memory-mapped I/O
D. All the above
24. In an Interrupt -driven I/O, when an interrupt is detected, details on the current processor
condition is stored in
A. Return address register
B. Program counter
C. Program status word
D. Memory bank
25. Control Register And Status Register determine the control and status of the device connected.
26. An ACK or acknowledgment is a Bus grant signal sent between them CPU and I/O device.
27. Interface is used in I/O modules to help in transfers as the transfer rate difference between
processor and external devices are quite large.
28. Main drawback of programmed-I/O is a Time consuming transfer and the CPU being busy with
the I/O transfer.
29. The CPU sends the address of the I/O device to the DMA controller to read or write data into it.
UNIT III
1. Bootstrap loader requires
a. RAM
b. ROM
c. any memory
d. processor
2. In memory hierarchy, the following memory has least capacity
a. Register
b. Cache memory
c. Main Memory
d. Magnetic tape
3. The part of the computer system that supervises the flow of information between
Auxiliary Memory and Main Memory is called
a) Processor Management System b)Data Management System
c) Address Management System
d) Memory Management System
4. Existence of two or more programs in different parts of the Memory Hierarchy at the
same time is defined as:
a) Uni programming b)Multi programming c)Multi processing d)Uni processing
5. If Cache Access time is 100ns, Memory access time is 1000ns, if the hit percentage is
100%, what is the Average access time
a. 100
b)1000
c)1100
d)10
6. If both Cache Memory and Main Memory are updated for a write operation, the type of
the Cache Memory is called
a. Write-back
b)Write-through
c)Associative d)TLB
7. If only Cache location is updated during a Write operation as long as there is no
replacement, the type of the Cache Memory is called
a. Write-back
b)Write-through
c)Associative d)TLB
7. Replacing the block that has been not used for the longest period of time is
a. FIFO
b)LRU
c)MRU
d)LFU
8. Replacing the page that entered the Memory at first is
a. FIFO
b)LRU
c)MRU
d)LFU
9. A faster and smaller Memory in between CPU and main Memory is
a. Primary Memory b)Secondary Memory c)Cache Memory
d)Auxiliary Memory
10. If Hit ratio is 0.8, the miss ratio
a. 9.2 b)92 %
c)0.2 d)20 %
11. In the following, which is not a Cache Mapping Technique?
a. Associative Mapping
b)Direct Mapping
c) Test-Associative Mapping
d) Set-Associative Mapping
12. In four-way Set-Associative mapping, the number of tags is
a. One
b)Two
c)Four
d)Sixteen
13. In the following, which is the fastest mapping technique?
a. Direct Mapping
b)Associative Mapping
c) Test-Associative Mapping
d) Set-Associative Mapping
14. The transfer of data between main Memory and Cache is
a. WORD
b)BLOCK
c)LINE
d)CHARACTER
15. In Paging technique, the logical address space is
a. Divided into equal parts
b)Divided into unequal parts
c) Divided into two parts
d) either equal or unequal parts
16. The average time required to reach a storage location in memory and obtain its contents is
called_____.
A. Latency time.
B. Access time. C. Turnaround time. D. Response time.
17. Memory unit accessed by content is called______.
A.
Read only memory B.
Programmable Memory
C.
Virtual Memory
D.
Associative Memory
18. Cache memory works on the principle of_____.
A.
Locality of data
B.
Locality of memory
C.
Locality of reference D.
Locality of reference & memory
19. Virtual memory consists of _______.
A.
Static RAM
B.
Dynamic RAM
C.
Magnetic memory D.
None of these
20. Generally Dynamic RAM is used as main memory in a computer system as it______.
A.
Consumes less power
B.
has higher speed
C.
has lower cell density
D.
needs refreshing circuitry
21. Cache memory acts between_______.
A.
CPU and RAM
B.
RAM and ROM
C.
CPU and Hard Disk D.
None of these
22. Replacing the block that has been not used for the longest period of the time is
a. FIFO b. LRU
c. MRU
d. LFU
23. If the cache memory access time is 100ns, main memory access time is 1000ns, if the hit
ratio is 100%, what is average access time?
a. 100ns
b. 1000ns
c. 1100ns
d. 110ns
24. The transfer of data between main memory and cache memory is
a. Block
b. frame
c. word
d. character
25. The technique of paging suffers with ________fragmentation.
a. Internal
b. external
c. both
d. neither internal nor external
26. If there are 16 bits in the virtual address format, the size of the virtual address is
a. 16K words
b. 16 words c. 16M words
d. 64K words
27. In the following, which is not a physical memory
a. Main memory
b. secondary storage c. cache memory
d.
virtual
memory
UNIT IV
1. Intel 8086 has 6-byte queue
2. Semiconductor memory has ___ memory cell
a) Slow
b)fastest
c)lowest
d)highest
3. Which of the following is a 16-bit microprocessor?
a) Intel 8085
b)Intel 8086 c) Zilog 0
d)Motorola 6800
4. Address bus of Intel 8085 is ____ bit wide
a) 2
b)4
c)8
d)16
c)Intel 5005
d)Intel 6006
5. The first microprocessor is
a)
Intel 3003
b)Intel 4004
6. The _____ was the first hand held calculator to perform transcendental functions
a)
HP-32
b)HP-33
c)HP-34
d)HP-35
7. _____ technology has allowed us to put a complete CPU on a single chip
a)
LSI
b)MSI
c)VLSI
d)SSI
8. Example of embedded computer system is
a) personal computer
b)fax machine
c)printer
d)keyboard
9. Modern ___ processors can execute one instruction per clock cycle
a) RISC
10. Access time is faster for
b)CISC
c)RISK
d)CISK
a) ROM b)SRAM
c)DRAM
11. The conditional branch instruction JNS performs the operations when if __
a) ZF =0
b)SF=0
c)PF=0
d)CF=0
12. SOD pin can drive a D flip-flop?
a) SOD cannot drive any flip-flops.
b) SOD cannot drive D flip-flop, but can drive any other flop-flops.
c) Yes, SOD can drive D flop-flop.
d) No, SOD cannot drive any other flop-flops except D flop-flop.
18. IDIV and DIV instructions perform the same operations for?
a) Unsigned number b)Signed number
c)Signed number & Unsigned number
d) None of above.
19. What is the output of the following code AL=88 BCD, CL=49 BCD, ADD AL, CL DAA
a) D7, CF=1
b)37, CF=1
c)73, CF=1
d)7D, CF=1
20. What is the output of the following code?
AL= 49 BCD, BH= 72 BCD
SUB AL, BH
DAS
a) AL=D7, CF=1. B) AL=7D, CF=1.
C) AL=77, CF=1
d) none of them.
21. What is the output of the following code?
AL= -28 decimal, BL=59 decimal
IMUL BL
AX=? , MSB=?
A) AX= F98CH, MSB=1.
B) AX= 1652, MSB=1.
C) BX = F9C8H, MSB=1.
D) BX= 1652, MSB=1.
22. What is the output of the following code?
AL= 00110100 BL= 00111000
ADD AL, BL
AAA
a) AL = 6CH
b)12H
23. What is the output of the following code?
AL=00110101 BL= 39H
SUB AL, BL
AAS
c)12
d)C6H
a) AL= 00000100, CF=1
b)BL=00000100, CF=z
b) AL=11111100 CF=1
d)BL= 00000100, CF=1
24. What is the output of the following code?
CF =0, BH = 179
RCL BH, 1
a)
CF=0, OF= 1, BH= 01100101
b)CF=1, OF=1, BH=01100110
c)CF=1, OF =0, BH= 01001101
d)CF=0, OF=0, BH=00101100
25. What is the output of the following code?
SI=10010011 10101101, CF=0
SHR SI, 1
a) 37805, CF=1, OF=1
b)18902, CF=1, OF=1
c) 19820, CF=1, OF=1
d) 53708, CF=1, OF=1
26. What is the output of the following code?
PUSH AL
a) Decrement SP by 2 & push a word to stack
b) Increment SP by 2 & push a word to stack
c) Decrement SP by 2 & push a AL to stack
d)Illegal
27. In 8086 microprocessor one of the following instructions is executed before an arithmetic
operation
a) AAM
b)AAD
c)DAS
d)DAA
UNIT V
1. In 8086, Example for Non mask able interrupts is
a) Trap
b)RST6.5
c)INTR
2. What does microprocessor speed depends on?
a) Clock
b)Data bus width
c)Address bus width
3. Can ROM be used as stack?
a) Yes
b)No
c)sometimes yes, sometimes no
4. Which processor structure is pipelined?
a) all x80 processors
b)all x85 processors
5. Address line for RST3 is?
a) 0020H
6.
b)0028H
In 8086 the overflow flag is set when
c)0018H
c)all x86 processors
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
d)During subtraction
7. What do the symbols [ ] indicate?
(A) Direct addressing (B) Register Addressing (C) Indirect addressing (D) None
8. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b)Odd bank memory
c)I/O
d)DMA
9. In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI
b)DIV 0
c)TYPE 255 d)OVER FLOW
10. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode b) Coprocessor is interfaced in MIN
mode
b)
I/O can be interfaced in MAX / MIN mode
d)Supports pipelining
11. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
coprocessor
b)Address capability
c)Support
of
d) Support of MAX / MIN mode
12. Address line for TRAP is?
a) 0023H
b)0024H
c)0033H
13. IDIV and DIV instructions perform the same operations for?
a) Unsigned number b) Signed number c) Signed number & Unsigned number d) none of
above
14. The CMP instruction modifies the
a) program counter b)instruction register c) flags register
register
d)segment
15. Conditional instructions typically inspect the
a) program counter b)instruction register c)flags register
d)accumulator
16. The BP register is typically used for accessing
a) strings
segment
b)memory
c)stack
d)data
17. What is the output of the following code
AX = 37D7H, BH = 151 decimal
DIV BH
a) AL = 65H, AH= 94 decimal
b) AL= 5EH, AH= 101 decimal
c) AH= E5H, AL= 5EH
d) AL= 56H, AH= 5EH
18. In 8086 microprocessor one of the following instructions is executed before an arithmetic
operation
a) AAM
b) AAD
c) DAS
d) DAA
19. Number of the times the instruction sequence below will loop before coming out of loop
is
MOV AL, 00h
A1: INC AL
JNZ A1
(A) 00
(B) 01
(C) 255
(D) 256
20. What will be the contents of register AL after the following has been executed
MOV BL, 8C
MOV AL, 7E
ADD AL, BL
(A) 0A and carry flag is set
(B) 0A and carry flag is reset
(C) 6A and carry flag is set
(D) 6A and carry flag is reset
Prepared by: Prof. K.L. Chugh, Mr. D. Bheekya, Asst.Prof
HOD, COMPUTER SCIENCE AND ENGINEERING