NUCLEAR DATA, INC.
Post Off:ice Box 451
Palatine,r Illinois 60067
June, 1972
IM4 1-8045 -00
SOFTVVARE INSTRUCTI()N MANUAL
HARDWARE MULTIPLY/DIVIDE TEST
Copyright 1972 by Nuclear Data, Inc.
Prj n ted in U. S •A •
"THIS DCCUMENT IS THE EXCLUSIVE PROPERTY OF NUCLEAR DATA,
INC. AND MAY NOT BE REPRODUCED, NOR MAY THE INFORMATION
CONTAINED THEREIN OR DERIVABLE THEREFROM BE USED IN ANY
MANNER, EXCEPT BY WRITTEN PERMISSION OF NUCLEAR DATA,
INC. THE PROPRIETARY RIGHTS TO THE AFORESAID INFORMATION,
BOTH OF A PATENTABLE AND UNPATENTABLE NATURE, ARE EXPRESSLY
RESERVED TO NUCLEAR DATA, It-JC. II
A
TABLE
IV
1-1
1-1 •
1-3.
1-5.
1-7.
1-1
11-1
1-1
Main Routine • • • •
...
..
.....
r
2-1
2-1
C)PERATIONAL PROCEDURE
3-1
3-1.
3-1
Loading and Initialization Procedure
C)PERATOR OR USER CONTROL
General Information
.' .
....
Error Indi cati ons
COM/v\AND SUMMARY
6-1 •
General
4-1
4-1
ERROR DIAGNOSTICS ••
5-1.
VI
Program Summary •
Program Area • • •
Starti ng Address • • • • • • •
Equipment Configuration.
PROGRAM DESCRIPTION
4-1.
V
PAGE
IINTR<)DUCTION
2-1.
III
CONTENTS
TITLE
SECTION
II
()F
5-1
....
.. ..
5-1
6-1
.......
6-1
.....
7-1
VII
FLOW CHARTS •
VIII
PROGRAM LISTING
8-1
SECTION I
INTRC)DUCTION
1-1 •
PR OG RA,M SUMMARY
1-2.
The Hardware Multiply/Divide Test (ND41-8045) is a diagnostic program designed
to check the ND812 hardware multiply and divide circuitry.
iNOTE
This diagnostic applies to ND812 Central Processors serial number 236
and up or to earlier processor equil::>ped with the 24 X 12 divide modification.
1-3.
PROGRAM AREA
1-4.
This program may reside in any Memory Field octal locations ,.eJ2,.eJ,.eJ through ,.eJ425.
1-5.
STARTI NG ADDRESS
1-6.
The starting address of this program is,.eJ2,.eJ,.eJ8.
1-7.
EQUIPMENT CONFIGURATION
1-8.
Minimum equipment required for plroper operation of this program includes:
a. ND8'I2 Central Processor equipped with the 24 X 12 divide modification
(88-0397)
b. ASR33 Teletype and interface {86-0085 and 88-0481).
1-1
SECT! ON II
PROGRAt\1 DESCRIPTION
2-1.
MAIN R10Un NE
2-2.
The Hardware Multiply/Divide Diognostic performs incrementing multiplication and
division operation using three 12-bit values, A, B, and C for the equation:
(A*B) + C
--C--
= A + C (or as the program defines, A remainder C)
where,
A and B are in itially set to 1.
is initially set to,0 •
c:
. 2-3.
Value A is incremented by one from 1 to 4095. When A reaches the value 4095,
B is incremented to two and A is set to one. A will again be incremented to 4095, B
incremented to three and A set to one. This sequence is followed until value B equals
4095 at which time C is incremented to one and the entire sequence re-initialized. Thus:
A is incremented from one to 4095 for each increment of B
and B is incremented 4095 times for each increment of C.
2-40
Printout provided by thi s program is in two forms. The first states the val ues used
when an erroneous answer was computed.
A X B = Z + C/B
=X
RY
where,
A, B, C, X, and Yare 12-bit numbers
Z is the 24-bit product.
R indicates remainder (X remainder Y)
and
X should = A
Y should = B
2-1
2-5.
The second printout will be automcltically provided each time value C is incremented
(approximately every 15 minutes) and contains the accumulation errors. Printout is in the
following form:
.
010000071 E
Th is feature is of val ue when overn i ght testi ng is desi red.
2-6.
Another feature is included that prevents the program from incrementing any values
when an error condition is encountered. This allows troubleshooting of a particular set of
values if a pattern is detected. Setting the ND812 SWITCH REGISTER Bitf1 to "l" enables
the feature.
2-2
SECTION III
OPERATIONAL PROCEDURE
3-1.
LOADING AND INITlALIZA TI O~~ PROCEDURE
3-2.
The following is a step-by-step procedure describing the program loading sequence:
a. Load the Hardware Multiply/Divide Test (ND41-8045) into any Memory Field
with the Binary L.oader or Hardware Loader. Refer to IM41-0005 for loading procedure.
b. Set the ND812 SWITCH REGI STER to ~2~~8 and depress LOAD AR key.
c. Deprc9ss the ND812 START key.
d. The program will start and continue to operate until the ND812 STOP key is
depressed.
a-l
SECTION IV
OPERATOR C)R USER CONTROL
4-1.
GENERAL INFORMATION
4-2.
In addition to the initiation and te-rmination procedure outlined in Section III, the
value redundancy control is the only operotor control. Value redundancy is accomplished by
setting the ND812 SWITCH REGISTER Bit I~ to "111 and causes the program to continually
execute the diagnostic test using the values used when an error was detected. To recover
from the redundancy operation, set the ND812 SWITCH REGISTER Bit]1 to "]1".
4-1
SECTION V
ERROR DIAGNOSTICS
5-1.
ERROR I ND leA TI ONS
5-2.
Detecti on of em error causes the program to print:
PI X B = Z + C/B == X R Y
where,
PI, B, C, X and Yare 12-bH numbers
Z is the 24-bit product
R indfcates remainder (X remainderY)
and
X should == A
Y should == B
5-3.
An accumulative error message is printed for every incrementati on of value C and is
in the foil owi ng form::
00000071 E
5-1
SECTION VI
COMMAI'1D SUMMARY
6-1.
GENERAL
6-2.
This program does not use keyboard entry command. The only controls are the
ND812 STOP key for termination and SWITCH REGISTER Bit f5 for the value redundancy
operation.
6-1
SECTION VII
FLOW CHARTS
7-1.
GENERAL
7-2.
Attached pages 7-2 and 7-3 is a flow chart of the Hardware Multiply/Divide Test.
7-1
L
ET A = 1
B
C
=1
=0
IA*B
MULTIPLY
'---.-----'
NO
Figure! 7-1.- Hardware Multiply/Divide Flow Chart (Sheet 1 of 2)
7-2
NO
NO
NO
Figure~
7-1 .. Hardware Multiply/Divide Flow Chart (Sheet 2 of 2)
7-3
SECTION VIII
PROGRAM LISTING
8-1.
GENERAL
8-2.
Attached is a copy of the Hardware Multiply/Divide binary listing.
8-1
0<:>
IND41-a045-HARDW4RE MULTIPLY-DIVIDE TEST C24Xl2)
/BIT
~
LOCKS
~221~
151 [1
>5476
0202
1514
020:.5 >5470
lii2cIJ 4 )- 5 4 7 fi
1~1e
020.5
02c~6 >5474
0207
6434
5YSTE~1
START,
02 ~11
LOOP3,
LoaF'2,
LOOP1,
IN SCOPE LoaF AFTER FIRST ERROR
CLR
S1'J
J
MAXREM
CLR INC J
A
STJ
STJ
B
CLR
J
STJ
REM
.JPS
~1DTE ST
0211
0212
5n72
2:a66
LDJ
SMJ
6006
J ~~ f'
0213
~~:;~~4
~?:14
5466
2464
INC
STJ
SMJ
JMP
REM
MAXREM
LIMIT
021C.1
0215
t-J2t6
02:17
02:?-0
0221
[1222
02 ~~3
6vJei2
1 ~!
6,
346r1
6114
02r~4
3456
3456
. 6117
0225
3~52
02~~6
02~27
1530
0230
5451
51151
02 ~~ 1
2301
02~~2
'5450
6410
7055
0233
02~~4
e2~~5
02~~6
02~~7
024e;
0241
0242
02i13
J
I
I
B
LIMIT
LOOP1
I
I
I
ISI
A
I
JMP
LOOP2
I
A
B
I
I
I
ISZ
ISZ
,1 MP
LOQP2
lSZ
SET
STJ
STJ
SUBL
STJ
MAXREM
I
J
I
I
I
I
I
..JPS
XCT
LOJ
XCT
LDJ
XCT
5,151
7e63
5 46
7 f153
030.5
5140
'i
JMF'
0246
(JJ24i
02~i0
~510
SIN
CLR
LDJ
TWLDK
0251
0301
8
024S
A
B
1
REM
MOT EST
X2
CNTR+l
X3
CNTR
Xl
305
0000
1010
1506
1410
51031·
0244
MDTEs'r,
SCOPE lr
I
I
I
I
I
REM
Jr~p
LIMIT,
I
I
I
I
I
I
LOQPJ
I
I
I
I
I
I
I
SET J a ((1
SET MAXIMUM LEGAL REMAINDER. ZERO
SET J • 1
AI: 1
B= 1
SET J II 0
SET REMAINnER • ZERO
EXECUTE TEST SUBROUTINE
CHECK FOR REM AT MAXREM LIMIT
SKIP IF DIFFERENT
REM LIMIT REACHED • GO TO LARGER LOOP
UPDATE REM
SAVE IN REM
CHECK FOR REM AT B LIM!T
REM LIMIT REACHED • GO TO LARGER LOOP
NO LIMIT REACHED - REPEAT SMALLEST LOC
A+1 INTO A, OVE~FLOW?
NO, REPEAT MULTIPLV DIVIOE LOOP
YES, SET A II 1
NO, 8+1 INTO B, OVERFLOW?
NO, CONTINUE INTERMEDIATE LOOP
YES, INCREMENT MAXIMUM LEGAL REMAINDER
SET J II 77.,7
SET A • 7777
SET B • 7777
SET J iii 777e
SET REM II 777e
OUTPUT CR. LF.
SET J • MSB OF COUNTER
OUTPUT VALUE
SET J • TO LSB nF COUNTER
OUTPUT VALUE
OUTPUT E FOR ERRORS
DO OUTER LOOP AGAIN
t
0
LJS~J
GENERAL MULTIPLv/ntVIDE SUBROUTINE
LOAD J FROM SWITCH REGISTER
~ IS BIT 0 ON?
I NO. SET FLAG = ~
I YES, SET J • A
I
J
FLAG
A
I
SET K • B
8-2
0252
100Q1
02B3
50.2 Fi
(1(>54
13Ql~
MPY
LOJ
EXJRKS
B
I
I
I
JV
A.B
II·
SET J
• THEN A.B/B
II
B
e255
055r.
TWSTK
'12~6
0374
I
KV
l!'257
e:261!l
0261
5t24
5TJ
1~5C'1
e?62
0263
1455
CLR
ADJ
51Z
I
I
I
J=LSB l<aMSB RII1 s. ALTEREO VALUE
STORE RESULT OF MULTIPLV AT KV AND
MSB AT KV
LSB AT JV
SET UP TO ADO REM
I
I
I
I
I
DIVIDE K.J/R, QUOTIENT IN J REM. IN
IS FLAG II 0
NO, GO CONTINUE IN SCOPE L.OQF'
STORE QUOTIENT TN AJ
IS REMAINDER CO~RECT?
I
I
/
I
NO, ERROR, REMAINDER SHOULO = REM
YES, ARE A AND OUOTIENT II?
ALL RESULTS O.K. • EXIT
NO, ERROR THEV SHOULD BE II.
I
I
I
I
I
I
I
I
MAXIMUM ALLOWABLE REMAINDE~
MULTIPLICAND
MUL.TIPLIER AND DIVISOR
REMAINDER
PRODUCT OF MULTIPLICATION
LSB
QUOTIENT OF DIVIDE A".B/B
LSB OF COUNTER
MSB OF COUNTER
I
I
I
SKIP IF FLAG NOT SET
NO, GO TO C:OUNT2
OUTPUT CR. LF.
I
OUTPUT A
aCTS
I
OUTPUT B
KV
OCT
I OUTPUT KV
0264
0265
0266
0267
02iV'
44?1
1604
1 f~ Ql1
1 t.10 ~l
6122
5415
Vl2 5 Q1
0302
a
REM
CL~
K
SIZ
FLAG
SCOPE
AJ
Drv
X4,
0
INC
JMP
0272
1442
STJ
TWSMK
REM
SKIP
027~
0274
0275
0276
6014
2404
SNJ
6332
6011
JMP~
t-1DTEST
JMP
ERR
0277
0300
030"
0f'!vH~
MA')(REt'1,
0000
0880
A,
a,
03t?l2
0e,~o.;
REIM,
0~i'1
JMP
e JV,
03m3
(1 (i~ 0
0304
", I2liH1
03 [1!S
r.H~0t9
0306
0r10r~
0307
14~5
A,1 ,
CN'TP. ,
ER'R,
0310
5033
0311 >6474
~312
5112
0313 6440
X2,
Xl,
(1
0
0
0
rd
0
51Z
FL.AG
J t~P
COUN'r2
JPS
LDJ
JPS
CRLF
0330
330
0315
0316
0317
5114
6t135
LDJ
JPS
~275
275
~32~
5054
6444
5117
0323
13324
5430
LDJ
JPS
LDJ
JPS
~253
253
0325
0326
5123
LDJ
JPS
0322
0327
0330
0331
6"25
0257
~127
6422
X3,
A
0
ell
0314
0321
ERR
.
A
aCTS
8
JV
aCTS
I
OUTPUT JV
REM
aCTS
257
LDJ
JPS
B
OCT5
8-3
~332
0333
03~4
(1335
0336
0337
0j4(fi,
rn341
(Jl342
0343
'2I:i 4 4
0345
0346
0347
0:3 5.~1
0351
0352
0;'75
5127
6417
0322
1374
6426
1 &~ t ~~
15V12
142121
3536
1442
3537
1 0 1,J'
1505
275
LDJ
JPS
322
ROTD
JPS
LJSW
SIP
CMP
C:OUNT2, ISZ
SKIP
ISZ
LJSW
SIN
ALOOPP
FLAG
OCTS,
5~141
JPS
LDJ
0362
0363
6431
JPS
lSZ
0364
3510
6311
0365
0000
~366
543:1
0367
64a6
037~
6405
6404
6403
JPS
JPS
5306
JMP~
0371.
0372
e373
JPS
LDJ
JPS
LDJ~
J~1Pd'
OCT,
JPS
0e~(1
KV,
0375
0376
0l?,~0
OUT,
0377
1163
5423
2107
4422
0410
LDJ
ROTD
STJ
ANDL
ADJ
JPS
63(~7
JMP~
04tiH'
!34C'2
04'13
04~' 11
V'lAe,5
tij 4vJ 6
0~H'l0'
5012
CRL.Ff
I
I
I
I
I
INCREMENT COUNTER , OVERFL.Ow?
NO
YES, INCRE~1ENT MSB OF COUNTER
LOAD J FROM SWITCH REGISTE~
IS BIT
ON?
X4
'"
YES, SET FLAG II 1
IJMP SCOPE I L.OCK INTO SCOPE LOOP
I
OCT
K240
TYPE
aCTS
TYPE
I
I
SET J
" 240
PRINT SPACE
TYPE
aCTS
OCTS
I
EXIT
TEMP
OUT
OUT
OUT
OUT
OCT
I
I
I
I
I
I
STORE J IN TEMP
GO TO OUT
I
PRODUCT OF MUl.TIPLICATION
I
I
SET J • TEMP
SHIFT MSB OF DIGIT INTO L.se
I
I
I
I
STRIP OFF BITS 0-8
ADD ASCII
OUTPUT DIGIT
K240
0
STJ
JPS
5~25
OUTPUT REMAINDER
LOAD SWITCH REGISTER
eI
0374
04~1
J
SET
0361.
035fi
0356
0357
CNTR+l
1430
7164
0~6(1
0354
I
I
J
FLAG
CNTR
JMP~
XCT
IOUTPUT AJ
JK 14
OCT'
6255
0000
6411
5045
6435
53(71A
6433
0353
AJ
Del'S
0
0
TEMP
J 3
TEMP
.,
K2eH~
TyPE
OUT
"
II
H
EXIT
EXIT
0
LOJ
K215
8-4
"
.
MSB
(~4f,17
0410
91411
041.2
C'l413
Ql414
6404
5 rlJ 11
TYPE
K212
TYf'E
JPS
64~2
63t~5
PI QH1 ~
JPS
t.OJ
JMP~
TYPE,
415
0416
Cl417
~rMP
6304
Jr'~p,
(~420
~jt!15
K21!5,
0 4 ?1
0~12
K21:?,
TOS
~422
0?4el
~\2t1'~,
00VJQi
TEi1 P ,
24CJ1
0
042t'1
1~2 rH~
K2"1{) ,
26l~
C121~'
I
I
OUTPUT LINE FEED
EXIT
.-1
TYPE
I CLEAR PRINT FLAG,
I IS FLAG :: 1?
I NO, TRV AGAIN
I YES, EXIT
215
212
0423
0425
OUTPUT CARRIAGE RETURN
0
Tep
7413
7414
611.1 1
~,
CRLF
I
ALOnpp, lOOP1+1
IE3645
8-5
LOAD FROM J
SE
1:'; 1 ~~
A
AJ
ALOQPP
B
CNTR
COUNT?
CRLF
ERR
c
03~0
:I
0304
;:
~~4
=
=
=
r1301
=
25
r.33\i'!5
f~343
:I
04~5
03~7
:::
13303
:;
~~ 4? 1
(142v)
\J V
K212
K215
K2 4~1
a
(1422
K250
II
0424
KV
;I
:I
~374
L. I t,1 I T
:;
(122~
LOQP1
LOOP2
=
:I
0207
LOOP;'
::It
~j202
02~5
f~AXREt'1
11/
MOTEST
OCT
III
OUT·
:I
REM
SCOPE
= 021.14
0277
02 4~~
=: "'365
•
•
~1353
. START
:I
...
-
0200
TEMP
TYPE
X1
X2
•
~313
0~11
aCTS
::
I:
)(3
I:
X4
:;
ER 0000
(~37f)
0302
1~423
~1413
13321
0265
8-6