ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-278: Digital Logic Design
Fall 2016
Homework 3
(Due date: October 27th @ 5:30 pm)
Presentation and clarity are very important! Show your procedure!
PROBLEM 1 (25 PTS)
a) Complete the timing diagram of the circuit shown below. (5 pts)
resetn
clock
T
T
Q
resetn
T
Q
clock
Q
b) Complete the timing diagram of the circuit whose VHDL description is shown below: (5 pts)
library ieee;
use ieee.std_logic_1164.all;
elsif (clk’event and clk = ‘0’) then
if x = ‘1’ then
qt <= not(qt);
end if;
end if;
end process;
q <= qt;
end a;
entity circ is
port ( prn, x, clk: in std_logic;
q: out std_logic);
end circ;
architecture a of circ is
clk
signal qt: std_logic;
prn
begin
process (prn, clk, x)
begin
if prn = ‘0’ then
qt <= ‘1’;
x
Q
c) Complete the timing diagram of the circuits shown below: (15 pts)
resetn
D
clk
D
Q
Q
resetn
clk
D
Latch
D
Q
E
Q
Q
QL
QL
resetn
d
clk
clk
D
Q
Q
resetn
d
a
a
Q
1
Instructor: Daniel Llamocca
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-278: Digital Logic Design
Fall 2016
PROBLEM 2 (25 PTS)

Complete the timing diagram of the circuit shown below: (10 pts)
clk
Full Adder
a
b
x
y
cin
s resetn
s
FA
cout cout
D
Q
Q
a
b
clk
Q
cout
resetn
Q
s

Complete the VHDL description of the synchronous sequential circuit whose truth table is shown below: (5 pts)
library ieee;
use ieee.std_logic_1164.all;
clrn clk
entity my_ff is
port ( a, b, c: in std_logic;
clrn, clk: in std_logic;
q: out std_logic);
end my_ff;
A
B
Qt+1
1
0
0
Qt
1
0
1
Qt
1
1
0
C
1
1
1
B
X
X
0
architecture a of my_ff is
begin
-- ???
end a;

0
X
Complete the timing diagram of the circuit shown below. 𝑄 = 𝑄3 𝑄2 𝑄1 𝑄0 (10 pts)
Q3
Q2
Q1
Q0
resetn
x
D
Q
D
Q
D
Q
D
Q
clk
clk
resetn
x
Q
0000
2
Instructor: Daniel Llamocca
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-278: Digital Logic Design
Fall 2016
PROBLEM 3 (20 PTS)

Given the following circuit, complete the timing diagram (signals 𝐷𝑂 and 𝐷𝐴𝑇𝐴).
The LUT 6-to-6 implements the following function: 𝑂𝐿𝑈𝑇 = ⌈𝐼𝐿𝑈𝑇 0.95 ⌉, where 𝐼𝐿𝑈𝑇 is an unsigned number.
For example 𝐼𝐿𝑈𝑇 = 35 (1000112 ) → 𝑂𝐿𝑈𝑇 = ⌈350.95 ⌉ = 30 (0111102 )
D
clk
6
Q
ILUT
DI 6
E
LUT
6-to-6
OLUT
resetn
6 DO
6
DATA
OE
clk
resetn
OE
DATA
010101
111110
101011
010011
DI
DO
PROBLEM 4 (30 PTS)

The following circuit is a 4-bit parallel/serial load shift register with enable input.
Shifting operation: s_l=0. Parallel load: s_l=1. Note that 𝑄 = 𝑄3 𝑄2 𝑄1 𝑄0 . 𝐷 = 𝐷3 𝐷2 𝐷1 𝐷0
 Write a structural VHDL code. You MUST create a file for: i) flip flop, ii) MUX 2-to-1, and iii) top file (where you will
interconnect the flip flops and MUXes). Provide a printout. (10 pts)
 Write a VHDL testbench according to the timing diagram shown below. Complete the timing diagram by simulating your
circuit (Timing Simulation). The clock frequency must be 50 MHz with 50% duty cycle. Provide a printout. (20 pts)
Q0
Q1
Q2
Q3
resetn
D
E
Q
D
E
Q
D
E
Q
D
E
Q
E
clk
0
1
din D0
0
s_l
1
0
D1
1
0
D2
1
D3
clk
resetn
E
s_l
din
D
1011
1010
1100
0111
0101
Q 0000
3
Instructor: Daniel Llamocca