D A T A
S H E E T
Hyper-length FFT-IP Core
Overview
The Fast Fourier Transform IP Core (FFT) from Mistral allows implementation of very long transforms on an FPGA using external RAM. It supports run
time programmable transform lengths from 256 to 1M (powers-of-2) points. The Maximum transform length is limited by the memory available.
Higher transform lengths are supported and depend on factory configuration.
The IP is designed for:
:
Run time Programmability
:
Optimal Resource Utilization
Core Description
Block Diagram
FFT-IP Core uses the Divide-and-Conquer approach for FFT
computation. This approach expresses an FFT of length N
as a product of 2 integers, L x M. The L and M point FFTs
are computed using a pipelined FFT block.
Controller
Arbiter Control
The various blocks of FFT-IP Core are described below:
Controller: This block controls the sequence of
operations to be carried out for transform computation.
Transform computation involves input data load, M point
FFT computation, twiddle generation, L-point FFT
computation and output unload operations.
Pipeline FFT: A Radix-2 pipeline FFT-IP Core from Xilinx is
used for computation of L and M point FFTs. It supports
single precision floating point arithmetic, transform
lengths ranging from 8 to 1024 (power of 2 only) and
generates bit reversed output. It supports fixed point
twiddle factors of width 24 or 25 bits. The FFT-IP Core
internally uses block floating-point representation to
efficiently utilize FPGA resources while providing
performance similar to single-precision representation.
Input
Pipeline
FFT
Complex
Multiplier
Re-order
Re-order
Re-order
Arbiter
Twiddle
Generator
Re-order
External RAM
Twiddle Generator: Supports run time generation of twiddles for different transform sizes avoiding the need for a memory for storage of twiddles.
Complex Multiplier: Multiplies twiddles with data from memory and provides input to pipeline FFT.
Re-order blocks: These blocks re-order the inputs and outputs of the FFT.
Arbiter: It arbitrates memory read and write requests from various blocks.
Output
FFT with 24-bit phase factor and FFT-IP using Xilinx pipeline FFT with 25-bit
Features
phase factor.
Transform size, N = 2m, m = 8 to 20 (default). Can be customized
:
The RMS error for different models and transform sizes is shown below.
Forward or inverse complex transform with run time configurability
:
Note: RMS error is computed using results of one simulation run.
Run time computation of twiddle factors
:
Single precision floating point arithmetic
:
Computation Time
In-order input and output
:
Supports data rate of 200MS/s* (complex data)
:
FFT Size
* (The throughput of the core depends on the external RAM
and the device targeted)
Load cycles
Computation
cycles
Unload
cycles
Total
cycles
256
256
806
256
1318
512
512
1383
512
2407
1024
1024
2472
1024
4520
2048
2048
4584
2048
8680
4096
4096
8744
4096
16936
8192
8192
17079
8192
33463
16384
16384
33606
16384
66374
32768
32768
66630
32768
132166
time as input for RMS error computation. Double precision floating point
65536
65536
132422
65536
263494
MATLAB FFT is used as reference to compute RMS error. The models shown
131072
131072
264712
131072
526856
262144
262144
527638
262144
1051926
Applications
Radar signal processing (Pulse Compression,
:
Doppler processing etc)
Spectral analysis
:
RMS Error Computation
The Hyper-length FFT-IP Core from Mistral uses an impulse, randomized in
are, Single precision floating point MATLAB FFT, FFT-IP using Xilinx pipeline
-125
256
512
1024
2048
4096
8192
16384
32768
65536 131072
RMS Error in dB
-130
-135
-140
-145
-150
-155
Transform Size
FFT with 24 bit twiddles
FFT with 25 bit twiddles
Single precision MATLAB FFT
Resource Utilization
Deliverables
The post map resource utilization information is given below:
Part Number: IP_F_FFT_N_V1.0
•
Data sheet and User Manual
:
Synthesized netlist, fft.ngc
:
ModelSim simulation set up with VHDL test bench
:
Scilab scripts for test input generation and output validation
:
Bit-accurate C model *
:
With pipeline FFT using 24-bit twiddles
Device
Registers
LUTs
BRAMs
DSPs
Virtex-6
XC6VSX475T
11770/595200
= 1%
8605/297600
= 2%
16/1064
=1%
60/2016
= 2%
Part Number: IP_F_FFT_V_V1.0
With pipeline FFT using 25-bit twiddles
Device
Registers
LUTs
BRAMs
DSPs
Virtex-6
XC6VSX475T
13432/595200
= 2%
9774/297600
= 3%
16/1064
=1%
73/2016
= 3%
Note: Resource utilization is for guidance only and can change with
improvements to the design.
Data sheet and User Manual
:
VHDL source files
:
ModelSim simulation set up with VHDL test bench
:
Scilab scripts for test input generation and output validation
:
Bit-accurate C model *.
:
* Currently unavailable. Will be released later.
About Mistral
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company providing end-to-end solutions for product design
and application deployment. Mistral is focused in two
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and Homeland Security. Mistral provides total solutions for a
given requirement, which may include hardware board design,
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•