Product Specification
PE43703
50 Ω RF Digital Attenuator
7-bit, 31.75 dB, 9 kHz - 6000 MHz
VssEXT option
Product Description
The PE43703 is a HaRP™-enhanced, high linearity, 7-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB, or 1.0
dB steps. The customer can choose which step size and
associated specifications are best suited for their application.
The Peregrine 50Ω RF DSA provides multiple CMOS control
interfaces and an optional external Vss feature. It maintains
high attenuation accuracy over frequency and temperature and
exhibits very low insertion loss and low power consumption.
Performance does not change with VDD due to on-board
regulator. This next generation Peregrine DSA is available in a
5x5 mm 32-lead QFN footprint.
Features
 HaRP™-enhanced UltraCMOS™ device
 Attenuation options: 0.25 dB, 0.5 dB, or
The PE43703 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
L
P E
 3.3 V or 5.0 V Power Supply Voltage
 Fast switch settling time
 Programming Modes:
Direct Parallel
Latched Parallel
 Serial-Addressable: Program up to
eight addresses 000 - 111
 High-attenuation state @ power-up (PUP)
E4


BS
H
O
IT
Figure 1. Package Type
32-lead 5x5x0.85 mm QFN Package
13
T
37 E
1.0 dB steps to 31.75 dB
 0.25 dB monotonicity for ≤4.0 GHz
 0.5 dB monotonicity for ≤5.0 GHz
 1 dB monotonicity for ≤6.0 GHz
 High Linearity: Typical +59 dBm IIP3
 Excellent low-frequency performance
 Optional External Vss Control (VssEXT)
 CMOS Compatible
 No DC blocking capacitors required
W
Figure 2. Functional Schematic Diagram
O
AC
E
Switched Attenuator Array
RF Input
Parallel Control
7
EP
L
Serial In
RF Output
Control Logic Interface
CLK
R
LE
A0
A1
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A2
P/S
(optional)
VssEXT
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Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 1 of 15
PE43703
Product Specification
Table 1. Electrical Specifications: 0.25 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND
Parameter
Test Conditions
Frequency
Min
Frequency Range
0 – 31.75
9 kHz ≤ 4 GHz
0 dB - 7.75 dB Attenuation settings
8 dB - 31.75 dB Attenuation settings
0 dB - 31.75 dB Attenuation settings
1.9
9 kHz < 3 GHz
9 kHz < 3 GHz
3 GHz < 4 GHz
9 kHz - 4 GHz
Return Loss
All States
9 kHz - 4 GHz
Input
20 MHz - 4 GHz
IIP3
Two tones at +18 dBm, 20 MHz spacing
20 MHz - 4 GHz
Typical Spurious Value2
VssEXT grounded
1 MHz
Video Feed Through
10% / 90% RF
Settling Time
RF settled to within 0.05 dB of final value.
RBW = 5 MHz, Averaging ON.
900 MHz
1800 MHz
35
8
12
16
20
Attenuation Setting (dB)
24
28
1dB State
16dB State
ns
R
0
1000
2000
µs
15
10
5
5
10
15
20
25
Ideal Attenuation (dB)
30
35
Figure 6. 0.25 dB Attenuation Error
1.5
200 MHz
900 MHz
1800 MHz
2200 MHz
3000 MHz
4000 MHz
1.0
0.5
0.0
-0.5
-1.0
3000
Frequency (MHz)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
25
Attenuation State
2dB State
31.75dB State
EP
L
Attenuation Error (dB)
0.5
-1.5
ns
400
20
0
Attenuation Error (dB)
0.5dB State
8dB State
1.0
-1.0
650
H
Attenuation
Actual
Attenuation dB
(dB)
25
32
AC
E
O
0.25dB State
4dB State
-0.5
mVpp
0
W
4
Figure 5. 0.25 dB Major State Bit Error
0.0
10
900 MHz
1800 MHz
2200 MHz
3000 MHz
*Monotonicity is held so long as Step-Attenuation does not cross below -0.25
1.5
dBm
dBm
0.25-dB PE43701 Attenuation
3000 MHz
O
IT
2200 MHz
BS
Step Attenuation (dB)
0
59
4
30
0.25
dBm
E4
200 MHz
deg
32
Figure 4. 0.25 dB Step, Actual vs. Ideal Attenuation
Figure 3. 0.25 dB Step Attenuation*
0.50
33
-110
1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 5.
2. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT.
Performance Plots, 0.25 dB step
-0.25
30
L
P E
50% DC CTRL to 10% / 90% RF
dB
dB
dB
dB
T
37 E
Relative Phase
Switching Time
dB
18
P1dB (note 1)
RF Trise/Tfall
dB
2.4
±(0.2+1.5%)
±(0.15+4%)
±(0.25+4.5%)
13
Attenuation Error
Units
4000 MHz
0.25 dB Step
Insertion Loss
0.00
Max
9 kHz
Attenuation Range
Notes:
Typical
4000
-1.5
0.0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
Attenuation Setting (dB)
Document No. 70-0245-05
│ UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43703
Product Specification
Table 2. Electrical Specifications: 0.5 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND
Parameter
Test Conditions
Frequency
Frequency Range
Attenuation Range
9 kHz - 5 GHz
Input
20 MHz - 5 GHz
IIP3
Two tones at +18 dBm, 20 MHz spacing
20 MHz - 5 GHz
Typical Spurious Value2
VssEXT grounded
1 MHz
Video Feed Through
3000 MHz
4000 MHz
5000 MHz
35
0
4
8
12
16
20
Attenuation Setting (dB)
24
28
32
AC
E
O
25
2dB State
16dB State
31.5dB State
1.5
1.0
0.0
-0.5
-1.0
R
-1.5
0
1000
2000
µs
15
10
5
0
0
5
10
15
20
25
Ideal Attenuation (dB)
30
35
Attenuation State
4dB State
200 MHz
3000 MHz
1.5
900 MHz
4000 MHz
1800 MHz
5000 MHz
2200 MHz
1.0
EP
L
0.5
ns
25
20
Attenuation Error (dB)
1dB State
ns
Figure 10. 0.5 dB Attenuation Error
Figure 9. 0.5 dB Major State Bit Error
8dB State
mVpp
900 MHz
2200 MHz
3800 MHz
5000 MHz
*Monotonicity is held so long as Step-Attenuation does not cross below -0.5
0.5dB State
10
650
H
Attenuation
Actual
Attenuation dB
(dB)
W
-0.500
BS
Step Attenuation (dB)
0.000
dBm
0.5-dB PE43703 Attenuation
2200 MHz
30
0.500
dBm
E4
1800 MHz
57
-110
4
O
IT
900 MHz
dBm
Figure 8. 0.5 dB Step, Actual vs. Ideal Attenuation
Figure 7. 0.5 dB Step Attenuation*
200 MHz
deg
32
400
1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 5.
2. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT.
Performance Plots, 0.5 dB step
dB
dB
dB
dB
13
10% / 90% RF
RF settled to within 0.05 dB of final value.
RBW = 5 MHz, Averaging ON.
±(0.25+4.5%)
±(0.3+5%)
±(1.3+0%)
56
30
L
P E
RF Trise/Tfall
dB
T
37 E
All States
P1dB (note 1)
50% DC CTRL to 10% / 90% RF
2.6
18
Relative Phase
Switching Time
dB
2.0
9 kHz < 4 GHz
4 ≤5 GHz
4 ≤5 GHz
9 kHz - 5 GHz
Return Loss
1.000
Units
0 – 31.5
0 dB - 31.5 dB Attenuation settings
0 dB - 16.5 dB Attenuation settings
17 dB - 31.5 dB Attenuation settings
Settling Time
Max
5000 MHz
9 kHz ≤5 GHz
Attenuation Error
Attenuation Error (dB)
Typical
0.5 dB Step
Insertion Loss
Notes:
Min
9 kHz
0.5
0.0
-0.5
-1.0
3000
Frequency (MHz)
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4000
5000
-1.5
0.0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
Attenuation Setting (dB)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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Page 3 of 15
PE43703
Product Specification
Table 3. Electrical Specifications: 1 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND
Parameter
Test Conditions
Frequency range
Attenuation Range
Frequency
0 - 31
0 dB - 31 dB Attenuation settings
0 dB - 12 dB Attenuation settings
13 dB - 31 dB Attenuation setting
0 dB - 31 dB Attenuation settings
9 kHz – 4 GHz
4 GHz ≤6 GHz
4 GHz ≤6 GHz
4 GHz ≤6 GHz
All States
9 kHz - 6 GHz
9 kHz - 6 GHz
Input
20 MHz - 6 GHz
Two tones at +18 dBm, 20 MHz spacing
20 MHz - 6 GHz
Typical Spurious Value2
VssEXT grounded
1 MHz
Video Feed Through
50% DC CTRL to 10% / 90% RF
RF Trise/Tfall
10% / 90% RF
Settling Time
RF settled to within 0.05 dB of final value.
RBW = 5 MHz, Averaging ON.
900 MHz
4000 MHz
1800 MHz
5000 MHz
O
IT
8
12
16
20
24
Attenuation Setting (dB)
28
-0.5
R
-1.0
1000
ns
25
µs
0
0
5
10
15
20
25
Ideal Attenuation (dB)
30
35
Attenuation State
200 MHz
900 MHz
1800 MHz
2200 MHz
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
2000
3000
4000
5000
Frequency (MHz)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
ns
400
5
4dB State
31dB State
-1.5
0
650
10
Attenuation Error (dB)
0.0
mVpp
H
Attenuation
Actual
AttenuationdB
(dB)
AC
E
O
0.5
dBm
10
Figure 14. 1 dB Attenuation Error
EP
L
Bit Error (dB)
1.0
2dB State
16dB State
-110
15
32
Figure 13. 1 dB Major State Bit Error
1dB State
8dB State
dBm
dBm
20
*Monotonicity is held so long as Step-Attenuation not cross below -1
1.5
32
53
900 MHz
2200 MHz
3800 MHz
5800 MHz
25
W
4
dB
deg
1-dB PE43703 Attenuation
BS
Step Attenuation (dB)
0
dB
dB
dB
dB
Figure 12. 1 dB Step, Actual vs. Ideal Attenuation
2200 MHz
6000 MHz
30
-1
±(0.25+4.5%)
+0.4+8%
+1.4+0%
-0.2-3%
4
35
0.5
dB
E4
Figure 11. 1 dB Step Attenuation
-0.5
30
1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 5.
2. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT.
Performance Plots, 1 dB step
2.8
18
74
L
P E
Switching Time
dB
2.3
13
P1dB (note 1)
IIP3
200 MHz
3000 MHz
Units
T
37 E
Return Loss
Relative Phase
1
Max
6000 MHz
9 kHz ≤6 GHz
Attenuation Error
0
Typical
1 dB Step
Insertion Loss
Notes:
Min
9 kHz
6000
0
4
8
12
16
20
24
28
32
Attenuation Setting (dB)
Document No. 70-0245-05
│ UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43703
Product Specification
Performance Plots, 1 dB step (continued)
Figure 15. 1 dB Attenuation Error (continued)
3000 MHz
4000 MHz
5000 MHz
Figure 16. Insertion Loss @ Temperature
6000 MHz
1.5
+25C
+85C
-0.5
1.0
-1
Insertion Loss (dB)
0.5
0.0
-1.5
-2
-2.5
-3
T
37 E
Attenuation Error (dB)
-40C
0
-0.5
-3.5
-4
-1.0
-4.5
-5
-1.5
8
12
16
20
24
28
32
0.0
Attenuation Setting (dB)
0.5dB
1dB
8dB
16dB
31.75dB
-10
0dB
4dB
-10
-70
0
1
2
3
4
5
6
7
8
-30
0.25dB
8dB
0
W
85C
-20
-25
-30
-35
-40
1
2
R
0
3
4
5
Frequency (GHz)
Document No. 70-0245-05 │ www.psemi.com
0.5dB
16dB
1dB
31.75dB
2dB
1
2
3
4
5
6
Frequency (GHz)
7
8
9
Figure 20. Output Return Loss @ Temperature
for 16 dB State
-40C
25C
85C
-5
-10
Return Loss (dB)
-15
9.0
0
O
-10
EP
L
Return Loss (dB)
-5
8.0
-60
9
AC
E
25C
7.0
-50
Figure 19. Input Return Loss @ Temperature for
16 dB State
-40C
6.0
-40
Frequency (GHz)
0
5.0
H
-60
-20
O
IT
Return Loss (dB)
-20
BS
Return Loss (dB)
2dB
0
-50
4.0
L
P E
0.25dB
4dB
-40
3.0
Figure 18. Output Return Loss (+25C)
0dB
-30
2.0
Frequency (GHz)
Figure 17. Input Return Loss (+25C)
0
1.0
13
4
E4
0
-15
-20
-25
-30
-35
-40
-45
-50
6
7
8
9
0
1
2
3
4
5
6
7
8
Frequency (GHz)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 5 of 15
9
PE43703
Product Specification
Performance Plots (continued)
Figure 21. Relative Phase Error
0.25dB
0.5dB
1dB
4dB
8dB
16dB
31.75dB
Figure 22. Relative Phase Error vs.
Temperature for 31.75 dB State
2dB
3000 MHz
25.00
60
40
20.00
15.00
T
37 E
Phase (Deg)
80
10.00
20
5.00
0
0.00
1
2
3
4
5
Frequency (GHz)
6
7
8
-40
20
40
60
80
+85C
Figure 24. Attenuation Error @ 1800 MHz
L
P E
-40C
0
Temperature (Deg C)
Figure 23. Attenuation Error @ 900 MHz
+25 C
-20
13
0
+25C
-40C
+85C
1.5
1.5
1.0
Attenuation Error (dB)
1.0
0.5
0.0
-0.5
-1.5
4.0
8.0
12.0
16.0
20.0
Attenuation Setting (dB)
24.0
28.0
32.0
W
0.0
BS
-1.0
Figure 25. Attenuation Error @ 3000 MHz
-40C
0.5
-0.5
-1.0
-1.5
4
R
0
EP
L
0.0
8
12
16
-1.5
0
4
8
12
16
20
24
28
32
Attenuation Setting (dB)
0dB
0.25dB
0.5dB
1dB
4dB
8dB
16dB
31.75dB
2dB
65
60
55
50
45
40
35
20
24
28
Attenuation Setting (dB)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 15
-1.0
Figure 26. Input IP3 vs. Frequency
Input IP3 (dBm)
1.0
-0.5
70
O
1.5
0.0
+85C
AC
E
+25C
0.5
H
O
IT
Attenuation Error (dB)
1800 MHz
30.00
100
Attenuation Error (dB)
900 MHz
35.00
E4
Relative Phase Error (Deg)
120
0dB
32
30
0
1000
2000
3000
4000
5000
6000
7000
Frequency (MHz)
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│ UltraCMOS™ RFIC Solutions
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PE43703
Product Specification
C0.25
C0.5
C1
C2
C4
C8
C16
SI
Figure 27. Pin Configuration (Top View)
32
31
30
29
28
27
26
25
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESDsensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
1
24
CLK
VDD
2
23
LE
P/S
3
22
A1
Latch-Up Avoidance
A0
4
21
A2
GND
5
20
VssEXT
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
GND
6
19
GND
RF1
7
18
RF2
GND
8
17
GND
13
14
15
16
GND
GND
GND
GND
GND
Table 4. Pin Descriptions
Pin No.
Pin Name
1
N/C
No Connect
2
VDD
Power supply pin
3
Pิ /S
Serial/Parallel mode select
4
A0
Address Bit A0 connection
5
GND
6
GND
Ground
7
RF1
RF1 port
20
22
23
RF2 port
GND
Ground
External Vss Control
A2
Address Bit A2 connection
A1
Address Bit A1 connection
LE
Serial interface Latch Enable input
CLK
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Serial interface Clock input
SI
26
C16 (D6)
27
C8 (D5)
28
C4 (D4)
29
C2 (D3)
C1 (D2)
Parallel control bit, 1 dB
O
25
AC
E
24
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43703 in
the 5x5 QFN package is MSL1.
H
Ground
RF2
VssEXT
21
O
IT
19
GND
The PE43703 has a maximum 25 kHz switching rate
when VssEXT is grounded. Switching rate is defined to
be the speed at which the DSA can be toggled across
attenuation states.
W
18
Ground
Switching Frequency
BS
8 - 17
Description
13
12
For proper operation, the VssEXT control must be
grounded or at the Vss voltage specified in the
Operating Ranges table. When the VssEXT control pin
on the package is grounded the switch FET’s are
biased with an internal low spur negative voltage
generator. For applications that require the lowest
possible spur performance, VssEXT can be applied to
bypass the internal negative voltage generator to
eliminate the spurs.
E4
11
Optional External Vss Control (VssEXT)
L
P E
10
GND
GND
9
GND
Exposed
Solder pad
T
37 E
NC
31
32
Parallel control bit, 16 dB
Parallel control bit, 8 dB
Parallel control bit, 4 dB
Parallel control bit, 2 dB
EP
L
30
Serial interface Data input
Paddle
C0.5 (D1)
Parallel control bit, 0.5 dB
C0.25 (D0)
Parallel control bit, 0.25 dB
GND
Ground for proper operation
R
Note: Ground C0.25, C0.5, C1 C2, C4, C8, C16 if not in use.
Document No. 70-0245-05 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 7 of 15
PE43703
Product Specification
Table 5. Operating Ranges
VssEXT Negative Power Supply
Voltage1
Typ
Max
Units
Symbol
3.0
3.3
3.6
V
VDD
-4.0
0.3
V
-0.3
5.8
V
See fig. 28
+23
dBm
dBm
-2.4
V
VI
Voltage on any Digital input
70
350
μA
PIN
5.5
V
Input power (50Ω)
9 kHz ≤20 MHz
20 MHz ≤6 GHz
See fig. 28
+23
dBm
dBm
-40
25
0
85
°C
1
V
15
μA
TST
Storage temperature range
VESD
ESD voltage (HBM)1
ESD voltage (Machine Model)
-65
150
°C
500
100
V
V
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
E4
L
P E
H
O
IT
W
BS
25.0
Pin dBm
V
-2.7
30.0
0.0
6.0
-3.0
Figure 28. Maximum Power Handling Capability: Z0 = 50 Ω
5.0
-0.3
Vss External Negative Power
Supply Voltage (optional)
VssEXT
Note: 1. Applied only when external VSS power supply used. Pin 20
must be grounded when using internal Vss supply
10.0
Power supply voltage
V
Digital Input Leakage
15.0
Units
5.5
PIN Input power (50Ω):
9 kHz ≤20 MHz
20 MHz ≤6 GHz
20.0
Max
5.0
2.6
TOP Operating temperature
range
Digital Input Low
Min
4.5
IDD Power Supply Current
Digital Input High
Parameter/Conditions
13
VDD 3.3 V Power Supply
Voltage
VDD 5.0 V Power Supply
Voltage
Min
T
37 E
Parameter
Table 6. Absolute Maximum Ratings
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
1.0E+09
Hz
R
EP
L
O
AC
E
1.0E+03
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 15
Document No. 70-0245-05
│ UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43703
Product Specification
Table 7. Control Voltage
State
Table 10. Serial Address Word Truth Table
Bias Condition
Address Word
Low
0 to +1.0 Vdc at 2 µA (typ)
A7
(MSB)
High
+2.6 to +5 Vdc at 10 µA (typ)
X
X
X
X
X
L
X
X
X
X
X
L
Table 8. Latch and Clock Specifications
A0
Address
Setting
L
L
000
L
H
001
A6
A5
A4
A3
A2
A1
X
X
X
X
X
L
H
L
010
X
X
X
X
X
L
H
H
011
L
L
100
101
Shift Clock
Function
X
X
X
X
X
H
0
↑
Shift Register Clocked
X
X
X
X
X
H
L
H
X
X
X
X
X
H
H
L
110
X
X
X
X
X
H
H
H
111
Contents of shift register
transferred to attenuator core
Table 9. Parallel Truth Table
Table 11. Serial Attenuation Word Truth Table
D6
D5
D4
D3
D2
D1
D0
Attenuation
Setting
RF1-RF2
L
L
L
L
L
L
L
Reference I.L.
L
L
L
L
L
L
H
0.25 dB
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
Attenuation Word
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
Reference I.L.
L
L
L
H
0.25 dB
L
L
H
L
0.5 dB
L
1 dB
D4
L
L
L
L
L
L
L
L
L
L
L
L
L
1 dB
L
L
2 dB
L
L
P E
L
D0
(LSB)
D5
D3
L
L
L
H
L
L
L
2 dB
4 dB
L
L
L
H
L
L
L
L
4 dB
8 dB
L
L
H
L
L
L
L
L
8 dB
16 dB
L
H
L
L
L
L
L
L
16 dB
H
H
D1
D6
H
H
H
H
H
H
31.75 dB
0.5 dB
O
IT
L
D2
Attenuation
Setting
RF1-RF2
D7
L
31.75 dB
BS
L
13
Parallel Control Setting
E4
X
↑
T
37 E
Latch Enable
H
L
L
L
H
L
W
Table 12. Serial-Addressable Register Map
Bits can either be set to logic high or logic low
Q15
Q14
Q13
A7
A6
A5
LSB (first in)
D7 must be set to logic low
AC
E
O
MSB (last in)
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Attenuation Word
EP
L
Address Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state
at address 3:
R
Address word: XXXXX011
Attenuation Word: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → 01001001
Serial Input: XXXXX01101001001
Document No. 70-0245-05 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 9 of 15
PE43703
Product Specification
Programming Options
shift register. Serial data is clocked in LSB first,
beginning with the Attenuation Word.
Parallel/Serial Selection
Either a parallel or serial-addressable interface can
be used to control the PE43703. The Pิ /S bit
provides this selection, with Pิ /S=LOW selecting the
parallel interface and Pิ /S=HIGH selecting the serialaddressable interface.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data into the DSA. Address Word and
Attenuation Word truth tables are listed in Table 10
& Table 11, respectively. A programming example of
the serial-addressable register is illustrated in Table
12. The serial-addressable timing diagram is
illustrated in Fig. 29.
T
37 E
Parallel Mode Interface
The parallel interface consists of seven CMOScompatible control lines that select the desired
attenuation state, as shown in Table 9.
The parallel interface timing requirements are
defined by Fig. 30 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
Power-up Control Settings
EP
L
O
AC
E
W
Serial-Addressable Interface
The serial-addressable interface is a 16-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The 16-bits make up two words comprised of
8-bits each. The first word is the Attenuation Word,
which controls the state of the DSA. The second
word is the Address Word, which is compared to the
static (or programmed) logical states of the A0, A1
and A2 digital inputs. If there is an address match,
the DSA changes state; otherwise its current state
will remain unchanged. Fig. 29 illustrates an
example timing diagram for programming a state. It
is required that all parallel control inputs be
grounded when the DSA is used in serialaddressable mode.
H
BS
O
IT
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
R
The serial-addressable interface is controlled using
three CMOS-compatible signals: Serial-In (SI),
Clock (CLK), and Latch Enable (LE). The SI and
CLK inputs allow data to be serially entered into the
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 15
13
For latched-parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Fig. 30) to latch new attenuation state into
device.
E4
L
P E
The PE43703 will always initialize to the maximum
attenuation setting (31.75 dB) on power-up for both
the serial-addressable and latched-parallel modes of
operation and will remain in this setting until the user
latches in the next programming word. In directparallel mode, the DSA can be preset to any state
within the 31.75 dB range by pre-setting the parallel
control pins prior to power-up. In this mode, there is
a 400-µs delay between the time the DSA is
powered-up to the time the desired state is
set. During this power-up delay, the device
attenuates to the maximum attenuation setting
(31.75 dB) before defaulting to the user defined
state. If the control pins are left floating in this mode
during power-up, the device will default to the
minimum attenuation setting (insertion loss state).
Dynamic operation between serial-addressable and
parallel programming modes is possible.
If the DSA powers up in serial-addressable mode (P/
S = HIGH), all the parallel control inputs DI[6:0] must
be set to logic low. Prior to toggling to parallel mode,
the DSA must be programmed serially to ensure
D[7] is set to logic low.
If the DSA powers up in either latched or directparallel mode, all parallel pins DI[6:0] must be set to
logic low prior to toggling to serial-addressable mode
(Pิ /S = HIGH), and held low until the DSA has been
programmed serially to ensure bit D[7] is set to logic
low.
The sequencing is only required once on powerup. Once completed, the DSA may be toggled
between serial-addressable and parallel
programming modes at will.
Document No. 70-0245-05
│ UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43703
Product Specification
Figure 29. Serial-Addressable Timing Diagram
Bits can either be set to logic high or logic low
D[7] must be set to logic low
DI[6:0]
TDISU
ADD[2:0]
TDIH
VALID
TASU
TAIH
P/S
TPSSU
TPSIH
D[0]
SI
TSISU
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
A[0]
A[1]
A[2]
TSIH
CLK
TCLKH
TLESU
T
37 E
TCLKL
LE
DO[6:0]
TLEPW
TPD
VALID
VALID
TDISU
TDIH
LE
TLEPW
DO[6:0]
O
IT
VALID
TPD
TDIPD
BS
Table 13. Serial-Addressable Interface
AC Characteristics
H
DI[6:0]
TPSH
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Serial clock frequency
-
Serial clock HIGH time
30
Serial clock LOW time
30
O
TCLKL
Min
Max
Unit
10
MHz
-
ns
-
ns
W
FCLK
TCLKH
Parameter
AC
E
Symbol
Last serial clock rising edge
setup time to Latch Enable
rising edge
10
TLEPW
Latch Enable min. pulse width
30
-
ns
TSISU
Serial data setup time
10
-
ns
TSIH
Serial data hold time
10
-
ns
TDISU
Parallel data setup time
100
-
ns
Parallel data hold time
100
-
ns
TDIH
TASU
TAH
EP
L
TLESU
-
ns
Address setup time
100
-
ns
Address hold time
100
-
ns
Parallel/Serial setup time
100
-
ns
TPSH
Parallel/Serial hold time
100
-
ns
-
10
ns
R
TPSSU
TPD
E4
TPSSU
L
P E
P/S
Digital register delay (internal)
Document No. 70-0245-05 │ www.psemi.com
13
Figure 30. Latched-Parallel/Direct-Parallel Timing Diagram
Table 14. Parallel and Direct Interface
AC Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
TLEPW
Latch Enable minimum
pulse width
30
-
ns
TDISU
Parallel data setup time
100
-
ns
TDIH
Parallel data hold time
100
-
ns
TPSSU
Parallel/Serial setup time
100
-
ns
TPSIH
Parallel/Serial hold time
100
-
ns
Digital register delay
(internal)
-
10
ns
Digital register delay
(internal, direct mode only)
-
5
ns
TPD
TDIPD
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 11 of 15
PE43703
Product Specification
Figure 31. Evaluation Board Layout
Evaluation Kit
Peregrine Specification 101-0312
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE43703 Digital Step Attenuator.
L
P E
Note: Reference Fig. 32 for Evaluation Board Schematic
H
W
BS
AC
E
O
E4
Serial-Addressable Programming Procedure
Position the Parallel/Serial (Pิ /S) select switch to
the Serial (or right) position. Prior to
programming, the user must define an address
setting using the ADD header pin. Jump the
middle pins on the ADD header A0-A2 (or lower)
row of pins to set logic high, or jump the middle
pins to the upper row of pins to set logic low. If
the ADD pins are left open, then 000 become the
default address. The evaluation software is
written to operate the DSA in either Parallel or
Serial-Addressable Mode. Ensure that the
software is set to program in Serial-Addressable
mode. Using the software, enable or disable each
setting to the desired attenuation state. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
O
IT
For manual direct-parallel programming,
disconnect the test harness provided with the EVK
from the J1 and Serial header pins. Position the
Parallel/Serial (Pิ /S) select switch to the Parallel (or
left) position. The LE pin on the Serial header must
be tied to VDD. Switches D0-D6 are SP3T switches
which enable the user to manually program the
parallel bits. When any input D0-D6 is toggled
‘UP’, logic high is presented to the parallel input.
When toggled ‘DOWN’, logic low is presented to
the parallel input. Setting D0-D6 to the ‘MIDDLE’
toggle position presents an OPEN, which forces an
on-chip logic low. Table 9 depicts the parallel
programming truth table and Fig. 30 illustrates the
parallel programming timing diagram.
13
T
37 E
Direct-Parallel Programming Procedure
For automated direct-parallel programming,
connect the test harness provided with the EVK
from the parallel port of the PC to the J1 & Serial
header pin and set the D0-D6 SP3T switches to the
‘MIDDLE’ toggle position. Position the Parallel/
Serial (Pิ /S) select switch to the Parallel (or left)
position. The evaluation software is written to
operate the DSA in either Parallel or SerialAddressable Mode. Ensure that the software is set
to program in Direct-Parallel mode. Using the
software, enable or disable each setting to the
desired attenuation state. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
EP
L
Latched-Parallel Programming Procedure
For automated latched-parallel programming, the
procedure is identical to the direct-parallel method.
The user only must ensure that Latched-Parallel is
selected in the software.
R
For manual latched-parallel programming, the
procedure is identical to direct-parallel except now
the LE pin on the Serial header must be logic low
as the parallel bits are applied. The user must then
pulse LE from 0V to VDD and back to 0V to latch the
programming word into the DSA. LE must be logic
low prior to programming the next word.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 15
Document No. 70-0245-05
│ UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43703
Product Specification
Figure 32. Evaluation Board Schematic
13
E4
L
P E
T
37 E
Peregrine Specification 102-0381
EP
L
O
AC
E
W
BS
Figure 33. Package Drawing
H
O
IT
Note: Capacitors C1-C8, C13, & C14 may be omitted.
QFN 5x5 mm
R
A
MAX
0.900
NOM
0.850
MIN
0.800
Document No. 70-0245-05 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 13 of 15
PE43703
Product Specification
13
L
P E
T
37 E
Figure 34. Tape and Reel Drawing
E4
H
BS
O
IT
Tape Feed Direction
Pin 1
Top of
Device
Device Orientation in Tape
W
Figure 35. Marking Specifications
O
AC
E
43703
YYWW
ZZZZZ
EP
L
YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Table 15. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
43703
PE43703 G - 32QFN 5x5mm-75A
Green 32-lead 5x5mm QFN
Bulk or tape cut from reel
PE43703MLI-Z
43703
PE43703 G – 32QFN 5x5mm-3000C
Green 32-lead 5x5mm QFN
3000 units / T&R
EK43703-01
43703
PE43703 G – 32QFN 5x5mm-EK
Evaluation Kit
1 / Box
R
PE43703MLI
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 14 of 15
Document No. 70-0245-05
│ UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE43703
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Fax: +82-31-728-3940
T
37 E
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
Peregrine Semiconductor K.K., Japan
13
E4
Europe/Asia-Pacific
Aix-En-Provence Cedex 3, France
Phone: +33-4-4239-3361
Fax: +33-4-4239-7227
O
IT
Americas
San Diego, CA, USA
Phone: 858-731-9475
Fax: 848-731-9499
L
P E
High-Reliability and Defense Products
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Data Sheet Identification
W
Advance Information
H
BS
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
O
AC
E
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
EP
L
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
R
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a CNF
(Customer Notification Form).
Document No. 70-0245-05 │ www.psemi.com
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 15 of 15