107
Closure
of lnterconnections
Properties
of
Determinate
Sys€ens
Suhas S. Patil
Pto j ect MAC, M. I. T., Cambridge,
A system is
characterized
onl-y way a system interacts
it
and the outPut
consists
of
it
state
Turing
machines,
but
The input/output
for
two inputs
hthy deterininate
ful,
Just
as in
the circuit
hazard
free,
in
refers
circuit
a function
is
will-
constfucting
exhibits,
as the
is presented
that
An important
theory
is not
it
class
of
The one-input
to
systems
one-outplrt
are such systems and so are
hazard free
be referred
is
not.
A system
to as a determirtate
a determinate
system.
system has the important
-
the same,outputs
Tnie non-determinate
propa reason
systems are also
use-
Eo deal with.
sequential
by inEerconnecting
a Large determinate
the interconnected
to the property
i.n a deEerminate
the input
the s4me, the qystem gives
a larg€
consttucted
constructing
that
a function.
circuit
which
a function,
which are
through
the input.
systems have wide applications.
one desires
property
sults
is
being
but ere much more difficult
desire
tems'
relation
relation
to
relation
in sequential-
a sequential
tetrationship
systems is
in response
machines studied
whose input/output
that
r'rith other
produces
those whose input/output
finite
erty
by the input/output
rra*ssachuse t ts
systeft
circuit
from smaller
smaller
hazard
sysiem out of
free
one would
circuits
to be
smatrler determinate
to be determinate.
whereby any interconneceion
circuits,
In
this
sys-
paper the closure
of determinate
systems re-
system.
Sys tems
A system has a nr:rnber of
inlets
and outlets
(Figure
l)
which are
Ehe points
through
inlet
2-+
i
I
inlets
ovLLetj
input
outlets
Figure
1
Interconnected
Systems
Figure
2.
Input
and Output
Arrays
W o r k r e p o r t e d h e r e i n w a s - s u p p o r L e d i n p a r t by Projeet lvIAC, an M . I . T . r e s e a r c h p r o j e c t
sponsored by the Advanced Research projects Agency, Department o f D e f e n s e , u n d e r O f f i c e
of Naval Research Contract Nonr-4102(01).
I
ACM 1970, Conference
Record
CONCIJRRENT
SYSTEMSAND PAMLLEL COMPUTATION
108
S.
which
the system interacts
with
other
and sends out output
signals
points
a system is
qhich
through
to a system through
outPuts
of
cussion,
an inlet
an ordered
Thus an inPut
each outlet
A prefix
(i.e.,
relation
Ar < A denotes
a Proper prefix
the array.
is
an array
interacting
input
inlets
is
an array
that
of A,
of
an array
signals
having
the only
Ttre inputs
and
In our dis-
to as an array.
for
of
each inlet
a sequence of
are prefixes
whose elements
array
i.€.,
At
a prefix
is
At {A
an array
of
of
of
the
signals
for
the corresponding
(Figure
the array
of At is
and some element
shorter
A defined
by a slice
t
is
The
that
than the
signals).
a prefix
once, and thus defines
exactly
3).
A, and Ar < A denotes
the array
thaE the elements are sequences of
each seguence in aq array
The prefix
be referred
inlets
alphabet
draqm from the alphabet.
sequences of signals)
of A (recall-
element
are
svsterns.
dravm from a finite
a sequence of
also
through
and outl-ets
rnTith other
signals
signals
having
signals
PATIL
2).
the corresponding
cuts
of
from the system is
elements
A slice
receives
Moreover,
sequences of
the system (Figure
of an array
corresponding
capable
it
set whose el-ements are sequences will
to a system
of
outlets.
are sequences of
the system are also
system and the output
At is
through
systems;
S.
of
denoted by Ar.
In relation
to an array A, a slice r, is said to be -before or earlier
than r^ if
I
L
12
-;
in this case ,r, is said to be after
or @!g
than r'
If the array, defined
by a slice
is not a prefix
of the one defined by another slice and vice versa, then the
A
T l-
< A
two slices
are not related
In dealing
of
with
time and are
slice
t,
are equal
if
r,
later
to or larger
Ttre time
for
together
the initial
in
is
than r,
systems,
time slices.
sl-ices
A slice
and the individual
than the corresponding
are signal
sequences of
a sequence of
time slice
the array,
as there
with
called
of
relation.
t,
called
and in
successive
is
Thus for
can be more than one such sequence of
the array
is
of
least
array
of
by r,
one slice
of
the ar-
the system.
where the first
at
defined
time slices
and outlets
a given
instants
by at most one signal.
successive
time slices,
with
to be a successor
said
sequences in
the inlets
the sequence there
a history.
are associated
sequences in f,
a system is marked by a sequence of
ray whose elements
ray
inpuEs and outputs
therefore
is
by the above mentioned
time slice
past
every
An aris
signal
may be many histories
there
time slices.
-/i\
1(i)
is
r(j)
a pref ix
,"
4r(i)
is
Figure
ACM CONFERENCE
RECORD, L97O
or 6r
a successor
o = r(0)
history
than 1(k);
earlier
r(1)
(k);
r(i)
f
< rG)
(i)
u or(k)
of 1(i)
...
= (A,o.)
3,
PROJECTMAC CONFERENCE
r09
CIOSURE PROPERTIESOF DETERMINATESYSTEMS
It
not
should
an input
world
this
output
be noted
that
history.
the input
Thus an input
means Ehat an input
is also
an array
defined
can be reached by any one of
a system gives
for
considered
here,
to be a signal
couLd have moie than one history.
and can be reached by aq1 one of
Ttre interpretation
the systems being
of a system is
this
several
several
the input-output
relation
is
ways.
and
Similarly
the
the systeD.
For
ways.
relation
a function
ariay
In the physical
that
of
maps inputs
into
outputs.
X + Y
I:
Furthermore
for
the set of inpuE arrays dnd y is
output arrays over the alphabet of signals
where X is
the set of
the systems being
tency requiremenE
given
considered,
Requirement -
Consisteniv
the
interpretation
must satisfy
the consis-
beJ.ow.
If
Xl
is
a prefix
of X,
then I(Xr)
a prefix
is
of
I(Xr):
Xt (XZ + r(xr) < r(x2)
It
may be noted
tion,
that
if
the consistency
the transformation
represents
requiremeni
holds
for
the input/output
transforma-
a function.
Xl=XZ=Xl{XrandX2{Xt
r I(x1) < I(X2) and I(xr) < I(Xr)
* r(xr) = r(x2 )
Moreover,
some inPut
in
until
operation
that
cause and effect
ship
its
input
is
relationship
imposes the foLlowing
the history
of an output
be the earliest
r(i)
t
such that
in sequence q.
unconditionally,
holding
or certain
system until
which
it
other
has acted
ments hold
we shall
conditionally-,
denote
yr(n),
and for
- "t(i)
Yr(j)
the class
output
words,
This
that
depends on
the system holds
cause and effect
a
relation-
histories
...,
r(n)
any time slice
".,a let
r(i-1)
be the sequence of
r(j)
time slices
the sequence, let
in
be the inmediate
r(i)
predecessor of
< r(x"(i-1)).
conditions
and dependency requirements
of
hold
conditional
the type
on the preVious
and dependency requirements
and output.
on signal
some they may hold
the above requirements
In other
Let o = t(0)r(1),
the consistency
and for
received.
between input
Then yr(i)
Fof some systems,
actually
requirement
Deoendencv Reguirement in
a system cannot produce a certain
one.
be called
then the systems are
of unconditionally
to certain
thaE a new signal
We shall
unconditionally.
hold will
stated
first
manner of use or
not be sent
consider
The systems for
determinate
called
to
the
systems for
which
sysEems;
conditionallv
determinate
above may hold
if
the consistency
these require-
determinate
systems.
systems by s.
CONCURRENT
SYSTEMSAND PAMLLEL COMPUTATION
S. S. PATIL
110
lhe
is
aggregate
an array
of
two arrays
whose first
(sequences),
A and B of m and n elements
m elements
of arrays
are that
as A EB,
written
n elements
A and the remaining
are
that of B.
The following
theorem shows that
Lhe class
of systems S is
closed
under inter-
connection.
The Cl-osure Property
lheorem 1.
Proof:
of
Un-qonlitionally
Any interconnection
To prove
this
systems frorn S is
following
is
in
sufficient
S.
With
reference
X + Y and Xt, .
Y',
the dependency requlrement
of
S, and S,
x = x1 trX,
the
to Figure
also
in
of
interconnection
4 this
S.
means that
the
any input
= xi
and x'
i.e.
holds,
implies Y < Yl
then X <Xt
holds
of
histories
(Fi8ure 4) such that X ( Xl,
for
signal
of
histories
the system.
trxj,
of two subsystems
the system consisEing
and 1et Y = I(X)
that x <x',
from the fact
and Y' = I(x').
it
follows
Since
that
(r)
x r < x i a n dx , ( x j .
To show that
that
Y ( Y',
Suppose Y * Y'.
ur(i)
it
is
S, and.S2 "t"
Let o = r(0)
r(1)
* v'
only
necessary
determinate
to show that
t(j)
slice
be the earliest
And to show
U ( Ur and V < vl
systems as they are in
be a sequence of time slices
...
Ihen'let
* u' or vr(i)
Yl < Yi and YZ < Yi.
one must show that
Yl ( Yl and Y2 < Yi,
because system:
tuo
requirement
the consistencv
Let X and Xtbe
to shor^7that
requirement
the consistency
(ii)
number of systems from S is
be shornrn:
if
Proof
it
also
should
(i)
of a finite
theorem
Sys.tems
Qgterninale.
S.
associated with
X -f Y.
in o for which either
or both.
holds
Since the dependency requirement
for
the individual
systems S, and S'
we have
Y
U
^1
"2
s1
Y
Figure
ACtf CoNFERENCERECORD, L97O
4.
PROJECTMAC CONFERENCE
CLOSIJREPR.OPERTIESOF DETERMINATE SYSTEMS
l1t
uJ r ( i ) <
\ r
r 2^\ (
^ 2x I ( j - 1 ).L ,' v, r ( i - 1 ) ,r
r
Now,X, tr vr
1i-l \
(J-r/
< r(j)
r(j-f)
(2)
< xi tr Vr becausexz < Xi
and r(j)
from the consistency
the earliest
is
(from 1) and Vr(j-1)
sLice for which vr(j)
< Vr because
I y'.
Iherefore,
requirernent
rz(xztrv" (j-1)) < 12(xitr v')
that
is
Tr(xrEvr(j-1)') < u'
(3)
From 2 and 3 we get
< U'
U[(j)
Thus we have a contradiction,
consistency
Froof
of
condition
r(i)
is
the dependency requirement
But neither
of
*
for
S is
also
I
these can be true
This is
of
type
the class
It
transitions,
are systems of
type S,
type S gives
many important
results
initial
quences for
of
the marking
initiai
or
rt'i\
*, . ,- 2 *r -*2r ( j - 1 ) . , r r ( j - 1 ) r ' )
Y2"'
that
is easily
i< rr(xlr(j-1)
x u"(j-1))
holds
both
for
the dependency require-
Therefore,
of
Ttrus interconnection
there
is
two systems
about
is
are
marked graphs of Anatol
the transitions
seen that
that
them, €.8.,
which
infinite,
i.e.,
of
marked graphs are systems of
if. a marked graph is
is reached.
thaE is
[1].
considered as
are interconnections
not
reached when the graph comes to a halt
condition
Holt
and the
as systems,
the transitions,
marked graphs,
a simulation
inarking
consider
The knowledge
the way the terminal
marking
that
vr(j)
of as signals,
S, and therefore,
given
eirher
S systems,
points:
same regardless
a
in S.
in a graph can be thought
marking,
exists
for which the output is at.least
slice
system.
systems,
an initial
V ( Vf , and the
Then there
as the dependency requirement
places as interconnection
in
does not ho1d,
a contradiction.
the interconnected
As an example of a class
are
Sirnilarly
t,"ttj-l)).
inrplies
11r(3-1))
systems S, and Sr.
ment holds
the earliest
is
thar yr(j)
true
yr(j)
The markers
U < Ur.
satisfi6d.
such that r(i)
Y T ( J ) and it
frqn
is
and therefore,
the dependency requirement
Suppose that
s lice
nas ur(i) 3y'.
but our hypothesis
infinite,
Furthermore,
Ehen all
the graph is
live
if
live
is
the
for
a
simulation
for
that
for
semarking.
CONCURRENTSYSTN,IS AND PARS,LLEL COMPUTATION
TL2
S. S. PATIL
ConditionalLy
In
Determina.te
the
Systems
case of a conditionally
requirements
hold
conditional
assume many forrns,
as for
example,
be from a subset
of all
new input
not be sent
to act
signal
possible
on the previous
to the eDtire
is
conditions
dividual
signal.
system in
the
provision,
under this
the
of
arrays.
system.
conditions.
could
be thaE the
Another
condition
about
them.
input
system be true.
the interconnected
system will
a
is
required
hold
The following
might
is
for
and it
that
the
the in-
theorem states
(subject
be determinate
apply
kinds,
different
and dependency requirements
interconnected
system
be that
whil.e others
A11 that
the
to
may
system has had a chance
be of
could
The conditions
could
that
be local
could
and dependeney
consistency
certain
The conditions
consistency
the
of a system until
Some conditions
to be any more specific
under which
system,
the condition
input
to the inlet
interconnected
not necessary
determinate
to the holding
that
to those
condi tions ) .
Ttreorem 2.
An interconnected
systems is
The proof
that
determinate
of
under which
the
To gain
consider
conditions
bitrary
uation
in
this
case,
shornm in
an arbitrary
a place
in
it
Figure
nature
pacity
not
5.
In
to hold
because of
signals
large
is
an arbitrary
we sha1l
now
may be occasions
than the rate
a functional
storage
t,
that
gets
systems,
ahead of
is
such a sit-
place
tr.
p may have
Ttre ability
crucial
to
such infinite
systems.
on
the ar-
to store
figure,
however,
at which
transformation
capacity
An example illustrating
of praetical
the finiteness
change
the conditions
systems,
there
number of markers
In practical
of
only
are determinate.
greater
shown in
on how tar
Figure
ACM CONFERENCE
RECORD, L97O
systems,
to perform
the marked graph
systems
the
systems are deteminate.
aE the node.
depending
of marked graphs.
possible
input
1 with
Iheorem
deEerminate
deterrninate
the system is
signals
of
to the holding
conditionally
must have arbitrary
number of markers
a marked graph
terminate
is
of
determinate
those conditions.
Ehe interconnected
at which a system receives
If
of
the proof
under which practical
number of unused input
is
ln
of unconditionally
up those signal-s.
the input
to the holding
become conditional
systems
a deeper understanding
In the operation
it.uses
the proof
individual
specific
when the rate
subject
the above theorem parallels
the staEements in
of a number of conditionally
system'consistirig
Finite
of
the decasystems
5.
PROJECT}4AC CONFERENCE
113
CLOST'REPROPERTIESOF DETERMINATESYSTEMS
are conditionally
determinate
keep unused input
signal-s
We wil-l
sent
say that
a new signal
is
is
sent
called
operation,
manner.
is
i.e.,
that
a system has assimilated
without
Finite
their
determinacy
it
is
of
an input
only
if
their
signal,
if
another
a previous
destr:oying
to a system on an inlet
a clash.
Therefore,
they are determinate
capacity
to
not exceeded.
on the same inlet
to it
lated
in
signal.
the previous
before
systems are determinate
interest
The situation
to clash-free
they are used in a clash-free
if
which guarantee
to examine conditions
wherein
signal- has been assimi-
conditional
can'be guaranteed only
may be
signal
clash-free
operation.
If
inlet
is
we consider
assimilation
must be ordered
to be avoided.
respect
with
a clock
the case of asynchronous
esting
and useful
In
input
put
the
and appropriately
signal
is
through
of
point
interconnection
is
a chain
on the chain
that
fron
such that
the signal
the preceding
at
in stating
the condicion
condition
the systems should
input
signals
treatment
nuLl
signal
is
and is
ceive
the first
follows:
Condition
.t
said
associ.ated
signal.
cy -
points
of Si,
the first
to which
x.
with
decide
not require
the
point
after
the in-
x.
at
and only
a if
on the chain
fact
depends on
is
used below
systems.
al-l
is no different
signal
cy for
is
inlets
condition
statement
inlet
to have been sent
thought
untiL
that
inlet
is
asynchronous
refers
of
be ready to receive
from any other
interconnected
following
if
points
interconnection
how the initial
that
of an
the system has made some progress.
until
the null
Ttre condition
an inter-
to depend on
said
with
point
asynchronous
we should
not
ardong signals.
gets
syscem a signal
The above mentioned
to have been assimilated
in
case is
associated
an interconnection
initial-ly,
it;
this
interconnection
are signals
We will
least
in
at
on the chain.
ready
not
ready
The
if
a
to the
to re-
systems is
to the external
as
world
connected.
A system of
to satisfy
an interconnection
nection
world
at
not
considered
the system is
onment is
Si+l
-
The word environment
to which
signal
interconnected
be treated.
in asynchronous
relationship
clash-freeness
In an asynchronous
cy can be stated
an inlet,
inlet
at
point
a for
inieial-Ly
of
the output
a to b and there
but
signals,
Ehe system sends out only
which
signal.
a clash
if
the onLy $ray to know the assimilation
b depends on a signal
the signal
Before
input
signal
below.
system,
signal
has been assimil-ated;
the assimilation
there
an output
to an_
sent
In synehronous systems
by a cause and effect
presented
interpretation
this.
for
a signal
the previous
of
timing
systems the gequirement
case of an asynchronous
signal
as an event,
ways of atlaining
systems such order must be established
In
signal
to the assimilation
There are several
can be done by using
this
of an input
such that
signal'on
interconneeted
condition
point,
Sr*r,
cy if
there
the last
the chain.
the svstem is
for
is
asynchronous
every
a circuit
signal
pair
consisting
on the chain,
(Note that
systems placed
of consecutive
in an envir-
signals
of a chain
of
S, and
intercon-
depends on the assimilation
the chain may pass through
the external
conne.cted.)
CONCURRENTSYSTEMSAND PAMLLEL
COMPUTATION
LL4
S. S. PATIL
From the discussion
tems if
and only
guaranteed
in
the system is
to be determinate
eonstructing
sign
if
two paragraphs
of asynchronous
(Ihe o-condition
in
connected
system is placed
system.
that
holding
A feature
system is
of
which
use of
g is
of
importance
The de-
sub-systems.
use of
Ehis condition.
work had been reported.)
that
the o-condition
because it
undesirable
sys-
hardware systems can be
to attain
clash-free
in which
to depending on the interconnections
to a new environment.
connected
asynchronous
depends on the environment
the condition
in addition
is
after
for
condition
[2] makes implicit
unti1
the straightforward
is
operation,
system from determinate
asynchronous
modul-es from micro-modules
operatlon
cv holds
Since asynchronous
under clash-free
had not been formalized
One difficulty
condition
clash-free.
only
a determinate
earlier,
a new test
ca11s for
This difficulty
the inter-
within
every
Ehe
time
the
renloved by the use of
is
B-
systems discussed below.
B-Svs tems
g-systems,
In the case of
ports.
A port
consists
tems are
such that
received
through
input
signal
of
only
the
the ir,rlets and outlets
one inlet
one signal
inlet
a null
signal
sends its
signal.
hand a port
On the other
port
and does not
observing
connection
gent port
this
rule
first
and the output
output
send an output
signal
is
two ports
is
an incidenE
until
signal
is
port
port,
is
and that
for
a signal
afEer
designated
signal
together
a port
if
the
as an
by the port.
ready
an input
to receive
an in-
is received.
to have property
may be connected
Lhese sys-
sent out only
initial-I-y
an input
said
called
the need to receive
without
as @!!gg
discipline
of a port
outlet
In the case of a port
signal
designated
that
and the other
the
through
by the system.
conrnunication
states
out
sent
of
The interpretations
Ehought to have been received
is
Tttus an emergent port
Put signal,
is
has been assimil-ated
emergent Port,
and one outlet.
Ehe port,
of
in pairs
of a sysEem occur
p.
A
The inter-
one of
them is
may not be connected
an emerto more
than one port.
An important
consequence of
interconnection
of
interconnection
of ports
and outlets
guaranteed
asynchronous
involved
in
of p-determinate
to clash-free
in general,
are members of
theorem 3.
a property
stated
cr-systern.
above is
ltris
great
importance
any
so because each
which meets the o-condition
Ttrus any interconnection
of
is
that
of
for
the inlets
p-systerns is
from the point
of practical
hardware
conditional
the
circuit
the interconnection.
-
discipline
in a clash-free
forms a local
to be clash-free
The class
denote
the signalling
p systems results
later
class
of
systems consists
operation
as well
S, the class
of
as those
those B-sysEems which are determinate
B-systerns r^rhich, considered
of unconditionally
determinate
systems.
as systems
We shall
p-systems by SF.
Any interconnection
ACM CONFERENCE
RECORD.1970
of a finite
number of systems frorn SF is
also
in
S9.
PROJECT},IAC CONFERENCE
CLOSIJREPROPERTIESOF DETERMINATESYSTEMS
115
Since SF c S, from theorem 1 the interconnected
Proof:
rem€lins to be shotm is
connected
system is
that
a p-system,
not
does not ho1d, but
this
is
the subsystems which are
Itrus,
theorem is
determinate
Theorem 4.
system is
dividual
system in
interconnected
system is
of a finite
in
of asynchronous
in
that
the inter-
the B-property
is aiso a port
of one of
S9.
number of
the previous
it
B-determinaEe
clash-free.
appLication
three
deals
with
systems is
the interconnected
paragraphs
Thus the condition
the interconnected
system is
condi-
also
a
a
the inter-
determinacy
for
system is met,
system is
earlier,
of
each in-
and from The6rem 2 the
determinate.
of
rnodular controt
formed by interconnecting
theorem,
from our disc-ussion
Thus the interconnected
One important
which
If
system.
Moreover,
connected
for
because Ehe port
Thus all-
B-systems.
From the argument given
B-system'
impossible
has a port
S.
a B-sysEem.
anal-ogous to the above theorem but
Any interconnection
B-detenninate
Proof:
then it
system is
in
p-systemS.
the interconnected
The following
tionally
the interconnected
system is
a p-determinate
system is
p-determinate
sEructures
for
systems is
system.
in
the design
cornputers [3r4].
and construction
These s.tructures
are
a few types of asynchronous modules which are B type systems.
the reLementary controlr
moduLes are p-determinate.
Thus
Of these asynchronousmoduies
from the theorem above,
the elementary
control
sEructures
are B-determinate
syscerns.
Conclusions
In conclusion
influences
the cloiure
Paper reports
provides
able
to deal with
vides
in
a way for
circuits
a different
the design
constructed
properties
on a choice
ther
practical
we say the choice
of determinate
with
are determinate
perspective
of asynchronous
properties
systems which
determinate
only
if
be considered
conErol
possible.
are conditionally
systems is
of practical
used in a clash-free
of systems and formalizes
a determinate
structures
input
to a system
sysrem under interconnection.
which rnakes such closure
dealing
conditionally
from them is
of what should
[3] with
some of
Ttris
The paper
determinate.
interest
manner.
Being
because
This paper pro-
the informal
the property
fur-
that
ideas
used
any structure
system.
CONCIJRRENTSYSTEMS AND PARATLEL COMPUTATION
116
S. S. PATIL
References
1.
A. W. Itol-t and F.
Conference
Cormnoner, Events and conditions.
on Concurr,ent Systems and Parallel
Record of
Computations,
the Proiect
l4AC
ACI.,I,New York 1-970,
pp 3-52.
2.
3.
S. S. Patil,
Circuits
October
1969.
S. S. Patil,
Project
4.
A Micro-modular
modular
J.
MAC, M.I.T,,
processor.
Implementation
MernolfAC-M-423 ,
l4acro-modular
B. Dennis,
Parallel
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Computation,
ACU CONFERENCE
RECORD, L970
the Control
Design of Asynchronous
Cambridge, Massachusetts,
Modul-ar, asynchronous
Record of
of
Modules of
control
Circuits.
Memo MAC-M-414,
May L969
structures
for
a high
the Pro-iect I'IAC Conference on Concurrent
ACM, New york
Basic Macro-
Pro ject I"IAC, M. I. T, , Cambridge, l'{assaehusetts,
performance
Systems and
L970, pp 55-80.
PROJECTMAC CONFERENCE