Silicon Integration Initiative
Introduction to Chip-Package Interface
Protocol Standard for 3D-IC Power
Distribution Network
Interoperability For 3D Stacked Die Design Flows
Norman Chang, VP and Sr. Product Strategist
Apache Design, Inc. (subsidiary of ANSYS)
Oct. 9, 2012
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3D-IC Chip-Package Interface Protocol - Goal
2
• Power grid analysis with optional package/PCB netlist for DC drop, dynamic
voltage drop, LdI/dt noise, AC analysis (impedance and resonance), and current
density/electromigration for wires, ports, and TSVs
• Optimization of PDN via the interchange of CPIP for 3D-IC what-if analysis and
parameterized optimization flow
• Enabling signal integrity analysis, particularly for jitter analysis of chip-to-chip
communication with vertically stacked-die or through a silicon interposer channel
3D Stack
2.5D Stack
SoC/Custom Die
Re-usable Die 1
TSV
Reusable Die
Si Interposer
TSV
Package
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TSV
SoC/Custom Die
Package
PCB
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Chip-Package Interface Protocol - Coverage
• Unified interface protocol for the following interface definition including
both Power/Ground and Signal ports
– die <-> die
– die <-> pkg
– pkg <-> PCB
• Compact equivalent circuit in SPICE format for CPIP-compliant models
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Chip-Package Interface Protocol Need for
Interposer-based Design
Die 1
Die 2
CPIP (die <-> die)
CPIP (die <-> die)
Interposer
CPIP
CPIP (die <-> Pkg)
Package
CPIP (Pkg <-> PCB)
PCB
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Chip-Package Interface Protocol Need for
Vertically Stacked Die
Die 2
CPIP (die <-> die)
Die 1
CPIP (die <-> Pkg)
Package
CPIP (Pkg <-> PCB)
PCB
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Chip-Package Interface Protocol - Overview
General Info
Model Properties
Signal Ports
Power Ground Ports
• CPIP Version
• Design Name
• Units
• Info on CPIP-ready model generation such as
simulation time, time step, command options used,
and excitation settings, etc.
• CompName-PinName ; X,Y location, layer
• NodeName ; NetName ; PadLandingMetal; SignalPortGroup
• PortType (die2die, die2pkg, internal, pkg2die, or other)
• All fields same as in signal ports
• PadType (power, ground, or other)
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Example Target Application
• CPIP-compliant model of a die or dies and CPIP-compliant pkg/PCB model can be
incorporated in a concurrent power integrity simulation of a 3D-IC design
Memory Die (40nm)
Logic Die (28nm)
LEF/DEF/GDS
CPIP-compliant Model
Silicon Interposer Die (65nm)
LEF/DEF/GDS
Package
PKG netlist in CPIP-compliant Model
PCB
PCB netlist in CPIP-compliant Model
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Concurrent
analysis
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Concurrent 3D-IC Voltage Drop Analysis Example
• Input multi-die design and corresponding process data (can be of different
technologies), all at once
• Impact from shared P/G nets and decap in interposer die can be factored into
memory and logic die
DvD Map of 3-die concurrent analy
Logic Die
LEF/DEF, 28nm tech
Memory Die
LEF/DEF, 40nm tech
Power Integrity
Tool
Concurrent Analysis
Memory Die
Logic Die
Silicon Interposer
LEF/DEF, 65nm tech
Pkg Netlist in
CPIP-compliant model
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Silicon Interposer
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CPIP-based Multi-die IR/DvD Analysis Example
• Most suitable when one die is external without the complete design database
• CPIP-compliant model is a die model with RLC network and current profile
with a CPIP header, generated by Power Integrity Tool(s)
• Enables simple hand-off and fast turnaround time
Logic Die
LEF/DEF, 28nm tech
Silicon Interposer
LEF/DEF, 65nm tech
DvD
Memory Die
Pkg Netlist in
CPIP-compliant model
LEF/DEF, 40nm tech
- die concurrent analysis
Power Integrity
Tool
CPIP-compliant model
Memory Die
Map of 3
Power Integrity
Tool
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Logic Die
Silicon Interposer
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Application of CPIP-ready Models in 3D-IC
Test Case
10
• Connected in a face2back manner
• “Top die” connects to “package”
through “bottom die”
• Bottom die PDN contains TSVs that
connect its M1 to back-side metal,
which connects to top die using
“copper pillars”
• CPIP-compliant model of package used
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11
CONCURRENT
MODEL BASED
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3D-IC Test Case Description for CPIP-based
Applications
Layout view of both die in
concurrent mode; pkg in
CPIP-compliant model
CPIP-ready
model
CPIP-ready
model
Model of top die (CPIPcompliant model) hooked to
bottom die layout; pkg in
CPIP-ready
model
CPIP-compliant model
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Top Die Demand Variation Example of a 3D-IC
Transient Analysis with CPIPs
12
Case A: top half of the top die is active
Case B: left half of the top die is active
Bottom Die (left) affected by operation of the Top Die (right)
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Interface with Other 3D-IC Open3D Workgroups
(Thermal and Pathfinding WGs)
• Shared 3D-IC assembly info for stack-up and per die placement information
• Standard per die power density map for 3D-IC thermal analysis (work done
with Thermal WG on the standard)
• Standard per die thermal map for thermal-aware electrical analysis and
CPIP-ready model generation (work done with Thermal WG on the standard)
Power Density Map
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Thermal Map
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Summary
• Current status
A final draft of CPIP document has been completed in PDN WG, and is ready to be
submitted to the TAB-level for review as v1.0
• Thanks for the hard work of the PDN WG over the past year
• Also, thanks to the SRC Interconnect WG for their early exploration of the
3D-IC Interface Standard and for their contribution to the 3D-IC term definition
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Current PDN WG Participants
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