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2008
Characterization of physical defects and fault
analysis of molecular and nanoscaled integrated
circuits
Sergey Lyshevski
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Characterization of Physical Defects and Fault Analysis
of Molecular and Nanoscaled Integrated Circuits
Sergey Edward Lyshevski
Department of Electrical Engineering, Rochester Institute of Technology, Rochester, New York 14623, USA
E-mail: [email protected] Web: http://people.rit.edu/seleee
Abstract – This paper reports a concept to design the defecttolerant molecular integrated circuits (MICs). The results are
applicable to conventional ICs which utilize solid-state devices. By
enhancing photolithography and other CMOS processes,
advancing materials and optimizing devices, some device and
circuit performance were improved. Unfortunately, some key
performance characteristics and capabilities were significantly
degraded. The performance tradeoffs and effects of the equivalent
cell size reduction are well known. The defects and faults at the
device and circuit levels must be accommodated. It is illustrated
that in general, the defects and faults can be accommodated.
1. INTRODUCTION
Faults and fault models should describe defects in the
circuit. A defect, as a failure source, is the unintended
difference between the IC hardware and its intended design.
The defects result due to CMOS and molecular fabrication
inconsistency (missing connect, missing or faulty component,
etc.), environmental (radiation-, temperature- and vibrationinduced defects) as well as other hardware and physical
imperfections. A fault is defined as a representation of the
defect at the function level. A physical defect in any IC can
produce multiple faults, and a single test cannot detect all
possible or actual defects. The problem of defect detection,
localization and determination should be solved. For solid-state
and molecular electronics, one may differentiate between soft
(parametric, e.g., high delay, low speed, coupling, immunity,
etc.) defects and hard (catastrophic) defects which cause faults.
There is a significant number of faults which may occur, and
there are controllability, observability, detectability,
equivalence, dominance and other issues to be resolved.
II. MICROELECTRONICS AND MOLECULAR ELECTRONICS:
FROM ICS TOWARDS MICS AND PROCESSING PLATFORMS
Microelectronics (solid-state electronics) and ICs are
progressing towards their physical and technological limits [1].
The dimensionality (effective cell size) has been gradually
reduced. Though the channel length is expected to reach ~10
nm and the insulator layer thickness is ~1 nm, these field-effect
devices utilize the conventional device physics. Furthermore,
quantum effects (tunneling, leakage, etc.) and discrete
impurities significantly degrade the device and circuits
performance. The device physics and technological limits for
the field-effect and bipolar-junction transistors result in the
minimum dimensionality ~20λ ×20λ and ~50λ ×50λ, where λ
is expected to reach ~25 nm by 2025, and it is projected that
λmin is ~20 nm [1]. The performance of the most advanced
~1000 ×1000 nm field-effect transistor is found to be of
concerns, particularly from the circuit design prospective.
Departing from microelectronics (which progressed to the
nanoscaled dimensions in 40 years ago or recently, depending on
which definition one implies), molecular electronics and
molecular processing are emerging [2-4]. The MICs can be
synthesized through hierarchical synthesis motifs utilizing
neuronal hypercells (ℵhypercells) as molecular hardware
primitives [2]. A 3D directly interconnected molecular
electronics concept utilizes a direct device-to-device
aggregation [2]. One needs to design reconfigurable circuits
and architectures, as well as to develop complimentary
software tools to cope with not perfect (partially defective and
faulty) ℵhypercells and circuits in arithmetic, control, inputoutput, memory and other units. Molecular electronics
(molecular processing) will result in MICs (molecular
processing platforms MPPs) with a significant number of
entirely or partially defective and faulty devices and
interconnect. The redundancy concept may not be effectively
applied, while reconfiguration ensures the soundness [5, 6].
The circuit reconfigurability capability is defined by the
yield, complexity, software abilities (to identify and tolerate
the hardware deficiencies), etc. Adaptability and
reconfigurability can be achieved through hardware
diagnostics, testing and analysis with the following mapping,
matching, switching, controlling, rerouting and networking
tasks performed by software [2, 5-8]. One designs – optimizes
– builds – tests/evaluates – reconfigures MICs. We develop the
following design rules:
M
M
1. Design and optimize ICs or PPs;
M
2. Apply the target ICs realization using the modular
ℵ
hypercell primitives;
3. Design a specific ℵhypercell template assessing the
expected yield and error rates;
4. Analyze and perform the bottom-up synthesis developing
and specifying the technology, processes, sequence order
M
and other tasks to synthesize ICs as an assembly of
ℵ
hypercell aggregates;
5. Synthesize ℵhypercells aggregates forming node lattices
M
which should realize ICs by utilizing hierarchical:
• (a) random assembly with random sequences, (b) nearrandom assembly with near-random sequences, or (c)
ordered assembly with deterministic sequences,
• specificity (terminal/interconnect-recognition, selfbinding, paring and complimentary compliance of
ℵ
hypercell primitives within node lattices),
• nearest-neighboring ℵhypercell placement motifs;
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514
6.
7.
Perform verification and testing;
M
Reconfigurate, characterize, evaluate and validate ICs.
These design rules define the random, near-random or
ordered (directed) ordering of ℵhypercells and their aggregates.
Using this hierarchical strategy, we ensure the soundness of the
integrated
design-synthesis-networking-and-reconfiguration
tasks. The proposed concept, though, results in
1. Sub-optimal solution (for random and near-random
ordering),
2. Significant complexity and constraints (limitations)
which are expected to ensure the following features:
• Affordability and high yield with tolerable error rate;
• Selectivity and specificity of ℵhypercells as processing
and memory primitives;
• Controllable self-assembling and robust binding/paring by
ℵ
ℵ
hypercell-ℵhypercell
and
hypercellutilizing
interconnect uniformity, complimentary compliance and
recognition;
• Overall aggregability, reconfigurability and functionality.
Figure 1 documents a 4×3×1 lattice with 12 interconnected
nodes Nijk [2]. Each node comprises 2×2×2 modular
ℵ
hypercells Dijk
engineered from molecular gates (Mgates).
M
Each gate can comprise of two or more molecular electronic
devices (MEdevices) depending on its device-level
implementation, functionality, application, etc. For example,
the memory ℵhypercells can be designed using MNAND gates,
while multiplexer, adder and multiplier ℵhypercells have tens
of Mgates. The nodes and ℵhypercells are connected through
the exterior (peripheral) and interior interconnects. A single
hypercell core represents a fixed motif and specific hypercells
from the primitive library, while a split hypercell core is
applied to assemble and network hypercells aggregates. The
,
synthesis will result in the defective or faulty hypercells
, interconnect miss and link
as well as to hypercells miss
miss. These defects and misses should be detected and handled.
N111
N121
D115
D111
D112
D118
D114
D113
D211
D311
D312
D321
D324
N321
D234
D322
D331
D327
D323
D334
N331
D247
D243
D345
D341
D337
D333
D242
D244
D332
D246
D248
D336
D338
D143
D241
D233
D147
D245
D237
D335
D142
D144
D232
D146
D148
D236
D238
D326
D328
D133
D231
D223
D141
D137
D235
D227
D325
D317
D313
D222
D224
D132
D134
D145
D136
D138
D226
D228
D316
D318
D123
D221
D213
D131
D127
D225
D217
D315
N311
D124
D212
D214
D122
N141
D135
D126
D128
D216
D218
D314
D121
D117
D215
N131
D125
D116
D346
D342
D348
D344
D347
D343
N341
Figure 1. Aggregated ℵhypercells Dijk within a node lattice
As documented, node N12, ℵhypercells (D123, D124 and
some other), interconnects (between D121-D122 and some other)
and a link (from D347) are defective or faulty. Furthermore,
D345 is missing. One needs to identify and isolate defective
ℵ
hypercells and nodes through reconfiguration. While partially
functional nodes can be utilized, it is very challenging to
employ partially functional ℵhypercells. The missing
ℵ
hypercells, faulty interconnect and links must be identified.
In microelectronics, various diagnostics and verification
algorithms are available using different test signals, vectors,
patterns, protocols and routing schemes. Those concepts, to
some extent, potentially can be utilized in molecular
electronics. However, due to different device physics and
technological limits, built-in-self-test strategies (linear
feedback shift registers are used to generate pseudorandom test
patterns for synchronous and asynchronous circuits), response
analyzers, observers, and FPGAs defect extraction, may not be
fully applicable. For communication, configuration,
combinational and memory circuits, algorithms are different.
Using the molecular hardware test logics, one can perform the
hardware-software tests with evaluation and diagnostics
features assuming the testability, controllability and
observability. The input-output mappings are utilized because
any defects, faults and misses lead to detectable and faulty
steady-state and dynamic behavior. The isolation, rerouting
and reconfiguration are performed to ensure functionality.
Novel concepts are needed to cope with high defect rates
of ℵhypercells due to defective MEdevices, imperfect
interconnect, partial assembly control, etc. The defect rate is
estimated to be much higher as achieved in the current 65-nm
and expected 45-nm CMOS technology nodes. For MEdevices
and ℵhypercells, the parametric yield is defined as the
fabrication technologies will mature and data will emerge. The
performance measures are random variables, and the yield is
Y=Pr(r∈R),
where r=[r1,r2,…,rp–1,rp] is the vector of performance measures;
R is the performance space, R={r|aimin•ri•aimax, i=1,2,…,p–1,p}∈úp; aimin and aimax are the lower and upper limits of the
acceptability of the ith performance.
The primitive parameters are also specified. The mapping
x→r from the parameter space to the performance space
defines r(x). Using the indicator function, the yield can be
estimated and evaluated using stochastic methods. As the
synthesis will mature to fabricate and evaluate ℵhypercells, the
probability distribution functions will result. This will lead to
the ability to evaluate metrics thereby enabling meaningful
comparisons between the reference designs and synthesis
yields. The performance and parameter variability are
significant factors to be analyzed.
III. PROPOSED CONCEPT
Let y(x) be the logic function of a combinational circuit C,
where x is the input vector. Hence, y(x) denotes the mapping
realized by C. The presence of a fault φ changes C into a faulty
circuit Cφ with the corresponding mapping yφ(x).
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Taking note of the testing inputs t, the input test vector
T={t1,t2,…,tn−1,tn}
provides a test sequence. One performs testing applying T
which should detect the detectable faults and distinguish
among them.
A complete fault location test distinguishes between every
pair of distinguishable faults. A complete fault location test can
diagnose a fault within a functionally equivalent class.
A test t detects a fault φ iff y(t)≠yφ(t).
A fault φ is detectable if there exists a test t which detects
φ, otherwise, φ is undetectable. Two faults φ and g can be
equivalent.
Faults φ and g are called to be functionally equivalent iff
yφ(x)≡yg(x).
If T can distinguish between two faults φ and g, e.g.,
yφ(x)≠yg(x), these faults are distinguishable.
There does not exist t which can distinguish between two
functionally equivalent faults. For test generation, it is
sufficient to consider only one representative fault from every
functional equivalent class.
We introduce a functional fault model to describe faults
from a given arbitrary level of abstraction to the next higher
level by means of the test generation design. Consider a
Boolean function
y=f(x1,x2,…,xn−1,xn)
which is implemented by a processing primitive in a circuit.
We introduce a defect variable d which represents a given
physical defect which affects y by changing the Boolean
function to be
y=fd(x1,x2,…,xn−1,xn).
A parametric function yp is a function of a defect variable
d. In particular,
y p = f p ( x1 , x2 ,..., xn −1 , xn , d ) = d f ∨ df d
describes the behavior of the primitive for both fault-free and
faulty cases.
For the faulty case, the value of the defect variable d is
d=1. For the fault-free case, d=0. Hence, we have
yp=fd if d=1, and yp=f if d=0.
The Boolean differential equation
∂y p
(1)
=1
Bd =
∂d
establishes the conditions which define the defect d as well as
results in t. The parametric modeling of a given defect d allows
one to perform:
1. Defect-oriented fault simulation by verifying the condition
Bd=1;
2. Defect-oriented test generation by solving the equation (1)
when the defect d is activated and tested using the logic
condition given by Bd.
To find Bd for a given defect d one derives the
corresponding logic expression for the faulty function fd by:
• Logical reasoning;
• Performing defect simulation;
• Carrying out experiments to derive the physical behavior
and f implemented.
Example 3.1.
Consider a molecular circuit reported in Figure 2 which
implements a switching function y = x1 x2 x3 ∨ x4 x5 .
x1
x4
x2
short
x3
x5
y
Figure 2. Circuit schematics
A short defect d, shown in Figure 2, changes the circuit
output to y d = ( x1 ∨ x4 )( x2 x3 ∨ x5 ) . Thus, we have
L
∂y p ∂ ( x1 x2 x3 ∨ x4 x5 )d ∨ ( x1 ∨ x4 )( x2 x3 ∨ x5 )d
Bd =
=
∂d
∂d
L L
LL
L
L
= x1 x2 x4 x5 ∨ x1 x3 x4 x5 ∨ x1 x2 x3 x4 x5 = 1
The derived expression provides three t. The test vector is
found to be T={10x01, 1x001, 01110}. Each t can be used as a
test pattern for the given d.
■
[
]
Example 3. 2.
Consider a MNOR gate with an open fault as illustrated in
Figure 3. The output retains its previous logic value. The
considered combinational logic gate behaves as a dynamic
memory element. The faulty function of the gate is
yd= x1 x 2 ∨ x1 x 2 y s ,
where ys is the output value stored at the output of the faulty
M
gate.
We have
y p = d ( x1 ∨ x2 ) ∨ d ( x1 x 2 ∨ x1 x 2 ys ) = x 2 ( x1 ∨ dys ) ,
and Bd = ∂y p / ∂d = x1 x 2 y s = 1 .
The condition to activate the defect is x1=1, x2=0 and ys=1.
Thus, for testing the fault one needs a test sequence of two
patterns, e.g., 00 (to obtain 1 on the output y), and, then 11.
V1
x1
x2
x1
y
x2
V2
Figure 3. Molecular gate with an open fault
■
One can map the interconnect defects. Consider a
primitive (P) with a Boolean function y=f(x1,x2,…,xn−1,xn) and
interconnect I={xn+1, … ,xp}. We apply the defect variable d to
represent physical defects in the circuit C=(P,I).
Let the defect d changes the Boolean function
f(x1,x2,…,xn−1,xn,xn+1,…,xp) to fd(x1,x2,…,xn−1,xn,xn+1,…,xp). To
model physical defects in C, we use the parametric function
M
y p = f p ( x1 , x2 ,..., xn −1 , xn , xn +1 ,..., x p , d ) = (d ∧ f ) ∨ (d ∧ f d )
which describes the behavior of the circuit for the fault-free
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and faulty cases. For the faulty case, d=1, while for the faultfree case d=0.
Thus, yp=fd if d=1 and, yp=f if d=0.
The solutions of the Boolean differential equation (1)
allows one to perform the analysis and obtain the conditions
which activate the defect d.
Example 3. 3.
Consider a short in a circuit as documented in Figure 4.
The parametric function is
y p = d ( x1 x2 ∨ x 3 ) ∨ d ( x1 x2 y ∨ x 3 ) = x1 x2 ( d ∨ y0 ) x 3 ,
where y0 denotes the previous value of y.
The Boolean differential equation (1) leads to
Bd = ∂y p / ∂d = x1 x2 x3 y 0 = 1 . Hence, one can test the short
as: (i) Set the value y=0 (for example, by assigning x3=0); (ii)
Apply the test pattern 111 (x1=1, x2=1 and x3 =1).
x2
M
AND x1 NAND x3
M
M
NAND
y
00001}. The derived T one ensures more than 99% of possible
fault detection.
M
x1 NAND
y1
x2
x3
.
x4
x5
y2
Figure 5. C17 circuit with six MNAND gates
Example 3. 5.
Consider a register at the gate level. The condition to
detect the defect d on the observable Y is
BD=∂Y/∂yM ∧∂ yM /∂yG ∧Bd=1,
where yM is the output variable of a logic level module; yG is
the output of a logic gate with a physical defect d.
In this equation, ∂Y/∂yM gives the high-level fault
propagation condition, ∂yM/∂yG is the fault propagation
condition (Boolean derivative) at the gate level.
■
IV. CONCLUSIONS
Figure 4. Molecular gates with a short
■
The described method represents a general approach to
map an arbitrary physical defect into a higher level. It was
shown that the method of defining faults by logic condition
Bd=1 can be used both in fault simulation and in test
generation.
Consider a node k in a circuit. The output of a module Mk
is yk. For Mk, consider a set of faults Rk=RFk∪RSk, where RFk is
the subset of faults in Mk; RSk is the subset of structural faults
(defects) in the network neighborhood of Mk. In general, Bd
allows one to examine conditions when the faults d∈Rk change
yk. We denote by BFk the set of conditions Bd activating the
defects d∈RFk, while BSk gives the set of conditions Bd
activating the structural defects d∈RSk. Using BFk and BSk, one
obtains a map of faults for test generation from a higher to a
lower levels, as well as for fault simulation and fault
diagnostics tasks. In test generation, to map a lower level fault
d∈Rk to the higher level, we use Bd=1. If Bd=1 is guaranteed,
the defect d∈Rk changes yk. For fault simulation and fault
yk
is
diagnostics,
an
erroneous
di∈Rk.
For
the
dy k → d1 Bd 1 ∨ d 2 Bd 2 ∨ ... ∨ d n Bdn ,
hierarchical testing, for each module Mk of the circuit one
studies Rk with logical conditions Bd for each d∈Rk. The set of
conditions BFk for the functional faults d∈RFk of the module is
found by low-level test generation for the defects in the
module. The set of conditions BSk for the structural faults
d∈RSk is to be derived from the Boolean differential analysis of
the fault-free/faulty functions. For the concept under the
consideration one considers d=(d1,d2,…,di−1,di).
Example 3. 4.
For c17 circuits, represented in Figure 5, by making use
the concept reported, we obtain T={10000 00101 01110 00110
We reported an innovative concept in the design of the
defect-tolerant ICs and MICs. The approach was illustrated for
various circuits. It is computationally efficient and applicable
to 3D-topology circuits. The defects and faults due to
ME
devices, Mgates and ℵhypercell can be accommodated.
Various illustrative results are provided.
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