`timescale Directive
• Timescales use two numbers: the reference
time unit and the precision.
p
• The first number sets the unit of
measurements for times and delays
delays.
• The second sets the precision, that is, the
smallest unit of time that the simulator will
track without rounding.
ECE 526
Compiler Directives
2
`timescale Rules
`timescale is a Directive
• `timescale uses back tick (`), not an
apostrophe (‘).
• The units of measurement can never be less
than the precision.
• `timescale is a Compiler Directive.
• This means that it does NOT follow certain
Verilog HDL conventions.
–1
1. The directive does NOT end in a semicolon
semicolon.
– 2. It is set BEFORE the module/endmodule
structure.
structure
– i.e. `timescale 1 ns / 10 ns is ILLEGAL
• Only 1, 10 and 100 are valid numbers for
specifying either time units or precision.
– i.e. `timescale 1 ns / 500 ps is ILLEGAL
3
4
Examples of Good `timescale
timescale
Directives
Meaning of Timescale Numbers
• Each Timescale directive has two numbers:
– `timescale 100 ps / 10 ps
• The first number says what the units of time
in the file are going to mean.
• `timescale 1 ns / 1 ns
• `timescale
timescale 1 ns / 100 ps
• `timescale 100 ps / 10 ps
– #10 CLK <= 1’b0;
– Wait for 10 time units, then assign a value of
zero to signal CLK.
– 10 time units means 1 ns here.
5
6
`timescale
timescale Compiler Directive
`timescale
timescale Compiler Directive
• `timescale compiler directive specifies the time unit and its
precision, which is used in measuring times and delays. It has
the following format:
`i
`timescale
l <time_unit>/
i
i / <time_precision>
i
ii
Where:
<time_unit>
specifies the time unit.
<time_precision> specifies the precision used in
rounding
di ddelay
l values
l
bbefore
f
using
i them
h iin
simulation.
• Each of <time_unit> or <time_precision> consists of an integer,
to represent
p
the magnitude,
g
, followed byy a time unit specifier.
p
• The valid values of the magnitude are 1, 10, 100.
• The valid time unit specifiers are: s(second),
ms(millisecond) = 10E-3 second,
us(microsecond) = 10E-6 second,
ns(nanosecond) = 10E-9
10E 9 second,
second
ps(picosecond) = 10E-12 second,
fs(femtosecond) = 10E-15 second.
and
• The `timescale compiler directive must be written outside the
boundary of the modules.
• <time_precision>
<time precision> must be at least as small as the <time_unit>
<time unit> .
7
8
`timescale
timescale Compiler Directive
Directi e
Timescale Resolution
The time unit of the simulation is determined by the smallest
value of all the timescale directives.
directives
• The second timescale number specifies the
granularity in which the simulation will be
run.
`timescale 10 ms/ 1 ms
// all time units are in tens of milliseconds
module \2*4_bin_dec (f0,f1,f2,f3,I1,I2);
– `timescale 100 ps / 10 ps
input I1, I2;
• This will cause rounding for any unit of
time less than 10 ps.
output f0, f1, f2, f3;
– and #1.26 ANDGATE1(OUT, IN1, IN2);
• OUT will change 130 ps after IN1 or IN2
9
The values in the modules are multiples
of 10 ms
ms, rounded to the nearest ms.
ms
Therefore, the not time delay will be rounded to
17 ms and the and time delay will be rounded to
26 ms.
not #1.66 not1 (\~I1 , I1);
not #1.66
#1 66 not2 (\~I2 , I2);
and #2.578 and1 (f0 , \~I1 , \~I2 );
If the time precision was 100 us instead,
and #2.578 and2 (f1 , I1 , \~I2 );
the not time delay would have been set to 16.6 ms
and #2.578 and3 (f2 , \\~I1
I1 , I2 );
and the and time delay would have been rounded to
and #2.578 and4 (f3 , I1 , I2 );
25.8 ms.
10
end module
Timescales and Hierarchy
Timescales and Time Delays
• Even simple
p Verilog
g designs
g have hierarchyy
– Example: test bench instantiates DUT
Outside of the module there should be a timescale
directive:
`timescale 1 ns / 1 ns
• Verilog
g compiler
p
over-writes timescale
every time a new one is read.
• Thus a module containing
g time delays
y but
no timescale directive will use the last
timescale directive read, which may not be
what is wanted.
• Moral: if a module contains time delays, it
must also contain a timescale directive.
In the absence of such a directive, most simulators will
default to 1 ns / 1 ns. This is not guaranteed.
Even
E
en if 1 ns / 1 ns is what
hat you
o want,
ant it’s good policy
polic to
explicitly put it in each file. Failure to do so can have
surprising results.
11
12
`define Compiler Directive
`define Compiler Directive
• The `define
define directive is used for text substitution
substitution. It has the
format:
`define gate
and
`d fi gate_delay
`define
d l
#2
`define not_delay #1
module \2*4_bin_dec (f0,f1,f2,f3,I1,I2); module \2*4_bin_dec (f0,f1,f2,f3,I1,I2);
`define
define <macro
<macro_name>
name> <macro_text>
<macro text>
input I1, I2;
output f0, f1, f2, f3;
input I1, I2;
• When used in a Verilog code, the compiler will replace
`macro
macro_name
name with macro
macro_text.
text
• The `define directive does not get affected by `resetall
compiler directive.
output f0, f1, f2, f3;
nott #1 not1
t1 (\
(\~I1
I1 , I1);
I1)
not `not_delay not1 (\~I1 , I1);
not #1 not2 (\~I2 , I2);
not `not_delay not2 (\~I2 , I2);
`gate `gate_delay and1 (f0 , \~I1 , \~I2 ); and #2 and1 (f0 , \~I1 , \~I2 );
and #2 and2 (f1 , I1 , \~I2 );
` t ``gate_delay
`gate
t d l and2
d2 (f1 , I1 , \~I2
\ I2 ));
and #2 and3 (f2 , \~I1 , I2 );
`gate `gate_delay and3 (f2 , \~I1 , I2 );
and #2 and4 (f3 , I1 , I2 );
`gate `gate_delay and4 (f3 , I1 , I2 );
end module
end module
13
`define Macros and Parenthesis
`define is dumb macro substitution
• Define is for macro substitution.
• It will just substitute whatever follows the
macro name.
–
–
–
–
–
–
14
– Example: `define CUCU a+4
• Then you want to multiply CUCU by 12
`define whatever 1234;
`whatever
whatever will be 1234;
Semicolon will be included.
Usually that’s
that s not what is wanted
wanted.
`define whatever 1234
Now `whatever
whatever will be replaced with 1234
1234.
– `CUCU * 12
• What you get is
– a + 48, because multiplication has higher precedence
than
h addition.
ddi i
• To get 12a +48, use parenthesis
– `define
`d fi CUCU ((a+4)
+4)
15
16
https://www.synopsys.com/news/pubs/snug/boston2008/bresticker_paper.pdf
Trying Too Hard
Homework 1
• Multiple things to define: can they be
combined?
• Homework 1 is now posted on the course
web site.
• It will be due in one week.
– Try `define one 1, two 2
• No go.
go
• Must use one `define per macro
17
18
Lab Reports
Lab Reports
The most important elements of lab reports
are:
– Statement of what you are accomplishing,
demonstrating, determining, etc.
– Methodology: statement of how you did it.
Specifically includes test plan.
– Analysis of results: what did you
demonstrate/prove.
– Conclusions.
C l i
• All Verilog files need header and in-line
comments.
• Computer printouts (source code, test bench
code wave pictures
code,
pictures, log files) are
supporting documentation, NOT an lab
report by themselves
themselves.
• Your lab report should reference this
supporting documentation.
documentation
19
20
Modeling In Verilog
• Structural Modeling
– The entire hierarchy is built from primitives.
Behavioral Modeling
• Behavioral Modeling
– Algorithmic-Based Modeling
• In this modeling, a procedural code is used to describe the
input/output behavior without any details about actual hardware
implementation.
– Data Flow/RTL Modeling
• In Data Flow/RTL Modeling,
g, Verilogg HDL operators
p
are used to
describe the model behavior.
22
Four-bit
Four
bit Counter
HDL Counter
reg [3:0] Count;
always @(posedge CLOCK) Count <= Count + 1;
/*Verilog oddity: “Count++” is NOT supported syntax*/
23
Image © Texas Instruments
24
Modeling In Verilog
Customization is Easy
Full Adder Boolean Equations:
S=A^B^C
Co = A•B + A•C + B•C
always @(posedge CLOCK) begin
if (COUNT == 27) COUNT <= 0;
else if ((COUNT == 13)) COUNT <= 15;;
else COUNT <= COUNT + 1;
A
A B
B
end
C
Co
Co
Full Adder
T that
Try
h with
i h K-maps!
K
!
S
25
Structural ModelingA
module full_adder (Co, S, A, B, Ci);
input A, B, Ci;
output Co,
Co S;
xor (t1, A, B);
xor (S,
(S t1,
1 Ci);
Ci)
and (t2, A, B);
and (t3, A, Ci);
and (t4, Ci, B);
or (Co, t2, t3, t4);
endmodule
Co
26
Data Flow/RTL Modeling
Ci
module full_adder (Co, S, A, B, Ci);
input A, B, Ci;
output Co, S;
S
Co
S
Behavioral Modeling
B
Full Adder
A B
Ci
Ci
A
Co
Ci
Full Adder
assign S = A^ B ^ Ci ;
assign Co = A&B | A&Ci | B&Ci ;
Ci
B
S
endmodule
S
27
28
Behavioral Modeling
D t Flow/RTL
Data
Fl /RTL Modeling
M d li
Behavioral Modeling
module
d l ffull_adder
ll dd (C
(Co, S,
S A,
A B,
B Ci)
Ci);
A
B
input A, B, Ci;
output Co, S;
Co
assign {Co, S} = A+ B+ Ci;
endmodule
Ci
Full Adder
• If you were actually going to model something so trivial as
a single-bit adder, behavioral would be the way to go.
Structural HDL using primitives is useful for library
development, not for digital design.
{Co S} = A+ B+ Ci;
{Co,
S
• Modeling individual components at such a detailed level
d f t the
defeats
th purpose off using
i HDL andd synthesis.
th i
Note use of addition operator. “+”
+ is NOT the same as logical and.
29
30
Basic Rules
More Basic Rules
• All the action takes place within “Modules.”
• One module per file is good practice
practice.
• Give modules and files meaningful names,
preferably the same names
names.
• Use synchronous design techniques
whenever
h
possible.
ibl
• Every file requires documentation,
especially in the header.
• Commenting code is not something you do
after the project is done, maybe, if you have
time. It is an integral part of the design.
• Unlike assembly language programming,
there is no premium on writing tight, cryptic
Verilog.
31
32
P
Procedural
d l Blocks
Bl k
Procedural Blocks
•Procedural Blocks are used in test fixtures to apply stimulus and display
results .
• They are of two types:
* Procedural blocks are activated at time 0 and executed
when the associated condition becomes TRUE.
* initial procedural blocks, which executes only once.
* always procedural blocks, which execute continuously in a loop.
initial Condition
begin
------------end
* If there is no condition, procedural block is executed
immediatelyy followingg its activation.
always Condition
begin
-------------
* All procedural blocks are executed concurrently.
end
Initial procedural blocks are used not only for initialization but also for
all operations that need to be executed once.
33
Procedural Blocks and Synthesis
• always blocks are synthesizable.
• initial blocks are not.
not
• What kind of sense does this make?
34
Initial and Always Blocks
• Both initial and always blocks are useful in
test fixtures.
• Only always blocks may be used in
synthesizable code
code, ii.e.
e circuit descriptions
descriptions.
35
36