IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011
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A 6-Gb/s MIMO Crosstalk Cancellation Scheme
for High-Speed I/Os
Taehyoun Oh, Student Member, IEEE, and Ramesh Harjani, Fellow, IEEE
Abstract—A continuous-time multiple-input multiple-output
crosstalk cancellation (MIMO-XTC) architecture operating at 2–6
Gb/s has been proposed. The performance of the XTC equalizer
has been measured with various spacings of FR4 channels and data
rates. The crosstalk energy reutilization technique efficiently handles crosstalk and achieves high signal integrity in severe crosstalk
environments where crosstalk had completely closed the data eye.
Measurement results show improvement in
and vertical
opening of the eye diagram by 67% UI and 58.2%, respectively,
which is the best known improvement to date. The MIMO-XTC
portion occupies 0.03 mm and consumes 2.8 mW/Gbps/lane,
which is two times lower than previously proposed XTC schemes.
Index Terms—Bandwidth, equalization, high-speed links, intersymbol interference (ISI), jitter, multiple-input multiple-output
crosstalk cancellation (MIMO-XTC), parallel interfaces, pre-emphasis, pulse response, single-ended I/Os, vertical eye-opening.
I. INTRODUCTION
R
APID advances in CMOS technology continue to
increase the on-chip clock speeds exponentially, while
high-speed I/Os that are used to connect between chips continue
to be a performance bottleneck for the system. Finite-channel
bandwidths generate ISI and reduce the amplitude of the received signal and thus degrade SNR. Techniques to mitigate
ISI in single wireline channels have been used for more than
a decade, and systems operating at 20 Gb/s have recently
been published [1]–[6]. With increased speeds, I/Os become
more vulnerable to electromagnetic interference (crosstalk)
from adjacent channels. Channel equalization, in the form of
pre-emphasis, that is often used to tackle ISI, unintentionally
increases crosstalk by boosting the high frequency signal
component. A number of XTC techniques have been proposed
to remove the effects of crosstalk [7]–[13]. Jitter equalization
[7], [8], staggered I/Os [9], [10] and amplitude XTC with
a finite-impulse response (FIR) filter at the transmitter [11]
can be used to reduce the effects of crosstalk to a limited
extent. However, these schemes result in increased current
consumption and have limited or no impact on channel spacing.
Current crosstalk cancellation techniques do not adapt well to
I/O systems where power efficiency is critical [14]. In most
high-speed links, crosstalk is avoided by maintaining sufficient
Manuscript received November 30, 2010; revised February 03, 2011; accepted March 28, 2011. Date of publication June 09, 2011; date of current version July 22, 2011. This paper was approved by Guest Editor Pavan Kumar
Hanumolu. This work was supported in part by a grant from the Semiconductor
Research Corporation.
The authors are with the University of Minnesota, Minneapolis, MN 55455
USA (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2011.2151410
distance between channels and/or shielding the channels at
a higher cost, choosing differential I/Os at the expense of
doubled power, I/O pins and board area, or running the system
at lower data rates with closely spaced parallel channels. The
techniques developed in this paper rely on two distinct characteristics. First, we regard the crosstalk as a signal component
that can be reutilized to increase SNR which contrasts with
other XTC schemes where the crosstalk is simply considered as
a noise component to be removed. Second, the continuous-time
MIMO-XTC, introduced here, relies on cancelling a continuous-time phenomenon using a continuous-time technique.
This results in very efficient handling of the high-frequency
crosstalk signal and its cancellation.
The remainder of this paper is organized as follows. Section II
introduces the far-end crosstalk (FEXT) channel model for both
single-ended and differential I/Os and develops an intuitive
technique for pulse response analysis in terms of eye-diagram
properties. Section III proposes a new 2 2 MIMO-XTC
algorithm. A CMOS prototype implementation of the 2 2
MIMO-XTC for single-ended I/Os is presented in Section IV.
Measurement results are shown for the prototype circuit in
Section V. Section VI summarizes this work.
II. CHANNEL MODEL
A. Low-Impedance Microstrip-Line FEXT Model
FEXT in transmission lines is the signal energy that is
coupled between two closely spaced channels. When an active
signal is transmitted on one of the channels, as illustrated in
Fig. 1(a) and (b), the end of the adjacent channel receives the
coupled FEXT signal. If the adjacent channel transmits another
independent signal in the same direction, it will receive both
its own original signal and FEXT coupled from the adjacent
channel. Since these two signals are uncorrelated, the FEXT
degrades the horizontal and vertical eye-opening of the original
signal and is normally considered as noise. In a homogeneous
channel, i.e., strip-line, the inductive and capacitive coupling
is well-balanced and the FEXT becomes negligible [15]. On
the other hand, in an inhomogeneous channel like a micro-strip
line, significant crosstalk energy couples through the asymmetrical field [7]. However, micro-strip lines have a cost advantage
due to its convenient implementation so most interfaces are
manufactured using micro-strip lines. As PCBs are required
to have more and more channels in a limited board area for
higher data throughput, the physical spacing between channels
is reduced and crosstalk is rapidly becoming the dominant
factor affecting signal integrity.
Longer channel lengths and reduced channel spacings result
in a larger coupling coefficient and more crosstalk transfers
0018-9200/$26.00 © 2011 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011
Fig. 1. Pulse responses of NRZ signal and FEXT in single-ended I/Os. (a) Closely spaced single-ended I/Os. (b) Pulse responses. (c) Vertical and horizontal eye
margin. (d) Eye patterns.
onto the adjacent channel [7], [15]. Transmitted signals with
sharper transitions are more easily coupled because of the
high-pass filter characteristic of the crosstalk channel. Fig. 1(a)
presents the physical parameters used to formulate the crosstalk
model in single-ended I/Os.
is the channel length,
is
the channel width and
is the center-line distance between
channels. When the aggressor signal
is transmitted on
closely spaced channels, the FEXT signal
occurs at
the adjacent channel output as
(1)
where
(
) is the forward coupling strength and
is a function of channel length
and channel height. For
simplicity of analysis, we have assumed a fixed channel length,
channel height, and a constant transition time for the transmitted
signal. The crosstalk energy diminishes approximately by a
factor of , where, for single-ended I/Os, the nominal value
for
is between 1-2 depending on channel conditions [15],
[16]. In most low-impedance micro-strip lines used in portable
electronics, the inductive coupling component is dominant
and the FEXT pulse response is approximately the negative
derivative of the channel pulse response
[7], [11], [15].
B. Predicting Eye-Diagram Properties From the Pulse
Response
Here, we discuss the limitations of the previously proposed
FIR XTC filter in [11]. The channel ISI tails at a bit period of
and FEXT pulse response tails sampled at half a period
, as
shown in Fig. 1(b), are immediately related to the eye opening
level and jitter performance of eye-diagram. An algorithm to
determine the crosstalk cancellation tap weights has been suggested in [11]. However, the FEXT tails half a bit period away
from the eye-center timing,
significantly limit the
efficacy of XTC schemes with integer FIR taps.
The eye-diagram performance can be directly evaluated
from the shape of a single pulse response analytically. Experimentally, this single pulse response can be conveniently
measured via a digital sampling oscilloscope and a pulse generator. We propose a method to calculate the
and the
vertical eye-opening from a single output pulse. As shown in
Fig. 1(a) and (b), when a single pulse at the appropriate data
rate is transmitted, we can obtain the pulse responses of the
data and the crosstalk at the end of the channels, which are
expressed as
and
, respectively. The data eye-diagram
is a convolution of the pulse response
and the impulse
train sequence
and can be obtained by folding
it repeatedly with
integer multiple symbol periods. If we
assume that
is the response for a causal channel, then
,
. Further, for simplification in this analysis, we shall assume that the ISI tail is
limited to
and is zero for all positive values of greater
than 2. Then, the maximum data eye-opening can be directly
calculated as
in the worst case scenario. The
maximum magnitude of the vertical signal is
,
which is
larger than the maximum pulse amplitude
( ) due to the randomness of data. The time duration of the
maximum horizontal eye,
is the time interval between
the two points where the voltage level of the data pulse is
. As a result, the
becomes
.
In a highly lossy channel or higher data rates,
decreases
and the number of ISI tails and their magnitude increases and
therefore the eye-opening,
reduces. At the
same time, the horizontal eye interval reduces as the vertical
eye-opening
decreases and the two points are
brought closer together.
In the case of the crosstalk pulse response, shown in Fig. 1(b),
the maximum amplitude occurs at approximately half of the
two data eye centers. The crosstalk has its maximum amplitude during the data transition, typically
away from the
OH AND HARJANI: A 6-GB/S MIMO CROSSTALK CANCELLATION SCHEME FOR HIGH-SPEED I/OS
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Fig. 2. Skewed FEXT signal in a transmitter per-pin de-skew scheme.
data eye-center and crosses the zero when the data eye is at its
peak (i.e.,
). The maximum crosstalk amplitude
in the FEXT eye-diagram occurs at
away from the center of data eye, as shown in Fig. 1(d). On
the other hand, the integer crosstalk tails, and , align with
the center of data eye. If uncorrelated data and FEXT are combined, representing the case of crosstalk coupling to an adjacent
channel, the vertical eye-opening reduces by
in the
worst case and becomes
. Here,
we assume the delays between two channels are matched. The
maximum vertical eye-opening in the channel with both ISI and
FEXT can be more generally written as
(2)
The FEXT tails,
and
take place during the data
transitions and disturb the timing. The absolute magnitude of
and
are larger than
and , and, therefore, the
majority of the crosstalk energy is normally transformed into
jitter. The detailed behavior of how crosstalk affects timing
variation is described in [7], [8]. Additionally, in situations
where per-pin de-skew scheme may be applied, as shown in
Fig. 2, the
will further reduce because the timing of
FEXT center ( ) does not align with the timing of data center
( ). A simulation of the performance degradation in situations
where a per-pin de-skew scheme may be required is presented
in Section V.
Similar degradation by the
and
crosstalk occurs
even at lower speed signals. Here, the lower speed applies to
the overall data rate. We note that ISI tails are limited at this
lower rate for the limited loss cases. For example, as illustrated
in the low speed signal pulse response in Fig. 3, the integer
ISI tails (
) are zero and do not influence the following
symbol amplitude at the data center. In this example, the integer
crosstalk tails (
) are zero and the crosstalk tails at
and
only degrade the timing variation. For both lowspeed signal and high-speed signal, the large amplitude of
and
limits the benefits of crosstalk cancellation schemes
with integer FIR filters that have maximum effect only at the
center of the eye. Fractional taps are required to remove the
noninteger crosstalk tails, which increases the necessary clock
speed and power. Reference [11] proposes a zero-forcing algorithm to optimize the tap weights for the FIR filter for maximum
crosstalk cancellation. Here, 25-mW/Gbps/lane power is consumed to drive the digital taps with sufficient speed.
Fig. 3. NRZ signal pulse response
data rate versus high data rate.
and FEXT pulse response
(low
Moreover, XTC with a FIR filter is preferentially implemented on the transmitter-side due to availability of the timing
information coincidentally with the crosstalk signal. A typical
FIR filter with discrete taps at the receiver samples the signal at
the timing of
for maximum SNR. However, we can notice
that, from the crosstalk pulse response in Fig. 1(b), the
is received before
. Therefore, the sampled signal is not
available when the
disturbs the transition timing in the
adjacent channel and a XTC implementation with FIR taps in
the receiver becomes ineffective. A transversal FIR filter that
uses continuous-time analog delay, may be used instead of a
sample-data FIR filter to avoid the issues of the availability of
sampled signals from adjacent channels and fractional taps.
Besides, adding additional taps at the transmitter to generate
the crosstalk cancellation signal in addition to the pre-emphasis, reduces the overall output swing of the transmitter and
decreases the absolute value of the vertical eye-opening of the
received signal [11].
C. Single-Ended Versus Differential Signaling
The power spectrum of a NRZ signal coupled to an adjacent
channel can be expressed as
(3)
which is the product of the FEXT channel transfer
, and the NRZ data spectrum,
function,
. The power spectra of a 2-Gb/s
and a 5-Gb/s NRZ signal and the FEXT channel transfer
functions when
is
, have been measured and are shown
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011
Fig. 4. (a) 2-5 Gb/s NRZ spectrum and FEXT transfer function. (b) Coupled NRZ spectrum.
Fig. 5. Differential I/Os.
in Fig. 4(a). A PCB trace with a length of 16 inches, channel
width of 120 mils and channel height of 62.5 mils was used for
this set of measurements. The left-hand axis shows the units
for the NRZ spectrum in dBm, while the right-hand sides shows
the scattering parameters ( ) for the FEXT transfer function.
Notice that, as the data rates increase, a larger portion of the
signal energy moves towards frequencies where crosstalk has a
higher gain, allowing more NRZ signal energy to be coupled
to the adjacent channel as crosstalk. The power spectrum of
the NRZ signal coupled to an adjacent channel is shown in the
Fig. 4(b), i.e., this is the FEXT signal we wish to cancel.
These measurements suggest that to maximize the throughput
and at the same time to avoid crosstalk degradation, data should
be distributed over a large number of parallel lines operating
at lower speeds ( 2 Gb/s) where the crosstalk strength is minimal. Traditionally, most CPU-to-memory interfaces follow this
guidance. However, the overall throughput in this case is limited
by the number of channels, I/O pins, lower speed, and available
PCB area. An alternate choice is to run the system at a higher
speed utilizing differential signaling, which is less susceptible
to crosstalk. Nevertheless, low signal gain and long ISI tails of
the received NRZ signals place challenging design constraints
on the clock and data recovery circuits. Also, the additional
power necessary for the I/O makes the differential solution less
attractive.
It is instructive to derive the crosstalk equations for differential I/Os as well. Fig. 5 shows all the necessary physical parameters we will use to describe the coupled crosstalk signal. Here,
is the ratio of the distance between the differential pair to the
channel width. The bandwidth of the differential channel and
the characteristic impedance reduces for a small , while the
shielding effect provided by the wave guide declines and the
channel has a reduced common-mode rejection ratio (CMRR)
benefit for a large . A typical range for
is 1-1.5 [17]. Here,
is the distance between the two differential pairs. The aggressor signal
is applied at the differential input nodes
and the output signal at the adjacent differential channels receives the FEXT signals,
and
. As discussed earlier, the inductive crosstalk coupling component is
dominant in most micro-strip lines. Each differential output contains a superposition of the inductively coupled signals originated from
and
. Using (1),
and
can be expressed as
(4)
(5)
is usually larger than
for differential I/Os for better
crosstalk rejection. Expanding
and
, for
, the FEXT
signals seen at the differential output node is
(6)
This equation illustrates three important features of differential signaling. First, contrary to single-ended I/Os, the crosstalk
signal in differential I/Os has a positive polarity even though
each single channel is inductively coupled. Second, as the distance between the single differential pair
decreases, the
OH AND HARJANI: A 6-GB/S MIMO CROSSTALK CANCELLATION SCHEME FOR HIGH-SPEED I/OS
Fig. 6. 2
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2 MIMO-XTC architecture.
FEXT diminishes due to the increased shielding effect. However, this can only be achieved at the cost of reduced channel
bandwidth and reduced characteristic impedance. Finally, assuming that
in (1) equals
in (6), the modulus for differential crosstalk is lower than for the single-ended case by a
factor of
because of the shielding effect just described. Intuitively, the coupled signals of two differential aggressors with slightly skewed distances cancel each other in the
adjacent channel. The value of
depends on the board type
[see (1)]. In case of the channels presented in [11] and [16],
equals 1 and the crosstalk strength in differential I/Os decreases
proportional to
, whereas the crosstalk in a single-ended
channel decreases by
. In other words, differential I/Os
are more immune to crosstalk degradation than single-ended
I/Os at higher data rates. In addition, differential I/O circuits
have a better power supply rejection ratio (PSRR). However,
the MIMO-XTC scheme presented here minimizes the crosstalk
in single-ended I/Os allowing reductions in transmitter driver
power, I/O pin count and channel PCB area, provided the other
system constraints, such as PSRR, allow for this change.
Fig. 7. Bandwidth improvement by MIMO signals.
the gain is correctly adjusted to
term in the resultant matrix of
, it forces the nondiagonal
III. MIMO-XTC ARCHITECTURE
Our approach utilizes a continuous-time receiver-side
crosstalk cancellation scheme that is applicable to single-ended
I/Os. The proposed algorithm is shown in Fig. 6.
and
are the frequency-domain representations of the transmitted signals
on channels 1 and 2.
is
the channel transfer function and
is the FEXT. As
stated earlier, the FEXT is the negative derivative of channel
transfer function multiplied by
[see (1)]. The received
signals
and
contain both the primary signal with
the channel ISI and the FEXT of the adjacent channel signal.
The behavior of this two-channel system can be expressed in
matrix form as
(8)
to become zero and the crosstalk is cancelled out. At this point,
the equalized signals does not include the adjacent channel’s
signal component, and hence the two channels become independent as shown in
(7)
(9)
,
are added
In our algorithm, the received signals
to the adjacent channel’s received signal after differentiation
and with an appropriate value for the gain term . When
, where
is a primary signal path gain. An addiwhen
tional term,
, is now present in the diagonal terms.
This second derivative of the signal boosts the high frequency
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Fig. 8. 2
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011
2 MIMO crosstalk cancellation circuit implementation for single-ended I/Os.
signal content by
and works against the channel loss in
. This additional signal (MIMO signal) is normally lost
in previous schemes since the crosstalk is only considered as a
noise component to be cancelled out. In our MIMO algorithm,
the crosstalk signal energy is reutilized to reduce the jitter and
increase the vertical eye opening while mitigating the ISI tails.
When we differentiate the received signal, both the crosstalk
cancellation signal and a MIMO signal for the adjacent channel
are obtained. For clarity purposes, the signal path without differentiation is designated as the primary FEXT signal path and
the path with differentiation as the MIMO-XTC signal path, as
indicated in Fig. 6.
A continuous-time high-frequency boosting analog equalizer
stage follows the architecture to compensate for any remaining
ISI. In our test setup, the analog equalizer only compensates for
a small part of the channel ISI. In channels with large crosstalk
the MIMO boosting can significantly ease the burden on any
follow-on channel equalizer. It reduces both the number of
stages used in analog equalizers and the number of taps that may
be used in a decision feedback equalizer. Fig. 7 shows the frequency-domain impact of MIMO-XTC for various strengths of
the MIMO signal (
15 ps,
23 ps). We note that for channels with increased crosstalk degradation, the MIMO crosstalk
cancellation scheme results in a larger bandwidth improvement.
This implies that high-quality signal integrity can be achieved
even in severe crosstalk environments where the crosstalk completely closes the horizontal and vertical eye-opening. However,
it is important to discuss three fine points here. First, an increased
cannot be used to substitute for channel equalization for ISI
as they operate on different signals. Second, wireline channels
tend to be crosstalk and ISI dominant (by over 20 dB); thus,
increasing the high-frequency response does not degrade SNR
significantly but improves signal-to-distortion ratios. Third,
in the presence of per-pin de-skew scheme, the primary signal
and coupled FEXT signal will not align perfectly, as depicted
in Fig. 2. The FEXT and its cancellation signal or primary and
MIMO signal will be skewed even with an optimal value and
degrades some of the benefits of both crosstalk cancellation and
MIMO improvement discussed here. However, the degradation
is limited and is affected by where the majority of the skew is
accumulated in the channel. Further details about per-pin skew
are discussed in Section V.
IV. 2
2 MIMO-XTC PROTOTYPE IMPLEMENTATION
A 5-Gb/s prototype circuit for the proposed 2 2
MIMO-XTC scheme for single-ended I/Os has been
implemented in a 130 nm CMOS technology using passive differentiators, 180 phase shifters, pseudo-differential
pairs and analog equalizers as shown in Fig. 8. Replica circuits
OH AND HARJANI: A 6-GB/S MIMO CROSSTALK CANCELLATION SCHEME FOR HIGH-SPEED I/OS
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Fig. 9. Input network performance in the frequency domain. (a) Input network for primary FEXT and MIMO XTC signal path. (b) Frequency responses. (c)
amplitude from IC prototype.
Measured
for the differentiators and the 180 phase shifters are added to
corresponding stages of each path to equalize phase delays.
Fig. 9(a) and (b) shows the passive input network and its magnitude and phase response. The continuous-time capacitor-resistor (CR) filter for implementing the differentiator enables a
low power and low area design. The transfer function of the CR
, now differs from the
passive differentiator,
, by a factor of exactly
and
replica circuit’s,
the relation between two paths is only a differentiator. As shown
in Fig. 4(a) and (b), a 5-Gb/s NRZ signal and its FEXT frequency corner are around 2.5 GHz, so the low-pass RC replica
with a pole at 10 GHz does not affect the gain of the primary
value needs to be sufficiently large to
signal path. The
ensure that the pole of the replica does not reduce the signal
of interest. However, the MIMO-XTC signal gain is directly
proportional to the RC value to the first order, therefore
cannot be too large. In this design, the magnitude loss due to
the RC filter at 10 GHz on the signal frequency at 2.5 GHz
dB. The location of this
is
pole frequency is chosen, considering the trade-off between the
MIMO-XTC signal gain and the replica circuit’s pole. Tuning
resistors can adjust the pole frequency and reduce any mismatch
due to process variation of the RC constant between the differentiator and its replica circuit.
Circuit phase delays of the primary FEXT signal path
and MIMO-XTC signal path from two receiver inputs to an
analog equalizer input, are matched to 90 difference in our
MIMO-XTC scheme as stated earlier. Any per-pin skew would
detract from this matched case. However, for the prototype we
assume matched channel paths. Results for per-pin de-skew
degradation are presented in Section V. For a broadband
50- receiver input matching, the passive RC-CR network
impedance ( ) should have a large value, as indicated in
Fig. 9(a). In our case, the impedance
is approximately
and the measured input
remains below 15 dB
for the signals of interest up to 2.5 GHz as can be seen in
Fig. 9(c).
The primary FEXT and MIMO-XTC path’s signals are combined after differentiation and the remaining ISI can be removed
by the follow-on analog equalizer, as shown in Fig. 6. The combination of the adder and the analog equalizer is required to
have two features. First, since the original signal from the lossy
channel and the FEXT signal coupled from the adjacent channel
passes through the primary FEXT signal path and are random
and uncorrelated, the adder should have a large input swing,
500 mV . Second, the received single-ended signal needs
to be converted to a differential signal for improved PSRR at
some point.
Fig. 10 shows a couple of potential circuit combinations for
the high-speed signal adder plus analog equalizer. In the circuit
of Fig. 10(a), a current domain adder with a skewed gain control
combines the signals from the two paths and single-to-differential conversion is achieved by a passive low-pass filter at
the analog equalizer input with the penalty of 6-dB gain loss.
A difference between the primary signal-side amplifier and
XTC signal-side amplifier gain of 10 dB can cover a wide
distance. The primary FEXT
range of FEXT strengths for
signal-side amplifier’s gain only needs to avoid signal loss. The
output swing at the summing node of the first stage is dropped
to satisfy these demands, narrowing the output swing and limiting the dynamic range through the gain control. The circuit in
Fig. 10(b) circumvents this issue by adding pseudo-differential
circuits. A 180 phase shifter flips the sign of either the primary
FEXT signal path or the MIMO XTC signal path. The FEXT
signal and its cancellation signal appear as a common-mode
signal and is suppressed by the CMRR of the differential analog
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Fig. 10. Signal adder plus analog equalizer circuit design options. (a) Current domain adder + Analog equalizer. (b) Pseudo-differential pair + Analog equalizer.
Fig. 12. Die photograph.
Fig. 11. Simulated analog equalizer frequency response.
equalizers that follow. Although the 180 phase shifter and
its replica circuit result in approximately 6-dB loss, the gain
control amplifiers of the two paths now drive separate loads and
dynamic range need not be traded off. The ordering of the phase
shifter stage and pseudo-differential gain control stage can be
switched. With the arrangement in Fig. 10(b), the gain control
amplifier has lower input signal swing and operates in a more
linear region. The analog equalizers that follow both eliminate
the common-mode FEXT signal and boost the high-frequency
signals to remove the residual ISI. The frequency-dependent
gain equation is shown in [18]
(10)
The frequency for the zero,
is calibrated by
and
depending on both the channel loss and the
changing
distance,
necessary MIMO high-frequency boosting. For
the majority of the high-frequency loss is compensated by the
MIMO signals and the burden of high-frequency boosting in the
following stages can be significantly reduced. Fig. 11 shows the
simulated frequency response of the analog equalizer including
variations of
and
[19]. Instead of a varactor,
can
be implemented by a capacitor with a fixed minimum value or
a parasitic capacitance of the source for a higher zero at the
expense of a degree of freedom for calibration, making both
the zero frequency and the dc gain dependent only on the
value [20].
The prototype 2 2 MIMO-XTC circuit occupies 0.03 mm
and the die photograph is shown in Fig. 12. The physical conditions of channels 1 and 2 are expected to be symmetric, and,
therefore, the output results of channels 1 and 2 are normally
identical. In our prototype implementation, we have added two
additional analog equalizer stages in channel 2 to increase the
flexibility of our prototype so that we are able to handle both
low-loss and high-loss channels optimally. For our particular
test conditions, a single stage of the analog equalizer in channel
1 was sufficient to compensate for the residual ISI after the
high-frequency boosting due to the MIMO signal was included.
distance and
The MIMO-XTC circuit draws 11.3 mA at
distance from 1.2 V supply regardless of signal
14.3 mA at
speed. The magnitude of the FEXT depends mostly on the distance rather than on the data rate and the gain of the pseudodifferential amplifier need only be adjusted according to the
channel distance. The analog equalizer consumes 5.3 mA.
OH AND HARJANI: A 6-GB/S MIMO CROSSTALK CANCELLATION SCHEME FOR HIGH-SPEED I/OS
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Fig. 13. Calibrating FEXT cancellation gain and MIMO improvement (100 mV,100 ps/division).
V. MEASUREMENT RESULTS
A. 2
2 MIMO-XTC Gain Calibration – Single Input Signal
The receiver proposed in Fig. 8 has been implemented and
measured in a single-ended I/O environment. A 16-in FR4 board
with a channel loss of 9 dB at 2.5 GHz is used for this test. A
Centellax TG2P1A PRBS of pattern length
generates a
random NRZ signal on a single-ended channel, and the signal
at the receiver output is measured by an Infiniium DSO81204A
oscilloscope. The FEXT cancellation and MIMO improvement
were directly observed in our test setup after proper termination
and equalization. By transmitting a single NRZ signal onto either the channel 2 or the channel 1 input, FEXT cancellation or
MIMO improvement operation can be seen separately, as shown
in the test setup in Fig. 13 and only the measured output at the
channel 1 was used for both cases. A 5-Gb/s NRZ signal and
FR4 channels with
distance were used in this calibration
example.
When the input to channel 1 is off and only channel 2 is on,
then path A contains the crosstalk coupled to the channel 1 receiver. Path B is the crosstalk cancellation signal derived from
the received signals from channel 2. When the gain of the two
paths is adjusted correctly, the output of path A plus path B will
ideally have no signal. Their eye-diagrams are presented in the
Fig. 13. The gain of the pseudo-differential pair has a 3-bit resolution and was manually optimized to result in a minimum
amplitude for the sum of these two signals (path A and path
B). Fig. 14 shows the residual FEXT energy depending on the
gain control value. Both over cancellation and under cancellation increase the residual FEXT level and degrades SNR. In this
test the data rate is 5 Gb/s and channel distance is
. For this
channel condition, the pseudo-differential gain control of
results in the minimum achievable value for the residual error
mV . The value of the residual FEXT has a maximum
at the data transition and minimum at the center of the data eye.
The residual FEXT normally occurs at the data transition timing
and detracts minimally from the data eye center.
With a gain value that minimizes the residual FEXT, the
MIMO bandwidth improvement was observed in the path C
and path D in Fig. 13. The path C includes the original signal
with channel ISI. Path D has the second derivative signal that is
coupled to the adjacent channel as crosstalk and returns through
the differentiation path in our algorithm. When the signals from
these two paths are added, the MIMO signal reduces the jitter
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Fig. 14. Pulse response of residual FEXT depending on gain control ( ). (a) Gain control and residual FEXT. (b) Optimal gain control point.
B. 2 2 MIMO XTC Measurement Results—Two Independent
Input Signals
Fig. 15. Measurement results for 2,5,6 Gb/s NRZ signals in
and
distances (left-side graphs: 200 mV, 100 ps/division, right-side graphs: 100 mV,
) diatance. (b) 2 Gbps 240 mil (
)
100 ps/division). (a) 2 Gbps 360 mil (
) distance. (d) 5 Gbps 240 mil (
) distance.
distance. (c) 5 Gbps 360 mil (
) distance.
(e) 6 Gbps 360 mil (
horizontally and increases the data eye-opening vertically by
mitigating channel ISI, as shown in the eye-diagram of path C
plus path D in Fig. 13. The parameters for the follow on analog
equalizer was set to remove any residual ISI. This calibration
procedure could be done in parallel for each pair of channels.
During the calibration phase discussed above, only one
signal was used. In the measurements of this section, two
independent NRZ signals on channel 1 and channel 2 are
transmitted and the eye-diagrams of the received signals with
crosstalk (before MIMO-XTC) and the equalized signals (after
MIMO-XTC) have been measured for the channel distances of
and
for different data rates, as shown in Fig. 15. To
observe the FEXT degradation by varying the degree of ISI,
eye-diagrams with various data rates (2,5,6 Gb/s) are measured.
As the channel distance reduces and the signal frequency
increases, the FEXT impact becomes more severe and closes
the eye completely, as shown in Fig. 15(d) and (e). In the pulse
response of NRZ signals with higher data rates, the main tap
( ) is lower and ISI tails (
) have longer duration
and higher amplitude as explained in Section II-B. The data
eyes are more susceptible to FEXT degradation because of the
reduced vertical data eye-opening. For example, the vertical
and horizontal eye openings with the 5 Gb/s NRZ signal for
distance is 60 mV/821 mV (7.3%) and 30 ps/200 ps (15%UI).
For the same condition, by using our MIMO crosstalk cancellation scheme, the
reduces by 67% and the vertical
eye-opening increases by 58.2%.
Table I shows a summary of the measurement results before
and after MIMO-XTC for various channel distances and data
rates. Here,
is the jitter,
is the vertical eye-opening at
the center (
) and
is
the overall height of data eye (
). These are
indicated in Fig. 15(c). The case of a 6-Gb/s NRZ signal with
distance is not presented because the gain of the pseudodifferential pair in our scheme was not sufficient to generate
an adequate crosstalk cancellation signal at this frequency. At
2 Gb/s, MIMO-XTC has more impact on jitter reduction rather
than increasing the eye-opening because the crosstalk degrades
only the data transition timing and not the vertical eye-opening
at this low frequency.
An issue which needs discussion with any FEXT cancellation scheme is transmitter per-pin de-skew that adjusts timing
OH AND HARJANI: A 6-GB/S MIMO CROSSTALK CANCELLATION SCHEME FOR HIGH-SPEED I/OS
TABLE I
MEASUREMENT RESULTS (BEFORE AND AFTER MIMO-XTC)
of signal in channels with unequal lengths. A length mismatch
physically close to the transmitter outputs has a limited effect
because the coupled signal will align with the original signal
at the end of the channel. However, a length mismatch near
the receiver input directly skews timing of the crosstalks, reducing both jitter margin and vertical eye-opening even after
XTC. In general, skew mismatch is likely to be distributed over
the channel and its effect will lie somewhere between being
placed at the transmitter end or at the receiver end. In Table II,
we have assumed that all the per-pin skew, due to length mismatch, is lumped at the receiver input (i.e., worst case that is unlikely), and show the simulation results of performance degradation for the proposed MIMO-XTC scheme. In Fig. 2,
is
the amount of timing skew. As an approximate rule of thumb, a
quarter inch mismatch at the receiver input is expected to skew
the timing between the received signals by 40 ps. As we can see
from the table, that even though there is progressively larger
impact due to per-pin skew, the proposed MIMO-XTC scheme
still performs relatively well even at a quarter inch mismatch.
Prior crosstalk cancellation techniques have been implemented at the receiver end or at the transmitter end for various
channel conditions and data rates. Table III shows a comparison
of the MIMO-XTC technique to prior schemes. Differential
signaling is used for [7] and [11]. In [10] staggered I/O cancellation is realized using both the transmitter and receiver. The
MIMO-XTC technique achieves the best eye-performance improvement with the lowest power consumption. As technology
scaling advances, the corner bandwidth of the MIMO-XTC
schemes will need to increase further but should be equally
effective for higher frequency.
The proposed continuous-time MIMO FEXT cancellation
scheme has three advantages over the previous discrete time
digital schemes [7], [10], [11]. First, the simple CR differentiator and wideband pseudo-differential amplifiers generate the
crosstalk cancellation signal with low power, while discrete
time schemes normally require several high-speed fractional
taps that consume significant power. Second, the simple circuit
implementation allows for low chip area compared to prior
architectures [10], [11]. The MIMO FEXT cancellation block
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TABLE II
SIMULATED PERFORMANCE DEGRADATION OF THE PROPOSED MIMO-XTC
SCHEME DUE TO PER-PIN SKEW (LINE LENGTH 16 IN, WIDTH 120 MIL, HEIGHT
62.5 MIL, DISTANCE
, 5 GB/S NRZ SIGNAL)
spans only two stages for single-ended I/Os and one stage
for differential I/Os. Third, as the spacing between channels
reduces, the signal integrity improves due to the additional
high-frequency boosting from the MIMO signal energy that is
available for reuse. Operation with extremely narrow channel
distances, where the FEXT completely closes the eye-opening
as shown in Fig. 15(d) and (e), can be achieved. The additional
bandwidth improvement eases the burden on the following
ISI equalizer. In conclusion, we can both save board area
and increase signal integrity at higher data rates by using
MIMO-XTC.
VI. CONCLUSION
This paper presents an efficient continuous-time architecture
to cancel and reutilize the crosstalk signal energy to improve
SNR of NRZ signals. Slight modifications of this scheme are
applicable to environments where the unwanted crosstalk signal
is proportional to the first order derivative i.e., pad-to-pad and
pin-to-pin coupling [21]. The measurement results show the validity of the MIMO-XTC algorithm and efficiency of the continuous-time XTC scheme. The MIMO-XTC portion consumes
low power (2.8 mW/Gbps/lane) and low area (0.03 mm ). For
the prototype 2 2 MIMO-XTC scheme, the
reduces
by 67% UI and the vertical eye-opening improves by 58.2% at 5
Gb/s, which to the best of our knowledge is the highest performance improvement for any crosstalk cancellation technique.
Due to the crosstalk, single-ended I/Os have slowly been loosing
ground to differential I/Os as the go-to technology for high performance. However, single-ended I/Os with MIMO-XTC maintains the I/O pin, pads, and power advantages of single-ended
designs but allows for speeds that are comparable to differential I/Os although PSRR considerations may require converting
the single-ended signals to differential signals within the chip
as early as possible. In comparison to low-speed single-ended
I/Os, MIMO-XTC enhanced single-ended I/Os allow for closer
channel spacing resulting in further board area savings. Finally,
in addition to the crosstalk cancellation aspects of MIMO-XTC,
the MIMO signal improves the SNR and reduces the burden on
follow on equalization circuits.
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COMPARISON
OF
TABLE III
FEXT CANCELLATION SCHEMES.
Fig. 16. Noise simulation setup in a severe crosstalk environment. (a) A conventional analog equalizer scheme. (b) A MIMO-XTC scheme.
APPENDIX
Noise Analysis: Here, we compare the noise performance
of a conventional analog equalizer and the MIMO-XTC scheme.
Fig. 16 shows the noise simulation setup for the two schemes.
For this simulation we assume that four independent random
,
,
,
) at the transmitter outputs
noise sources (
and at the receiver inputs degrade SNR. The signal, crosstalk
and noise energy at points A, B, C and D are summarized in
Fig. 17. The simulation test setup used for these results are:
800 mV
NRZ signal operating at 5 Gb/s at the transmitter
output, 16-in channel length, 120-mils width, 62.5-mils height,
and 240-mils separation between channels. These are similar to
the measured responses shown in Fig. 15(d).
In this crosstalk dominant channels, a conventional analog
equalizer scheme is designed for comparison purposes, as
OH AND HARJANI: A 6-GB/S MIMO CROSSTALK CANCELLATION SCHEME FOR HIGH-SPEED I/OS
Fig. 17. Signal, crosstalk and noise energy (mV
) and BER performance.
shown in Fig. 16(a). The gain and pole location in
are set to result in an equivalent signal swing as the MIMO-XTC
scheme in Fig. 16(b) and thus
Note that the signal energy at points C and D in Fig. 17 is
matched as 311 mV . The corner frequency used for simulation purposes ( ) is 1 THz. The output signal and crosstalk
are
for channel 1 and
for channel 2. The crosstalk energy is
and increases from 163 mV
to 182
amplified by
mV
as shown in Fig. 17.
The noise at the receiver input [point B in Fig. 16(a)],
considering coupling, can be expressed as
for channel 1 and
for channel 2. When the noise passes through
a conventional analog equalizer system, the output noise
(
) is
We can see that the noise at the transmitter outputs does not
appear in the adjacent channel though the channels are coupled. The MIMO-XTC scheme cancels the coupled noise between channels, which looks similar to crosstalk cancellation
process. However, the noise component from the receiver input
in an adjacent channel is coupled through the differentiator and
increases the overall noise level. In Fig. 17, the noise energy
at point D increases from 5.5 mV
to 16 mV
due to the
additional noise from the adjacent channel receiver input noise.
As expected, the MIMO-XTC scheme has a noise penalty in
comparison to the conventional analog equalizer. However, the
residual crosstalk in the conventional analog equalizer scheme
significantly degrades SNDR in this severe crosstalk environment and therefore, the overall noise plus crosstalk is considerably smaller for MIMO-XTC. The BER can be evaluated by
considering the eye-opening [E,H in Fig. 15(c)] and noise standard deviation (
) at each point, as analyzed in [22]
(13)
,
The BERs at point B, C and D are approximately
and
. For this simulation, the noise bandwidth for
the sources
,
,
and
was limited to 100 GHz
[22] and a standard deviation of 5 mV
was used [23]. Fig. 17
shows the noise and signal energies at A, B, C and D in Fig. 16.
The noise and signal powers at each point has been estimated in
mV
by numerically evaluating the following:
• Point A
(11)
The output signal for MIMO-XTC, which can be obtained by
appending an analog equalizer stage to (9), is
for both channels. Here,
is the transmitted signal. The crosstalk component is cancelled
and reused as a MIMO signal in our MIMO-XTC. The signal
energy at point D in Fig. 16(b) includes this beneficial MIMO
energy. On the other hand, the noise component
at point D
can be expressed as
(12)
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• Point B
• Point C
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011
• Point D
ACKNOWLEDGMENT
The authors would like to thank F. O’Mahony, B. Casper, and
others at Intel Circuits Research Laboratory, M. R. Ahmadi at
AMD, and B. Hardy at LSI for technical help with this project.
The authors would also like to thank the anonymous reviewers
for their constructive comments and feedback.
REFERENCES
-spaced FFE in 65 nm
[1] A. Momtaz et al., “An 80 mW 40 Gb/s 7-tap
CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 364–365.
[2] H. Wang et al., “A 21-Gb/s 87-mW transceiver with FFE/DFE/analog
equalizer in 65-nm CMOS technology,” IEEE J. Solid-State Circuits,
vol. 45, no. 4, pp. 909–920, Apr. 2010.
[3] J. Lee et al., “A 20 Gb/s full-rate linear CDR circuit with automatic
frequency acquisition,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2009,
pp. 366–367.
[4] K.-C. Wu et al., “A 2 25 Gb/s deserializer with 2:5 DMUX for 100
Gb/s Ethernet applications,” in IEEE ISSCC Dig. Tech. Papers, Feb.
2010, pp. 374–375.
[5] S. A. Ibrahim et al., “A 20 Gb/s 40 mW equalizer in 90 nm CMOS technology,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 170–171.
[6] C.-F. Liao et al., “A 40 Gb/s CMOS serial-link receiver with adaptive
equalization and clock/data recovery,” IEEE J. Solid-State Circuits,
vol. 43, no. 11, pp. 2492–2502, Nov. 2008.
[7] J. F. Buckwalter et al., “Cancellation of crosstalk-induced jitter,” IEEE
J. Solid-State Circuits, vol. 41, no. 3, pp. 621–631, Mar. 2006.
[8] H.-K. Jung et al., “A 4 Gb/s 3-bit parallel transmitter with the crosstalkinduced jitter compensation using Tx data timing control,” IEEE J.
Solid-State Circuits, vol. 44, no. 11, pp. 2891–2900, Nov. 2009.
[9] K.-J. Sham et al., “I/O staggering for low-power jitter reduction,” in
Proc. Eur. Microwave Conf., Aug. 2008, pp. 1226–1229.
[10] K.-I. Oh et al., “A 5-Gb/s/pin transceiver for DDR memory interface
with a crosstalk suppression scheme,” in Proc. IEEE CICC, Sep. 2008,
pp. 639–642.
[11] K.-J. Sham et al., “FEXT crosstalk cancellation for high-speed serial
link design,” in Proc. IEEE CICC, Sep. 2006, pp. 405–408.
[12] C. Pelard et al., “Realization of multigigabit channel equalization and
crosstalk cancellation integrated circuits,” IEEE J. Solid-State Circuits,
vol. 39, no. 10, pp. 1659–1669, Oct. 2004.
[13] Y. Hur et al., “Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections,”
IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 246–255, Jan. 2005.
[14] G. Balamurugan et al., “A scalable 5–15 Gbps, 14–75 mW low-power
I/O transceiver in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43,
no. 4, pp. 1010–1019, Apr. 2008.
[15] F. D. Mbairi et al., “High-frequency transmission lines crosstalk reduction using spacing rules,” IEEE Trans. Compon. Pacakg. Technol.,
pp. 601–610, Sep. 2008.
[16] W. R. Eisenstadt et al., “Common and differential crosstalk characterization on the silicon substrate,” IEEE Microw. Guided Wave Lett., vol.
9, no. 1, pp. 25–27, Jan. 1999.
[17] “DDR2-533 memory design guide for two-dimm unbuffered systems,”
Micron, Tech. Note, 2003, p. 14.
[18] M. R. Ahmadi et al., “A 5 Gbps 0.13 m CMOS pilot-based clock
and data recovery scheme for high-speed links,” IEEE J. Solid-State
Circuits, vol. 45, no. 8, pp. 1533–1541, Aug. 2010.
[19] J.-S. Choi et al., “A 0.18- m CMOS 3.5-Gb/s continuous-time
adaptive cable equalizer using enhanced low-frequency gain control
method,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 419–425,
Mar. 2004.
[20] K. Fukuda et al., “A 12.3 mW 12.5 Gb/s complete transceiver in 65 nm
CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 368–369.
[21] C. Pfeil, “BGA breakout challenges,” PCB Fabrication Mag., pp.
10–13, Oct. 2007.
[22] S. Gondi et al., “Equalization and clock and data recovery techniques
for 10-Gb/s CMOS serial-link receivers,” IEEE J. Solid-State Circuits,
vol. 42, no. 9, pp. 1999–2011, Sep. 2007.
[23] B. K. Casper et al., “An accurate and efficient analysis method for
multi-Gb/s chip-to-chip signaling schemes,” in VLSI Circuits Dig.
Tech. Papers, Jan. 2002, pp. 54–57.
Taehyoun Oh (S’05) received the B.S. and M.S. degrees in electrical engineering from Seoul National
University, Seoul, Korea, in 2005 and 2007, respectively. He is currently working toward the Ph.D. degree in electrical engineering from the University of
Minnesota, Minneapolis, under the supervision of Dr.
R. Harjani.
His research is focused on high-speed I/O circuits
and architectures. During the summer of 2010, he
worked on I/O channel modeling and transmitter
equalization at AMD Boston Design Center, MA.
Ramesh Harjani (S’87–M’89–SM’00–F05) received the B.S. degree from the Birla Institute of
Technology and Science, Pilani, in 1982, the M.S.
degree from the Indian Institute of Technology, New
Delhi, in 1984, and the Ph.D. degree from Carnegie
Mellon University, Pittsburgh, PA, in 1989, all in
electrical engineering.
He is the Edgar F. Johnson Professor with the
Department of Electrical and Computer Engineering
and a Member of the graduate faculty of the Department of Biomedical Engineering, University of
Minnesota, Minneapolis. Prior to joining the University of Minnesota, he was
with Mentor Graphics Corporation, San Jose, CA. He cofounded Bermai, Inc., a
startup company developing CMOS chips for wireless multimedia applications
in 2001. He has been a Visiting Professor with Lucent Bell Labs, Allentown,
PA, and the Army Research Labs, Adelphi, MD. He is an author/editor of four
books. His research interests include analog/RF circuits for wired and wireless
communications.
Dr. Harjani was the recipient of the National Science Foundation Research
Initiation Award in 1991 and Best Paper Awards at the 1987 IEEE/ACM Design Automation Conference, the 1989 International Conference on ComputerAided Design, the 1998 GOMAC and the 2007 TECHCON. His research group
was the winner of the SRC Copper Design Challenge in 2000 and the winner
of the SRC SiGe challenge in 2003. He was an associate editor for the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS II from 1995 to 1997 and guest editor for the International Journal of High-Speed Electronics and Systems and
Analog Integrated Circuits and Signal Processing in 2004 and is currently a
guest editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He was the Chair
of the IEEE Circuits and Systems Society technical committee on Analog Signal
Processing from 1999 to 2000 and a Distinguished Lecturer of the IEEE Circuits
and Systems Society for 2001-2002.