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HighlLevel S m e s i s
High-level synthesis has received
much attention lately, mainly because it helps to cope with the ever
growing complexity of digital systems. High-level specifications are
in general shorter than lower level
ones, easier to generate and to understand,less error prone,and faster
to simulate. High-level synthesis
bridges the gap between such specifications and their implementation
in hardware, automatically generating a lower level description that is
suitable for other design-automation tools, such a s logic synthesis
and layout.
VHDL, short for The VHSIC (Very
High Speed IC) Hardware Description Language, is a formal notation
for hardware description, standardized by the IEEE in 1987,’ that allows the high-level description of
digital systems. High-level synthesis
from VHDL combines the advantages of a standard with the advantages inherent in high-level synthesis.
What is high-level
Synthesis?
Although high-level synthesis has
been used to define different design
MARCH 199 1
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I B M Research Division
L.F. SAUNDERS
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IBM General Technology Division
tasks,lately the scope of its meaning has
narrowed considerably “From Behavior
to Structure: High-Level Synthesis”’ defines it as the synthesis of a hardware
0740-7475/91/0W3-0~/$01
.OOO 1991 IEEE
structure from a behavioral description. Unlike logic synthesis,
which optimizes only combinational logic, high-level synthesis
also deals with memory elements
and the interconnection structure,
including buses and multiplexers.
As in most approaches, we assume
here that behavior is specified
using a sequential (procedural)
language,such as behavioral VHDL.
The hardware structure is usually
given by something like a netlist.
Many approaches to high-level
synthesis exist, and the tutorial just
mentioned is a good overview for
those unfamiliar with the topic.The
approach we take here is inspired
mainly by the high-level synthesis
approach taken by those who d e
veloped the Yorktown Silicon Compiler.3 Several common restrictions
imposed in the YSC make highlevel synthesis considerably easier.
The three main restrictions, which
also seem appropriate for synthesis
from VHDL,are
1. Only synchronous hardware is
synthesized.
That is, there are no feedback loops in
combinational logic,time is divided into
so-called control steps,and registers are
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loaded at most o n c e during o n e control
step.
2. High-level synthesis produces one
finite state machine for control for
each process and subprogram in the
specification.
High-level synthesis additionally obtains
parallelism in t h e data path by activating an arbitrary number of functional
units in a given control step (a state of
the controlling state machine). Users
may also want to specify concurrency a
higher level by hand, which they can
easily do by specifying a collection of
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concurrent processes. An example
would be a pipeline, which must be designed by exactly specifying the boundaries between each pipe stage and the
global control that takes care of such
things as interrupts and exceptions.
3. The behavioral specification is
given as an algorithm written in a sequential language, such as behavioral VHDL or C.
High-level synthesis does not change
this algorithm. In particular, high-level
synthesis will keep the ordering implied
by the data dependencies in the program and the basic loop structure. For
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example, the YSC will not automatically
convert a bubble sort into a quick sort.
This does not mean, however, that it
could not unfold simple loops,move operations out of loops, or replicate variables that could not share common registers.
We are not saying that these restrictions
are in heren t to high-level synt hesis-i n
fact, research is continuing in each of
these areas-but the state of the art is
not advanced enough to allow a practical general-purpose synthesis system
that does not impose these restrictions.
Using VHDL
Figure 1. Example (incompletej of a VHDL model.
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A VHDL model consists basically of
entities and architectures. An entity defines the interface between a design
and its envir0nment.h is specified in the
structural domain, essentially giving a
list of ports (inputs and outputs).
In the example in Figure 1,the entity e
has a bidirectional port, called bus, and
a n input port, called bus-ready An architecture specifies the relationships
between the inputs and outputs of a d e
sign entity It consists of declarations
and concurrent statements. Concurrent
statements execute asynchronously and
concurrently with respect to each other.
They include not only typical structuredefinition statements, such as component instantiation, and their interconnection, but also conditional signal
assignment as found in many hardware
description languages. In the example,
the architecture of entity e is called
arch. It contains only o n e concurrent
statement, namely the process p l .
Sequential statements included in
VHDL processes have the basic semantics of a sequential (procedural, imperative) programming language such as
Ada, C, or Pascal. The example includes
the typical loop, if-then else,and assignment (:=) constructs.A process can also
use procedures. For example,process p l
calls procedure read-bus. Notice that
IEEE DESIGN &TEST OF COMPUTERS
the signal a in Figure 2 , which is the
basic hardware structure described in
Figure 1, is drawn only for the sake of
clarity.Signal a will be eliminated during
optimization. A procedure is a sequential subprogram that can call other procedures as well. Recursion is allowed.
Processes are provided for describing
the behavior of a design.
Synthesis from concurrent VHDL is essentially register-transfer-leoelsynthesis.
RTL synthesis, which is the basic approach of silicon compilers such as
Genesi14 and Concorde: consists of
mapping VHDL operators to whatever
primitive components are permitted in
subsequent design tools, such a s logic
synthesis.
An example of a concurrent VHDL
synthesis system is the IBM VHDL synthesis ~ y s t e m .Although
~
other VHDL
synthesis systems d o
none allows the unrestricted use of the language.
Automatic synthesis of a design structure from a sequential VHDL process is
essen t ia 1ly high-levelsynthesis.AI t h ou gh
VHDL supports the development, verification, synthesis, and testing of hardware designs, according to the preface
of the reference manual,' we found certain difficulties for high-level synthesis.
Most of these have to d o with the modeling of time.Since a VHDL model can b e
simulated, time is well defined. For highlevel synthesis however,time is often not
specified o n purpose. Instead it is left to
the synthesis tool to determine when exactly a n operation will b e executed
(scheduling).
So there seems to b e a fundamental
problem. If time is not specified in a
VHDL model intended for synthesis, it
cannot b e simulated accurately, but if
the temporal behavior of the design is
specified in a way that allows us to simulate it exactly, synthesis may b e overconstrained. Fortunately VHDL gives us
the freedom to specify time with different accuracies: exact delays, delays in
multiples of a cycle time,or no delays at
MARCH 199 1
d1 but just the partial ordering of events
synchronization).
Sequential VHDL
5iukments
VHDL consists of the following seiuential statements: process communi:ation and synchronization, wait, signal
issignment,and variable assignment. We
ook at each of these in terms of their
iotential special problems for high-level
iynthesis.
Fortunately
V H D L gives
us the
freedom to
specify time
with different
accuracies.
Process communication
A process executes concurrently and
3synchronously with respect to other
:oncurrent statements, just a s any other
:oncurrent statement. As many concurrent processes can be defined a s are
ieeded.
A process executes in zero time unless
t encounters a wait statement used for
jynchronization. For example, the wait
Statement in procedure read-bus (Figure 1) synchronizes with the entity that
generates the signal bus-ready But this
characteristic of the process makes synthesis difficult, since hardware that e x e
cutes in zero time is impossible to synthesize. To solve this contradiction, we
impose the following, additional restriction on VHDL models:
The wait statement has the form
The sensitivity clause defines the set
Rule 1. Make n o implicit assumption
on the execution time of a process. To
ensure proper communication among
processes, either use explicit synchronization (such a s handshaking) or specify
appropriate delays using the wait statement.
We can interpret this rule as the following design rule: Communication
among asynchronous modules should
not be based on timing assumptions.
Since two asynchronous processes will
be implemented by two finite-state machines, if the processes communicate,
+=+
Bus-ready
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Figure 2. Basic hardware structure described in Figure I .
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V H D L signals
correspond to
actual design
signals and are
structural
elements that
can be used in
processes and
concurrent
statements.
of signals to which the wait statement is
sensitive. That is, execution continues if
any signal in the sensitivity list changes
(syntax: On G i g n a b ) .
In the example in Figures 3a and 3b,
procedure read-bus waits until signal
bus-ready changes, before assigning
bus to a.This leads to another restriction,
since a sensitivity list will detect edges
and the sequential synthesis of synchronous hardware uses only clock edges
(asynchronous hardware should be described in concurrent VHDL).
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Rule 2. Ignore sensitivity lists in sequential synthesis. Do not use them in
sequential processes.
The condition clause specifies a condition that must be met (evaluated as
true) to continue execution (syntax:
Until <condition>). In the example in
Figure 3a, procedure read-bus waits
until signal bus-ready is True before assigning bus. Condition clauses should
be used for synchronization, as Rule 1
requires.
The timeout clause causes the process
to be suspended until a timeout interval
has expired (syntax: For <time>). The
timeout interval is given in absolute
time,not in control steps.
An attribute can specify the cycle time.
In the example, the attribute cycle-time
of entity e is defined as 50 ns. Rule 3
specifies that all timing specifications
are converted to control steps (also
done in the After part of a signal-assignment statement and in the assert statement) Timeout clauses should b e used
for specifying delays,as Rule 1 requires.
Rule 3. Convert time expressions to
control steps and use them as design
constraints.
If procedure read-bus is being used to
load bus o n clock boundaries, then Fig-
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ure 3b gives the specification that simulates correctly
Signal assignment
A process communicates with its surrounding using signals. VHDL signals
correspond to actual design signals and
are structural elements that can be used
inside processes and in concurrent
statements. In VHDL, if multiple assignments apply to a signal, a resolution
mechanism defines the actual value of a
signal, The semantics of VHDL determine that signals assigned a value by a
process retain that value until they are
assigned a new one. In the general case,
this means that the signal must be
latched.
Exceptions to the latching requirement are signals generated by values
that are already latched or signals that
must never b e kept for more than o n e
control step. Detecting these exceptions,
however, may mean we have to analyze
the complete design, not just the process being synthesized. Consequently,
high-level synthesis may generate unnecessary output registers. We therefore
explicitly include the following rule to
make the designer aware of this fact:
(Determining in detail possible exceptions to this rule requires a n in-depth understanding of bus resolution and the
particular synthesis method, and so is
not covered here.)
For the example in Figure 1, this means
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Wait on bus-ready until bus-ready;
a(i) :=bus;
1-
Wait for 50 ns;
If bus-ready then a(i) := bus;
t-‘
End if;
la1
fb/
Figure 3. Example of a Wait statement. In [a),procedure read-bus waits until signal
bus-ready changes. In (b}, the process is suspended until a timeout interval has expired,
which in this case is 50 ns.
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Rule 4. In general, the synthesis system will latch those signals assigned values by a process (outputs).
- sn -
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that bus will be latched, as Figure 4
shows.,since it is assigned at the end of
process p l . Rule 4 can b e interpreted in
practice a s “Do not use processes to
specify combinational logic. Use concurrent VHDL, instead.”
Signal assignments may also contain a
time expression given by an After clause
(Rule 3).
IEEE DESIGN &TEST OF COMWTERI
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Variable assignment
Unlike signals, variables are local to a
process. They behave like variables in a
sequential program retaining their value
until a new assignment is made.Variable
assignment in VHDL does not pose any
difficulty for high-level synthesis.
Control constructs
The basic control construct is sequencing. The approach to handling sequences of statements is well known in
high-level synthesis. No additional difficulty is generated in VHDL. The conditional-execution constructs, If and Case,
also d o not pose special difficulties.
The iteration constructs-Loop, Next,
and Exit-do require special consideration and another restriction.
The Next statement causes a jump to
the beginning of a Loop. The Exit statement allows multiple exit points in a
Loop. In general, our synthesis algorithms will keep the specified loops.
Since the loop body must b e repeated,
we must allow at least o n e clock period,
since the repetition will occur when
there is a transition in the control finitestate machine. This greatly simplifies
high-level synthesis.
As we already explained, loops may
be transformed during high-level synthesis,so Rule 5 could b e thought of a s a n
implementation restriction rather than a
hard rule.
Rule 5. The synthesis system often
keeps loops as specified. In this case, a
delay of at least o n e clock period must
b e associated with the loop body
A typical exception to this rule are loops
with fixed boundaries, loops with a
small number of iterations, and loops
that have simple hardware associated
with the loop body
Both Next and Exit generate controlflow graphs that are not series-parallel
but can b e easily converted to seriesMARCH 199 1
parallel. This conversion flexibility may
be advantageous during synthesis and
may significantly reduce the complexity
of some algorithms. For example, propagating timing constraints in the manner
described in “Considering Timing Constraints in Synthesis from a Behavioral
Description”’ and determining if a n operation is dependent o n a previous test
(if or case statement) are much simpler
for series-parallel graphs.
Pmedurecalls
Within a process, we can define a hierarchy of procedure calls. This corresponds to the well-known procedurecall mechanism in modern programming languages. In the example in
Figure 1, process p l calls procedure
read-bus.Recursion is allowed in VHDL,
but because it generates great difficulties for high-level synthesis, we cannot
use it.
Rule 6. Recursive procedure calls are
not allowed.
For high-level synthesis,we can regard
the specification of procedures as a n
initial given partition. We can then synthesize each procedure a s a n independent hardware module, synthesizing the
calling mechanism by possibly introducing just o n e additional wait state in
the control finite-state machine. Thus,
this specification partition simplifies
synthesis because we then deal with
smaller problems.
Alternatively, we can flatten the procedure hierarchy by expanding each call
into the containing process.This alternative is useful if the given decomposition
into procedures is not related to the
final partitioning of the hardware into
modules.
Rule 7. Use the specification of procedures within a process as an initial given
partitioning of the synthesized hardware,or ignore the procedural hierarchy
and flatten the design.
VHDL is a
strongly
typed
language, but
we can avoid
that with
operator
overloading.
In the example in Figure 1, an alternae is to synthesize process p 1 a s a sepate piece of hardware from procedure
ad-bus. The cost would be a possible
,erhead in the calling mechanism and
e loss of optimizations over the
iundaries. The other alternative is the
-line expansion
of
procedure
ad-bus into process p l , which would
merate a larger, less structured synthei problem.
%er statements
The assert statement checks that a
ecified condition is true. Assert stateents only restate explicitly some contion that results from the given hard-
Bus pori
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Bus output
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Bus input
;Sure 4. A bufkred l/O port.. Bus resolu3n can be OR or tristate, for example.
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Clocking
schemes can be
characterized by
the number of
phases and
their length.
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Rule 9. High-level synthesis does not
support file objects and file types.
Data typing
VHDL is a strongly typed language. A
popular argument is that strong typing is
a disadvantage in high-level synthesis.
We can avoid VHDLs strong typing by
operator overloading. Data typing does
not affect high-level synthesis. It only affects the (existing) compiler, which
takes care of type checking, providing
a n additional consistency check. The effects of data typing on programming
practices for high-level hardware descriptions are a matter of taste.
Types in VHDL include scalar types,
composite types, access types, a n d file
types. File types cannot be supported
(see Rule 9), since the corresponding
object is not supported. Scalar types d o
not pose difficulties.
Composite types include structures
and arrays. The compiler decomposes
structures into their components. Arrays
of signals d o not allow dynamic indexing during assignment. That is, a n index
must always b e known before compile
time.This restriction makes the handling
of signal arrays quite easy Arrays of variables within processes in VHDL are not
different from arrays in programming
languages. In the general case, arrays
must be mapped onto multiport memories during synthesis. Strictly speaking,
the following rule is again a n implementation restriction rather than a hard rule,
but since the use of arrays is very important for hardware descriptions, it seems
useful to define their synthesis semantics a s follows:
Rule 10. During high-level synthesis,
variable arrays with dynamic indexing
will result in memories.
Array a in the example in Figure 1 will
result in a 16-bit-wide 16-word memory
The example ignores the obvious optimization that would eliminate the array
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completely because the comment "-operate o n d s t a n d s for code that requires
all 16 values. (If we did not need all 16
values,we could eliminate the array)
The last type in VHDL is the access
type. It provides access to objects created dynamically (the equivalent of a
pointer in programming languages). Access types would require the synthesis
of hardware for dynamic memory allocation. This is possible in principle, but
using hardware of a different level than
the rest of the language (stacks with a n
unknown size that could be specified
using a n attribute, for example). Again,
the following rule that prohibits access
types is more of an implementation restriction:
Rule 11. High-level synthesis does not
support access types.
Clocking
In high-level synthesis, we usually asw m e a given clocking scheme,which in
most approaches u p to now, is a simple
one-phase clocking scheme. In VHDL,
the clocking scheme of a process must
be consistent with the explicitly given
clocking scheme of the concurrent part.
It would be too difficult to support all
clocking schemes, of course. In practice,
the clocking scheme depends on the
technology and the design style.
All relevant clocking schemes for a
zertain design environment must b e
supported. They can be characterized
by a few parameters,mainly by the num3er of phases and by the relative length
3f the phases. They can b e specified by
3ttributes, such as the clock-phases in
'igure 1,which isspecified as 1.
Rule 12. Use an attribute to characterze the clocking scheme. High-level synhesis supports only a limited number of
:locking schemes and assumes the
:locks are present. It may automatically
:reate the clock-generation circuits.
IEEE DESIGN &TEST OF COMPUTERS
Rule 12 eliminates the need for a n explicit clock signal. In concurrent VHDL,
clocking is generally specified using the
edge of a n explicitly given clock signal
to control transfers. To synthesize designs described in both concurrent
VHDL using explicit clocks and sequential VHDL with implicit clocks, the clock
signals must also b e specified using a n
attribute.
w e have exhaustively examined the
suitability of sequential VHDL for highlevel synthesis and defined 12 rules that
allow high-level synthesis from sequential VHDL. Some of these rules (1,2,6,9,
11) restrict the language,while others (3,
4, 5, 7,8, 10, 12) detail the semantics of
sequential VHDL within a particular
high-level synthesis framework. The
rules can also be interpreted as a precise statement of the common limitations of high-level synthesis. As we
pointed out earlier, research is ongoing
to overcome some of these limitations.
The main problem with VHDL in highlevel synthesis is properly interpreting
time and synchronization. Rule 1 solves
this major problem by enforcing the
most beneficial use of the wait statement. We found n o other major difficulties to prevent the use of sequential
VHDL as input for high-level synthesis.
Indeed, the expected advantages of
using a slightly restricted standard as
the source for both high-level synthesis
and simulation should outweigh any
problems. @
References
1. IEEE Standard VHDL Language Refer-
ence Manual, IEEE Std. 1076-1987,IEEE
Computer Soc.Press,Los Alamitos,Calif.,
1987.
2. R. Camposano, “From Behavior to Structure: High-Level Synthesis,”IEEE Design
& Test of Computers, Vol. 7, No. 5, Oct.
1 9 9 0 , ~8-19.
~.
3. R. Brayton et al., “The Yorktown Silicon
Compiler,” in Silicon Compilation, D.
Gajski, ed., Addison-Wesley, Reading,
MARCH 1991
M a s . , 1988,pp.204-310.
4. Silicon Compilation, D. Gajski, ed., Addison-Weslex Reading, Mass., 1988.
5. L. Saunders, “The IBM VHDL Design Sys-
tem,” Roc. Design Automation Conf.,
1987,pp. 484-490.
6.J.Lis and D.Gajski,Synthesis from VHDL,
Proc. Int’l Conf Computer Design, IEEE
Computer Soc.Press,Los Alamitos,Calif.,
1988,pp.378-381.
7. S. Carlson,lntroduction to HDL-Based Design Using VHDL, Synopsys, Mountain
View,Calif.,1990.
8. R. Camposano and A. Kunzmann, “Considering Timing Constraints in Synthesis
from a Behavioral Description,” Int’l.
Con[ on Computer Design, IEEE Computer Soc.Press,1986,pp.6-9.
:aul Camposano is a member of the reearch staff at IBM T.J.Watson Research Cenzr, where his interests include CAD and deign automation for digital systems.
’reviously,he was assistant professor at the
Jniversity of Siegen in Germany and was
brofessor of computer science at the Uni.ersidad del Norte in Antofagasta, Chile. He
vas also a researcher in the Computer Scimce Research Laboratory of the University
)f Karlsruhe in Germany He holds a diploma
n electrical engineering from the University
)f Chile and a PhD in computer science
rom the University of Karlsruhe.
Larry Saunders was an advisory engineer
in automation technology for IBM Application Business Systems until just recently He
had been with IBM since 1976,during which
time he participated in the development of
the SI32 and SI34 processor hardware and
provided support and education to engineers using simulation,LSSD-testgeneration,
and structure-processing tools. He also
headed the development of new design-automation tools related to HDb and logic synthesis.He is a member of the IEEE Computer
Society and chairman of the IEEE Design Automation Standards Subcommittee and
holds a BEE, with emphasis in computer
hardware design, from the University of Illinois.
Raja M. Tabet is manager of the Logic Design Development Group in IBMS General
Technology Division. He has been with IBM
since 1981,concentrating on the design and
implementation of the IBM VHDL Design System.He holds a BS in computer science from
the State University of New York, Plattsburgh,
and an MS in computer engineering from
Syracuse University.
Send questions and comments on this article
to R. Camposano, IBM TJ. Watson Research
Center, PO Box 218, Yorktown Heights, NY
10598.
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