Enhancing DRAM Self-Refresh for Idle Power Reduction
Byoungchan Oh, Nimini Abeyratne, Jeongseob Ahn, Ronald G. Dreslinski and Trevor Mudge
University of Michigan
Motivation
Two Retention States
PSU&Etc.
24%
Bank
Senseamp.
Mat
Peripheral
Mat
Mat
Sub-array
Bank
Bank
Bank
Bank
Mat
WL0
WL0
Unselected
WL1
Cell 1
VDD/2
Unselected
a
Cell 1
VSS
VDD
Active (page-open)
Body
Static
10
Optimal NWL for dynamic
5
Optimal NWL for static
0
2.0
Optimal NWL for static
Static
1.5
1.0
0.5
-0.3
-0.2
-0.1
0.0
Refresh
Refresh
Refresh
Refresh
tREFI
Refresh
Background
ChipLeakage
Time
Power consumption during original self-refresh mode
-0.5
Word-lineVoltage[V]
-0.4
-0.3
-0.2
-0.1
0.0
Word-lineVoltage[V]
Refresh
PowerConsumption
-0.4
Refresh
Optimal NWL for dynamic
0.0
-0.5
Refresh
PowerConsumption
NormalizedRetentionTime
NormalizedCurrent
Proposed Self-Refresh
2.5
15
c
- Five leakage components
- Huge impact of the word-line and body bias on
leakage current
Leakage Current and Retention Time
Dynamic
Storage
node
b
- Dynamic and static retention states
- Less leakage current in static state
Dynamic
d
Word-line
VDD
Dynamic
Retention
Pre-charged (page-close)
20
e
Bit-line
VSS
VDD
VDD/2
Body
Cell 0
WL1
- DRAM is one of major power consuming
components in a modern computing system
- Non-negligible DRAM’s idle power
Selected
Cell 0
Storage
node
BLb
VSS
Static
Retention
Word-line
Senseamp.
BL
Unselected
Static
Retention
Total system idle power (49.5W)
Mat
BLb
BL
SSD
4%
Mat
Word-line
Capacitor
Bank
Mat
Bit-line
Bank
Mat
Word-linedriver
Bank
Mat
Bit-line
Bank
NIC
4%
CPU
55%
Mat
Word-linedriver
DRAM
13%
Chip
DRAM Cell Leakage
- Negative word line bias can suppress leakage current when a DRAM cell is in the dynamic state
- However, negative word line bias increases leakage current of the DRAM cell in the static state
- Selectively applying different bias levels to each state can improve retention time
- Body bias of the DRAM cell have similar trend with the word line bias
Refresh
Refresh
EnhancedtREFI
Time
Power consumption during enhanced self-refresh mode (ESR)
Mat
Mat
Word-line
Driver
PowerConsumption
VSS
VNWL
Implementation
Word-line
Driver
BL
BLb
WL
Mat
Switch
Mat
Mat
Mat
BurstRefresh
BurstRefresh
EnhancedtREF
Time
Switch
Mat
35
Mat
30
VSS
Switch
Current[mA]
Mat
Dynamic
Static
Power consumption during long latency self-refresh mode (LSR)
VNWL
- One switch per sub-array to enable selective word-line bias (minimal area overhead)
- Selective body bias can be enabled with few extra signals
25
OriginalSelf-Refresh
ESR
LSR
20
15
10
5
0
Evaluation
Comparison of current consumption
10
OriginalSelf-Refresh
8
0.6
0.4
0.2
0
Current
LSR
0.8
Power[W]
NormailizedEnergy
1
6
4
2
Proposed
Stand-by
Stand-by
Power-down
Power-down
Self-refresh
ESR
-
LSR
MPSM*
MPSM
*MPSM:
Latency
Increase
Power
Increase
Maximum Power Saving Mode
0
- On average, ESR mode can bring 22% of DRAM energy reduction without performance degradation
- In system idle state, LSR mode can reduce 6.5% of total system power.
InternationalSymposiumonLowPowerElectronicsandDesign2016