ESE370
Fall 2016
University of Pennsylvania
Department of Electrical and System Engineering
Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370, Fall 2016
Final
Thursday, December 15
• Problem weightings shown.
• Calculators allowed.
• Closed book = No text or notes allowed.
• Final answers here.
• Additional workspace in exam book. Note where to find work in exam book if relevant.
• Sign Code of Academic Integrity statement at back of exam book.
Name:
Q1
Q2
Q3
Q4
Q5
Q6
Total
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ESE370
Fall 2016
Default technology:
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•
•
•
•
•
F =22nm High Performance Process (HP)
γ=1
Vdd =900 mV
nominal Vthn = −Vthp =300mV
C0 = 2 × 10−17 F (for W = 1 device)
velocity saturated operation
Device
Vgs
NMOS Vgs < Vthn
Vgs > Vthn
PMOS
Vgs > Vthp
Vgs < Vthp
Ids
Vgs −Vthn
(1 × 10−6 ) W e 40mV
3 × 10−5 W (Vgs − Vthn ) −6
−
Vgs −Vthp
40mV
(−1 × 10 ) W e
3 × 10−5 W (Vgs − Vthp )
Transmission line:
w=√
1
c
=√
r µr
LC
(1)
s
L
C
R − Z0
Vr = Vi
R + Z0
2R
Vt = Vi
R + Z0
Z0 =
2
(2)
(3)
(4)
ESE370
Fall 2016
1. Dynamic Logic (10pts). Consider the following dynamic logic circuit. What logic
function does it evaluate?
Assume the circuit is loaded by 12C0 output. Assume Cdif f = 0.5Cgate , µn = 2µp .
Assume the CLK signal is driven strongly such that the rise time on the clock is
R0 C0 . Use Elmore delay calculations where appropriate. For full credit (and partial
credit consideration) show your delay components (stages, components of Elmore delay
calculation).
Out as a function of the
inputs: A, B, C, X, Y, Z?
Evaluate Delay in units of τ
(show delay
components)
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ESE370
Fall 2016
2. Synchronous Timing (10pts).
Consider latches A, B and C each nominally clocked off of the same clock. Assume:
• Each latch has a set-up time of 5ns and a clock-to-Q delay of 3ns to 4ns.
• The AND and OR gates each have a delay of 2 to 6 ns.
• The NOT gate has a delay of 1 to 5 ns.
(a) What is the shortest clock period you could safely clock this system at? Show
your work.
(b) What is the (non-negative) range of values for the flip-flops hold time would be
sufficient? Show your work.
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ESE370
Fall 2016
3. Memory (25pts). Here we consider implementing a serial memory as we might use
for a limited form of First-In-First-Out (FIFO). Assume we will write all the data to
memory first, then read all the data out.
Consider the following memory cell and chained memory configuration (for N =4 cells):
en<3>
en<2>
en<1>
en<0>
enable
enable
enable
enable
in
in
in
in
out
out
out
out
To write into cell i, we turn on all the enables ≥ i, allowing the value to propagate
from the input into cell i. We then turn off enable i so that cell i is not overwritten
when we write into the cells in higher positions.
To read from cell i, we turn on all the enables < i, allowing the value to propagate
from the cell to the output.
(a) What sizing issues does this cell have to guarantee correct operation?
(b) Which transistors can be minimum size for correct operation?
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ESE370
Fall 2016
For the following, assume it takes energy Ewrcell to overwrite the value in a memory cell.
(c) What is the total core energy to write all N values into the memory? (core energy
– only worry about energy to drive the transistors in all the memory cells shown,
not the external control energy.)
(d) Consider the hybrid case that adds a bypass line every k cells. Shown below is a
configuration for N = 8 and k = 3.
bypass_write
en<7>
enable
in
bypass<2>
Cs2s
out
en<6>
en<5>
en<4>
bypass<1>
en<3>
en<2>
en<1>
bypass<0>
en<0>
enable
enable
enable
enable
enable
enable
enable
in
in
in
in
in
in
in
out
out
out
out
out
out
bypass_read
out
W=4
bypass_line
• Assume Vdd =1V
• Assume Cdif f = 0.5Cgate
• Energy driving Cs2s is already included in Ewrcell
i. What is the energy required to drive the bypass line (function of N and k)?
ii. What is the energy to write all N cells as a function of k?
iii. What value of k minimizes total write energy? (symbolic answer)
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ESE370
Fall 2016
4. Long distance communication (10pts). Two clocks are used on chip, phi1 and phi2
and are shown below where phi1 is 3 times the frequency of phi2.
They are input into two inverters and the clocks and inverted clocks run adjacent to
each other for a long distance on a chip. Two different configurations are designed
with identical inverters and labeled below with A and B.
The waveforms from the configuration have different delays and are labeled below with
1 and 2.
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ESE370
Fall 2016
(a) Identify which configuration (A and B) and waveforms (1 and 2) match. Explain
your reasoning.
(b) Identify which configuration has the smaller delay and what about the configuration results in the smaller delay.
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ESE370
Fall 2016
5. Transmission Line Termination (25pts). A long data bus is designed and is modeled
as a transmission line with transmission lines branched off it as shown below. The
schematic shows a source end, S1, two branches, B1 and B2, and three destinations,
D1, D2, and D3. The intent of the design is for the waveforms on D1, D2 and D3
to be identical in shape to the source waveform with some propagation delay, but the
design fails to do that.
(a) Given the source waveform is a 900mV 2ns pulse at 0ns (shown below), draw the
waveforms seen at B1, B2, D1, D2, and D3 from 0ns to 20ns.
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ESE370
Fall 2016
(b) Fix the design so that D1, D2 and D3 are identical to the source waveform with
the same propagation delay as the design model in part (a). Draw the new design
model and clearly label the parameters (z0 and Delay) of each transmission line
segment as well as any resistors.
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ESE370
Fall 2016
6. (20 pts) Short Answer Questions: Answer the questions briefly. Include diagrams and
equations as needed. Be clear in your explanation and handwriting.
A What is velocity saturation and under what conditions does it occur in a MOSFET
device?
B What power density problem can you encounter with ideal scaling from technology
node to technology node and how can you avoid this?
C What is a tristate buffer and what benefits do we get from it? Draw a schematic
example to help explain your answer.
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ESE370
Fall 2016
D Why does DRAM need to be refreshed?
E Identify two techniques to reduce the effects of inductive noise.
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