Conference Program: Multicore Expo Munich
Tuesday, Nov 14, 2006, ICM - Munich Trade Fair Center
Topic
Speaker
Company/Organization
Topic
Session 1
Going Multicore:
Opportunities, Challenges and Dreams
9:30
The Multicore Transition:
Challenges and Directions
11:00
Multicore Systems Going Embedded:
Challenges and Solutions
11:00
Anant Agarwal
MIT/Tilera
Alex Klimovitski
Intel
Manfred Schlett
Renesas
Break
Going Multicore:
Opportunities, Challenges and Dreams
9:30
The Multicore Transition:
Challenges and Directions
11:00
Multicore Systems Going Embedded:
Challenges and Solutions
11:00
PolyCore Software
11:30
Anant Agarwal
MIT/Tilera
Alex Klimovitski
Intel
Manfred Schlett
Renesas
Break
Empowering the Programmer with Truly
Concurrent and Efficient Mechanisms
Håkan Sundell and
Philippas Tsigas
Parallel Scalable Solutions
SMP Requirements and Architecture
for Embedded Multicore Devices
Michael
Christofferson
Enea
11:30
Building a Network for On-Chip
Communications
13:00
Marcello Coppola
STMicroelectronics
Lunch
13:00
Session 2
Lunch
Session 4
Seamless Transformation of Single-Core
Embedded Solutions into Next
Generation Multicore Offerings
Larry Leibson
Torrenza: Multi-Processing Enablement
through direct attachment
Peter Robinson
15:30
16:00
17:30
Company/Organization
Session 3
A Standardized Approach to Asymmetric
Sven Brehmer
Multicore Programming
14:00
Speaker
Mplicity
14:00
AMD
Break
Experiences in Uncovering Thread-level
Parallelism using Transactional
Memory Models
Per Stenstrom
Chalmers University
of Technology
Development and Optimization
Techniques for Multicore Processors
Bernth Andersson
Intel
15:30
Inside Views of the SH-Mobile G Series a Heterogeneous Multicore Architecture
Manfred Schlett
Renesas
Multicore for the Embedded World - A
Completely Different Planet
Steve Roddy
Tensilica
Efficient Multi-Processing for Media
Applications
Peter Hutton
ARC International
16:00
17:30
Break
Multiprocessor Real-Time Scheduling
in a Microkernel-Based System
Robert Kaiser
Scheduling Considerations for
Real-Time Symmetric Multiprocessing
David Kleidermacher Green Hills Software
Industrial Requirements for
Multiprocessing Chips
Hans Carper
SYSGO
Dualcore Semiconductor
Conference Program: Multicore Expo Munich
Wednesday, Nov 15, 2006, ICM - Munich Trade Fair Center
Topic
Speaker
Company/Organization
Topic
Session 5
9:30
Cesar Martin-Perez
Challenges and Solutions of MPSoC
System-Level Design Automation
Frank Schirrmeister
MIPS Technologies
9:30
Imperas
Break
Measuring the Performance
of a Multicore Platform
Markus Levy
EEMBC
11:30
Just How Well do Media Codecs Run on
John Goodacre
an Embedded Multicore Processor?
ARM
Lunch
Cesar Martin-Perez
MIPS Technologies
Challenges and Solutions of MPSoC
System-Level Design Automation
Frank Schirrmeister
Imperas
Break
Configurable Interconnect Feature Set
Options for Multicore SoC
Jeff Haight
Sonics
Socket-level Traffic Monitoring Implementing a Next-Generation
Interconnect
Neal Stollon
MIPS/FS2
13:00
Lunch
Session 6
Session 8
Utilizing OpenSPARC, Sun's Opensource
Constantin Gonzalez Sun Microsystems
Hardware Initiative
Next Generation Network Application
Processing using Multicore MIPS64
Processor with L3-L7 HW Acceleration
14:00
14:00
Multicore Techniques
15:30
16:00
17:30
Implementing a High Performance
Platform Architecture for MIPS
Processors
11:00
11:30
13:00
Company/Organization
Session 7
Implementing a High Performance
Platform Architecture for MIPS
Processors
11:00
Speaker
Alain Fanet
Scalable Upgradable Multicore Fabric
for Packet Processing
Arteris
Break
15:30
Efficient Debugging of
Multicore Environments
Anton Langebner
Wind River
The Practical Application
of a Multiprocessor Chip
Stefan Kaneff
Dualcore Semiconductor
Debugging & Optimizing Parallel
Applications: from 1 to 1000s of Cores
Michael Rudgyard
Allinea Software
16:00
17:30
Cavium Networks
Bryon Moyer
Teja
Break
Writing Reliable, High Performance
Software on Multicore Processors
Andrew Richards
CodePlay
Migrating Your Existing Code
to Multicore Processors
Elia Basam
QNX
OPEN CLASS
Registration: Multicore Expo Munich
Fax to (+ 49 89) 74 64 22 02
❑
Yes, I want to attend the Multicore Expo Munich 2006 (please specify):
n
dmissio
ludes a
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in
e
!
ic
Pr
tronica
to elec
Tuesday
Morning
❑
Afternoon
❑
Session 1
Session 2
❑
Session 5
Session 6
❑
❑
Session 3
Session 4
Wednesday
Morning
❑
Afternoon
❑
❑
Session 7
Session 8
Lunch
(please specify)
❑
Lunchbox
❑
Seated Lunch
FEES: (1/2 day = 1 session)
1 Session
2 Sessions
4 Sessions
185 EUR*
295 EUR*
545 EUR*
*subject to VAT.
Details: www.electronica.de/embedded
A registration to Multicore Expo Munich gives you free access to the
"electronica embedded Conference Munich" at the same location.
❑ Yes ❑ No
Do you plan to attend this embedded conference?
Methods of payment
The registration fees for the Conference are due with order. Please ensure when payment is made by bank transfer that the transfer/bank
charges are paid by yourself and not by the organizer.
❑ Bank transfer: Made through (name of your bank)
in Euro and free of charge to the recipient Vogel Industrie Medien.
Account No. 301427700 at Dresdner Bank AG, Bank Code 79080052, S.W.I.F.T.-Code (BIC): DRES DE FF 790,
IBAN: DE08 7908 0052 0301 4277 00. All payments must be addressed to: Vogel Industrie Medien code:
Multicore Expo. Please state participant's name clearly, otherwise payment cannot be identified!
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Address
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Postal Code
Phone
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e-mail
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Cancellation Policy: You may cancel in writing to Vogel Industrie Medien GmbH & Co. KG before October 20th, 2006 and receive a 75%
refund. Registrations received after October 20th, 2006 are not eligible for a cancellation refund.
Place
Date
Signature
Contact:
Johann Wiesböck
Vogel Industrie Medien GmbH & Co. KG
Supported by
Grafinger Straße 26
81671 München, Germany
Tel.
(+ 49 89) 746 42-207
Fax
(+ 49 89) 746 42-202
Mobil (+ 49 171) 763 72 74
E-mail: [email protected]