Course AE0B38APH - FPGA Application
1) Constants, variables, signals
ara
and sequential
an
s qu nt a domains
oma ns
2)) Parallel
Lecture topic 5,6
5 6
AE0B38APH ‐ FPGA Applications
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Data Objects in VHDL
 Constants
 Signals
g
 Variables
 Object declaration : assignment a value and type
associated with it
 Signals can be considered wires in schematic – their
y signal
g
assignment
g
statements
values are defined by
 Constants and variables are used to model the
behavior of a circuit
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Constants in VHDL
Syntax:
constant identifier : subtype_indication := constant_expression;
Examples:
E
l
constant
constant
constant
constant
Pi : real := 3.141;
Half_Pi : real := Pi/2.0;
cycle_time
y
: time := 2 ns;
N, N5 : integer := 5;
-
constant has a single value, cannot be changed during the simulation process
-
a deferred constant has no := constant_expression can only be used in a
package declaration and a value must appear in the package body !
-
may be declared at start of an architecture, can be used anywhere in
architecture,
-
constants declared in process is to see only in that process
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Signals in VHDL
Syntax:
signal identifier : subtype_indication
subtype indication [ signal_kind
signal kind ] [ := expression
];
Examples:
signal a_bit : bit := '0'; -- signal declariation
a_bit <= b_bit xor '1';
-- concurrent assignment
signal my_word : word := X"01234567"; -- signal declariation
my_word <= X"FFFFFFFF"; -- concurrent assignment
- signal is updated when their signal assignment statement is
executed, after a certain delay
f.e.: SUM <= (A xor B) after 2 ns;
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Selected assignment of signal value
Syntax:
WITH sel_signal SELECT
Signal
<= value_1 WHEN value_1_sel_signal,
<= value_2
value 2 WHEN value
value_2_sel_signal,
2 sel signal,
<= value_3 WHEN value_3_sel_signal;
Example:
WITH sel SELECT
out1 <= i0 WHEN “0000” TO “0100”, -- selection „from“ „to“
<= i1 WHEN “0101” | “0111”, -- „or“
<= i2 WHEN “0101”,
0 0 ,
<= i3 WHEN OTHERS; -- other values
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Conditional assignment of signals
Syntax:
signal <= value_1 WHEN condition_1 ELSE
value_2 WHEN condition_2 ELSE
value 3 WHEN condition_3
value_3
condition 3 ELSE
value_4;
Example:
hd1 <= i0 WHEN w=
w=’0’
0 ELSE
i1 WHEN x=’1’ ELSE
i2 WHEN z=’1’ ELSE ‘0’;
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Signal Attributes

signal_name’event returns the Boolean value True if an event on the signal occurred,
otherwise gives a False

signal_name’active returns the Boolean value True there has been a transaction
( ssi nm nt) on
(assignment)
n the
th signal,
si n l otherwise
th
is gives
i s a False
F ls

signal_name’transaction returns a signal of the type “bit” that toggles (0 to 1 or 1 to
0) every time there is a transaction on the signal.

signal_name’last_event returns the time interval since the last event on the signal

signal_name’last_active returns the time interval since the last transaction on the
signal

signal_name’last_value gives the value of the signal before the last event occurred on
the signal

s gnal_name
signal
name’delayed(T)
delayed( ) g
gives
ves a signal
s gnal that iss the delayed vers
version
on (by time
t me T)) of the
original one. [T is optional, default T=0]

signal_name’stable(T) returns a Boolean value, True, if no event has occurred on the
signal during the interval T, otherwise returns a False. [T is optional, default T=0]

signal_name’quiet(T) returns a Boolean value, True, if no transaction has occurred on
the signal during the interval T, otherwise returns a False. [T is optional, default T=0]
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An example of an attribute signal
if ((CLOCK’event and CLOCK=’1’)) then …
This expression checks for the arrival of a positive
clock
l k edge.
d
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Variables in VHDL
Syntax:
variable identifier : subtype_indication
subtype indication [ := expression ];
Examples:
variable count : integer := 0;
variable CNTR_BIT: bit :=0;
variable VAR1: boolean :=FALSE;
: FALSE;
- a variable has a single value as a constant, but can be
updated using a variable assignment statement
- variables must be defined inside a process (are local to
the process)
- the variable is updated without any delay !
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What’s difference between variables and signals ???
Example of a process using Variables
architecture VAR of EXAMPLE is
si nal TRIGGER,
signal
TRIGGER RESULT: inte
integer
er :=
: 0;
begin
process
variable var1: integer :=1;
variable var2: integer :=2;
variable var3: integer :=3;
begin
wait on TRIGGER;
var1 := var2;
-- var1 = 2
var2 := var1 + var3;
-- var2 = 5
var3 := var2;
-- var3 =5
RESULT <= var1 + var2 + var3;
end process;
end
d VAR
The result will have value of 12 after processing. Way ?
The each variable is computed sequentially and updated instantaneously !!!
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What’s difference between variables and signals ???
Example of a process using Signals:
architecture SIGN of EXAMPLE is
signall TRIGGER,
E RESULT:
E
integer := 0;
signal signal1: integer :=1;
signal signal2: integer :=2;
signal signal3: integer :=3;
begin
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
end SIGN;
Values
V
l s of
f signals
si
ls are computed
m t d att time
tim of
f trigger
t i
(at
( t th
the same
s m tim
time –
symultaneously) . Therefore value of RESULT is 6 !!!
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Initialization and assignment of sig. and var.
Both signal
g
and variables use := for initialization
Signal uses
Variable uses
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:=
for concurrent assingment
for sequential assingment
12
Sequential domain
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Sequential statements - process
 A process is a wrapper for sequential statements
 Sequential statements model combinational or synchronous
l i ((or b
logic
both).
h)
 Statements within a process are executed sequentially.
 Beware! Signal
g
assignments
g
are BOTH concurrent and
sequential.
 A process is concurrent with other concurrent
statements in an architecture.
architecture
 An architecture can have multiple processes.
 Only
y variables may
y be declared within a process.
p
Signals must be declared outside the process.
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Sequential statements - process
Syntax:
process
--variables
i bl
begin
--Sequential Statements
end process;
p
Example: process with synchronous RESET
process
begin
wait until clk'event AND clk='1';
if reset = '0' then
A <= "0000";
0000 ;
else
A <= B;
end if;
end
nd process;
p
ss;
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Process with asynchr. reset
process (reset, clk)
begin
g
if reset='0' then
-- Initial conditions for registers
elsif (clk'event and clk='1') then
-- Behavior of the circuit when not in reset.
end
d if;
if
end process;
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Sequential statements – IF
 VHDL has the full range of sequential statements
found in any language – IF, CASE, various forms of
LOOP
P:
syntax if:
if conditional then
--sequential
sequential statements
elsif conditional then
q
statements
--sequential
else --sequential statements
end if;
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Example: IF statement
entity my_if is
port ( c, d, e, f : in std_logic;
s : in std_logic_vector(1
_ g _
( downto 0);
)
pout : out std_logic );
end my_if;
architecture
hit t
my_arc of
f my_if
if is
i
begin
myif_pro: process (s, c, d, e, f)
begin
if s = “00” then pout <= c;
elsif s = “01” then pout <= d;
elsif s = “10” then pout <= e;
else pout <= f;
end if;
end process myif_pro;
end my_arc;
my arc;
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Sequential statements – CASE
Syntax:
CASE expression IS
WHEN value_ expression _1 => statement_1;
WHEN value_ expression _2 => statement_2;
WHEN value_ expression _3 => statement_3;
WHEN OTHERS => statement_4;
t t
t 4
END CASE;
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Example: CASE statement
entity my_case is
port ( c, d, e, f : in std_logic;
s : in std_logic_vector(1
_ g _
( downto 0);
)
pout : out std_logic );
end my_case;
architecture
hit t
my_arc of
f my_case iis
begin
mycase_pro: process (s, c, d, e, f)
begin
case s is when “00” => pout <= c;
when “01” => pout <= d;
when “10” => pout <= e;
when
h
others
th
=> poutt <= f;
f
end case;
end process mycase_pro;
end my_arc;
my arc;
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WAIT statement
Syntax:
WAIT (ON signal_list) (UNTIL expression) (FOR time);
Examples:
Examples
WAIT ON s1,s2; -- wait for signal changing
WAIT FOR 50ns; -- delay of 50ns
WAIT UNTIL enable = ‘1’;
1 ; -- stop until enable = “1”
1
Conditions can be combined as folow:
WAIT ON a,b UNTIL clk=’1’;
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Loops in VHDL
loop_label: LOOP
-- Unconditional loop
statement(s);
END LOOP loop_label;
loop_label: FOR loop_variable in RANGE LOOP -- FOR loop
statement(s);
END LOOP loop_label;
p
loop_label: WHILE condition LOOP -- WHILE loop
statement(s);
END LOOP loop_label;
loop label;
NEXT loop_label WHEN condition; -- NEXT : Causes the loop to begin
when condition is true
-- EXIT : Terminates the loop, unconditionally or conditionally
EXIT loop_label; -- or
EXIT loop_label WHEN condition;
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Concurrent statements
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Concurrent statements
 Signal assignment
outc <= ina AND (inb OR inc);
 Process
 Block statements
 Instantiation
h1: halfadd PORT MAP( a => ina, b => inb,sum =>
s1 c => s3);
s1,
 When-else
outc <= ina WHEN inc = ’0’ ELSE inb;
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Process statement - syntax
Syntax:
label : process [ ( sensitivity_list ) ] [ is ]
[ process_declarative_items ]
begin
sequential statements
end
d process [ label
l b l];
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Process statement - examples
-- input and output are defined a type 'word' signals
reg_32: process(clk, clear)
begin
if clear
clear='1'
1 then
output <= (others=>'0');
elsif clk='1' then
output <= input after 250 ps;
end if; end process reg_32;
reg 32;
-- assumes use IEEE.std_logic_textio.all
printout: process(clk) -- used to show state when clock raises
variable my_line : LINE; -- not part of working circuit
begin
if clk='1' then
write(my_line, string'("at clock "));
write(my_line, counter);
write(my_line,
it (
li
st i '("
string
(" PC="));
PC "));
write(my_line, IF_PC);
writeline(output, my_line);
counter <= counter+1;
end if;
end process printout;
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Block statements - syntax
Syntax :
label : block [ ( guard expression ) ] [ is ]
[ generic clause [ generic map aspect ; ] ]
[ port clause [ port map aspect ; ] ]
[ block declarative items ]
B i
Begin
concurrent statements
end block [ label ] ;
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Block statements - example
clump : block
begin
A <= B or C;
D <= B and not C;
end block clump ;
maybe : block ( B'stable(5 ns) ) is
port (A, B, C : inout std_logic );
port map ( A => S1, B => S2, C => outp );
constant delay: time := 2 ns;
signal temp: std_logic;
begin
g
temp <= A xor B after delay;
C <= temp nor B;
end block maybe;
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Component instantiation statement
architecture structural of BUZZER is
-- Declarations
component AND2
port (in1, in2: in std_logic;
out1:
1 out std_logic);
d l
)
end component;
component OR2
port (in1, in2: in std_logic;
out1: out std_logic);
end component;
component NOT1
port (in1: in std_logic;
out1: out std_logic);
end component;
-- declaration of signals used to interconnect gates
signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic;
begin
-- Component instantiations statements
port map
p (DOOR, DOOR_NOT);
U0: NOT1 p
U1: NOT1 port map (SBELT, SBELT_NOT);
U2: AND2 port map (IGNITION, DOOR_NOT, B1);
U3: AND2 port map (IGNITION, SBELT_NOT, B2);
U4: OR2 port map (B1, B2, WARNING);
end structural;
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Any questions
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