Journal of The Electrochemical Society, 146 (10) 3827-3832 (1999)
3827
S0013-4651(99)02-072-8 CCC: $7.00 © The Electrochemical Society, Inc.
Selective Hemispherical Grained Polysilicon Transformation for 256 MB,
1 GB Dynamic Random Access Memory and Beyond
M. M. Mansoori,a,z A. Banerjee,b,* A. Shimizu,c Y. Mori,c R. L. Wise,b
M. F. Pas,b,* and B. Chatterjeeb
aASM America, Phoenix, Arizona 85034 USA
bTexas Instruments, Silicon Technology Development,
cASM Japan
Dallas, Texas 75243 USA
Application of an ultrahigh vacuum vertical batch reactor for selective chemical vapor deposition of hemispherical grain (HSG)
polysilicon on planar and three-dimensional crown capacitor storage nodes is investigated. Comparison between selective HSG and
other nonselective alternatives is drawn. An optimum pre-HSG clean chemistry (with 60 Å overall oxide etch), suitable for 256 MB
and 1 GB application, for both multi- and single tank wafer clean modules is recommended. This clean method maintains the
integrity of the starting a-Si (>5% of the original a-Si thickness) prior to HSG transformation. Contamination issues related to the
tool, preclean module, and the processing ambient are explored. Factors impacting within wafer and wafer-to-wafer reflectance and
capacitance uniformity and the effect of particles and crystallization defects on HSG transformation are evaluated. Defect formation mechanisms and ways of minimizing defect density are also included. Effects of critical processing parameters on HSG grain
characteristics in order to obtain maximum area enhancement factor and highest Cmin/Cmax ratio for high density application
(256 MB, 1 GB, and beyond) is explored in depth. Post-HSG gas phase doping (8008C for 300 s) to achieve a Cmin/Cmax ratio of
>0.95 and its effect on surface roughness of HSG transformed a-Si film is investigated.
© 1999 The Electrochemical Society. S0013-4651(99)02-072-8. All rights reserved.
Manuscript submitted February 18, 1999; revised manuscript received May 28, 1999.
Reduction in minimum feature size, cell area, applied voltage,
effective capacitor dielectric thickness, and the overall capacitance
per cell have been realized in advanced dynamic random access
memory (DRAM) technology.1 This trend has continued through the
development of the 1 Gbit DRAM era and will continue as long as
improvements in lithographic resolution continue to be made.2 With
the reduction in cell area, different techniques to achieve the required capacitance have been proposed. Increasing the capacitor
area, thinning the dielectric, and using high dielectric constant material can increase stored charge in a DRAM cell. Issues such as
increased junction capacitance, higher voltage on the gate of the
transfer device, and reduced cell leakage to increase the cell retention time add to the challenges of satisfactory performance of miniature DRAM cells.3
A DRAM cell consists of one transistor and one capacitor. The
capacitor stores the data and the transistor transfers the data to and
from the capacitor.3 To increase capacitance of a DRAM cell, the
bottom storage electrodes are made of 3-D structures such as stacks,
cylinders, and crowns. For additional area enhancement, depositing
a layer of rugged polysilicon film or transforming an amorphous silicon (a-Si) electrode into hemispherical grain polysilicon increases
the surface roughness/area of the 3-D storage nodes.
In a narrow deposition temperature range (570-5858C), it is possible to deposit a “rugged polysilicon” layer by direct low pressure
chemial vapor deposition (LPCVD).4 Hemispherical shaped grains
are spontaneously deposited on the surface of a doped polysilicon
layer. Grain size, height, and spacing is simply controlled by either
deposition temperature or silane flow. Narrow temperature and flow
windows present challenges for accurate process control. The disadvantage is the nonselective nature of this process. In order to prevent
shorting of the capacitor bottom electrodes, an additional polysilicon
etchback from the field is required. Control of this etchback process
for small geometry and minimal internode spacing introduces challenges in the production of high density DRAM.
Another method for hemispherical grain (HSG)-Si formation is
by subsequent high vacuum anneal of a pre-existing amorphous silicon film.4 Since this process lacks a seeding (or nuclei generation)
step, it is generally more difficult to control grain density on the
* Electrochemical Society Active Member.
z E-mail: [email protected]
transformed a-Si layer. The process however, is selective in nature,
since it does not involve a seeding stage. Anneal temperatures of
approximately 6008C are common for this type of process.
Seeding method for the growth of HSG with molecular beam
deposition was an inevitable evolution of the previous methods of
surface roughening.1 This technique consists of first seeding Si
nuclei on a clean Si surface. Upon subsequent isothermal anneal
under ultrahigh vacuum conditions, Si microcrystals act as nucleation sites for the formation of HSG grains, as shown in Fig. 1 (HSG
grains in the cross-sectional transmission electron microscope
(TEM) image are outlined for better clarity). The comparative
advantage of this process is the ability to easily control grain features
and grain density.
Advancement in polysilicon technology finally led to the development of an ultrahigh vacuum chemical vapor deposition
(UHVCVD)-for HSG transformation. This process is comprised of a
seeding step to selectively generate the silicon nuclei, followed by a
subsequent isothermal anneal at system base pressure (typically at
3.0 3 1028 Torr). Standard processing parameters for the seeding
stage are as follows: temperature 560°C, pressure 4.0-5.0 3 1025
Torr, silane flow 15-100 standard cubic centimeters per minute
(sccm), silane percentage (in He or N2) 20 to 100%, and seeding
time $15 min. Selectivity is achieved by growing HSG grains under
UHV conditions. This selective process precludes polysilicon post
etchback from the surrounding dielectric. Selective HSG may be
deposited in batch or single wafer UHV reactors. Batch UHVCVD
reactors provide a SiH4-based, low temperature, high throughput
Figure 1. Top-down and cross-sectional view of HSG grains.
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Journal of The Electrochemical Society, 146 (10) 3827-3832 (1999)
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alternative resulting in an increase in capacitance by up to a factor of
three as compared to smooth polysilicon film incorporated in identical cell structure.
Presence of native oxide, hydrocarbon impurities, and high
dopant concentration on the a-Si film impede surface migration and
consequent growth of HSG grains. Several researchers have investigated growth kinetics of HSG-Si on clean a-Si surface.5 Based on a
geometric model, upward growth of Si grains resulting in the formation of hemispherical grains has been formulated mathematically.
According to this kinetic study, the activation energy for HSG growth
(during the anneal stage) was found to be approximately 2.3 eV.5
This paper focuses on unique aspects of selective HSG process in
a batch UHVCVD reactor for higher density DRAM applications.
The ASM A600 batch UHV CVD reactor (shown in Fig. 2) for selective deposition of HSG grains is introduced. In addition many important practical aspects of HSG process related to 256 MB and 1 GB
applications are discussed.
Experimental
Metal oxide semiconductor capacitors (MOSCAPs) were fabricated by incorporating HSG transformed a-Si films as bottom electrodes. a-Si films were deposited by a low-pressure chemical vapor
deposition (LPCVD) process. LPCVD undoped a-Si deposition was
carried out in a furnace from silane source gas at 5258C. Doped a-Si
films were deposited from silane and phosphine source gases at
5108C. HSG transformation of the a-Si layers was conducted in an
ASM A600 UHVCVD batch reactor. The seeding temperature and
pressure were 5608C and 5 3 1025 Torr, respectively. Immediately
following the seeding step, an isothermal anneal was performed at
3 3 1028 Torr to form the HSG grains. For the fabrication of
MOSCAP devices, the HSG films were formed over 8000 Å of
phosphorus doped polysilicon bottom electrode. The HSG films
were annealed in phosphine ambient at 8008C in a single wafer reactor. Subsequent rapid thermal nitridation was conducted at 7508C in
an NH3 ambient. MOS capacitors with Ta2O5 dielectric were fabricated. An LPCVD Ta2O5 dielectric was deposited from tantalum
pentaethoxide and oxygen source gases at 4108C. A TiN top electrode was subsequently deposited by an enhanced CVD (ECVD)
process using a tetrakis(dimethylamido) titanium source gas. In
addition to the LPCVD Ta2O5 dielectric, nitride film was also used
as dielectric for MOSCAP devices. Polysilicon top plate electrode
completed the nitride-based MOSCAP device structure. Similar
process flow was used in fabricating 256 MB crown DRAM capacitor storage nodes.
An a-Si surface with minimal native oxide, hydrocarbon contaminants, particulates, and metallic impurities is a prerequisite for HSG
transformation. In this study, all wafers were prepared with the following preclean chemistry: SC1 (1:2:10 ratio, 60°C, 300 s), postSC1 deionized (DI) water rinse (600 s); dilute HF (DHF) dip (1:100
Figure 2. Schematic drawing of the cluster platform along with two process
modules.
dilution, 368C, 128 s dip targeting 60 Å overall oxide etch), postDHF DI rinse (600 s), final DI rinse (600 s), and isopopylalcohol
vapor dry (600 s).
Results and Discussion
HSG preclean.—Native oxide removal by DHF provides surface
passivation in the form of hydrogen terminated silicon dangling
bonds. Surface passivation determines the sensitivity of the surface
to cleanroom ambient exposure. It is generally preferred to have a
DHF treatment equivalent to 200 Å overall thermal oxide etch so
that the wafers can withstand exposure to the cleanroom ambient
without detrimental impact on surface quality. For high density
DRAM applications (cylindrical or crown storage nodes), however,
aggressive native oxide removal is not acceptable due to the resultant
etching of the untransformed a-Si crown/cylinder bottom electrode
or the underlying dielectric. We have determined the effect of DHF
dip time on HSG characteristics. Undoped a-Si wafers were etched
for different times to target 30, 60, and 200 Å thermal oxide removal
while keeping the etch chemistry unchanged. HSG was grown using
the same process conditions on all wafers (temperature 5 5608C,
seed/anneal time 5 15/13 min, SiH4 in He 5 30%, total flow 5 50
sccm). Absolute reflectance at 650 nm for 200 Å thermal oxide
removal was 0.12 (3.13% standard deviation). Reflectance value for
30 Å overall oxide etch changed to 0.198 (9.28% standard deviation). The reflectance nonuniformity was based on nine-point measurement on blanket wafers. This data suggests that longer etch times
result in HSG films of lower mean reflectance and better within
wafer uniformity. Lower reflectance values correspond to higher surface roughness. Therefore, higher overall oxide etch provides more
complete surface passivation by removing the chemical oxide left
from the SC1 clean, increases the tolerance of the surface to ambient contamination, and facilitates the surface migration of silicon
atoms during the anneal stage.
Ambient moisture, hydrocarbons, and other impurities retard
HSG formation. In a series of experiments, samples were left in the
cleanroom ambient for various times prior to loading into the vacuum loadlock. Samples were then HSG transformed and reflectance
measurements were taken. Sample with maximum cleanroom exposure (15 min) showed 0.347 absolute reflectance (10.7% standard
deviation), whereas minimum exposure (1 min) resulted in reflectance of 0.297 (2.0% standard deviation). Once precleaned wafers are
transported into the vacuum loadlocks, they can reside up to 12 h
with no appreciable surface degradation. Quadrupole mass spectrometry analysis of the vacuum loadlocks at 1.0 Torr pressure
showed background H2O, O2, and CO2 levels of 50, 800, and
200 ppb, respectively. To avoid adverse effects of prolonged cleanroom exposure in a production environment, a wet clean station may
be integrated with the UHVCVD reactor in a controlled minienvironment with moisture and hydrocarbon filtration capability. Another alternative is to use a single tank tool. Single tank tools employ
deoxygenated DI water and do not allow ambient exposure during
wafer clean, thereby improving wafer surface quality prior to HSG
transformation.
Ultrathin a-Si deposited on 256 MB and 1 GB storage nodes (approximately 400 Å or less), may be subject to overetching during
HSG preclean. Amorphous silicon films of varying dopant concentration were treated by the aforementioned clean chemistry and different HF dip times. Film thickness was measured before and after
cleans. Films with higher dopant concentrations showed higher a-Si
etch rate. But only 4% of the most heavily phosphorous doped
(4.0 3 1020 atm/cm3) a-Si film thickness was consumed during the
most aggressive wafer clean considered in this study (1:100 dilution,
368C, 128 second dip targeting 60 Å overall oxide etch).
Effects of critical process parameters on HSG transformation.—
The reactive regime during the seeding step (5608C and pressure
<4.0 3 1024 Torr) is molecular, where the gaseous mean free path is
far greater than the characteristic dimensions of the device with
higher frequency of surface collisions than intermolecular collisions.
In this regime, mass transport does not become a limiting factor and
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Journal of The Electrochemical Society, 146 (10) 3827-3832 (1999)
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Figure 3. Change in deposition rate as a function of temperature (pressure 5
4.5 3 1025 Torr, SiH4 partial pressure 5 30%, no isothermal anneal was performed. Prior to thickness measurement, samples were N2 annealed at
9008C).
Figure 5. Effect of silane partial pressure on polysilicon thickness during
HSG transformation.
the overall deposition rate is surface reaction controlled. As a result,
the effects of system pressure and silane partial pressure are not as
prominent as temperature. In a series of deposition experiments
under UHV conditions, the seeding stage was characterized by determining the effects of process temperature and silane partial pressure on silicon growth rate. After polysilicon deposition on preexisting a-Si films of known thickness, samples were N2 annealed at
9008C for 2 h and the deposited polysilicon film thickness was measured. Figure 3 illustrates the Arrhenius dependence of preanneal
deposition at UHV condition (reactor pressure in 1025 Torr range).
Figure 4 shows the effects of temperature on Si growth rate (typically <10 Å per min). HSG transformation may be achieved in a wide
range of processing temperatures (540-6208C). Process temperature
adjustment can be very cumbersome at times, since temperature not
only enhances silicon deposition and subsequent HSG growth rate,
but also increases the possibility of premature crystallization of the
a-Si. So, HSG process temperature optimization should aim for
maximum growth rate while minimizing premature surface crystallization. Figure 5 shows the effect of silane partial pressure on silicon deposition during the seeding stage for selective HSG growth.
Film thickness increases with silane partial pressure for a given
seeding time. But in order to have maximum deposition during the
seeding step while maintaining selectivity, silane partial pressure has
to be optimized.
Dopant concentration of the a-Si is also critical for HSG transformation. Surface phosphorus competes for active sites and
impedes surface mobility of atomic silicon during the anneal stage.
In selecting an optimum dopant concentration for the starting a-Si,
the trade-off is between the ease of HSG transformation vs. the
dopant level requirements of the final capacitor device. For high density applications, we have found that additional gas phase phosphine
doping is necessary to reduce depletion and achieve >0.95 Cmin/Cmax
ratio. Figure 6 illustrates the effect of high phosphorous doping on
Si surface migration and HSG formation. Two sets of double layer
films, one with 1000 Å of heavily phosphorous doped (1.0 3 1021
atm/cm3) a-Si plus 500 Å of undoped a-Si on top, and another with
1450 Å of heavily doped a-Si with a top 50 Å undoped a-Si were
prepared. Both samples were processed in the same manner. During
HSG transformation, once the first 50 Å of the undoped a-Si (in the
latter case) are consumed, surface migration on the remaining heavily doped a-Si becomes more difficult. In the former case, however,
there is 500 Å of undoped a-Si available for surface migration and
grain growth and the impact of the substrate is negligible.
Deposition temperature of the starting a-Si layer is an important
factor in HSG growth. Deposition temperatures were varied from
510 to 5308C for in situ doped a-Si (deposited by silane and phosphine by LPCVD), and 530 to 5508C for the undoped layer. At higher deposition temperatures, polysilicon nuclei form at the a-Si/substrate interface. Upon further heating, these nuclei penetrate through
the amorphous layer, extend to the outer surface, and retard HSG
transformation by prematurely crystallizing the surface. Once the
amorphous phase transitions into crystalline phase, HSG nucleation
and grain growth are greatly inhibited. Figure 7 is the top-down
SEM picture of a typical “bald” crystallization defect. Once the sizes
Figure 4. Effect of temperature on polysilicon thickness during HSG
transformation.
Figure 6. Effect of heavily doped a-Si sublayer on HSG formed on an
undoped top layer.
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Journal of The Electrochemical Society, 146 (10) 3827-3832 (1999)
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Figure 7. Two types of crystallization defects (crystallization during heatup
and crystallization during seeding/annealing stages).
of these defects surpass the characteristic dimension of the node
cells, they can have adverse effect in yield loss, and decrease the
effective area enhancement. Figure 8 illustrates the effect of a-Si
deposition temperature on the formation of these defects. Phosphorous doped (2.0 3 1020 atm/cm3) a-Si films were deposited at 520
and 5308C, and were HSG transformed under the same processing
conditions. a-Si film deposited at 5308C shows a higher degree of
crystallization defects, compared to that deposited at 5208C. In the
absence of throughput issues, lowest possible a-Si deposition temperature is recommended for enhanced HSG transformation.
During the seeding stage, surface incorporation of atomic silicon
from the gas phase and the subsequent nucleation of atomic silicon
compete with one another. Longer seeding time allows for enhanced
nucleation, which ultimately results in higher grain density. For the
fabrication of capacitors, optimum seeding time for HSG transformation should allow for maximum possible grain density (higher
area enhancement) while maintaining sufficient intergrain spacing
for conformal dielectric and top electrode deposition. At 5608C and
pressure of 1.0 3 1024 to 1.0 3 1025 Torr we have determined the
selectivity limits for nitride and thermal oxide dielectrics (28 and 45
min, respectively). Once the first monolayer of silicon is deposited
on the dielectric, selectivity is lost and silicon is equally deposited
on the a-Si storage node and the isolation dielectric. In addition to
loss of selectivity, another perceived problem with excessive seeding
is grain coalescence.
For a given anneal time, longer seeding increases grain density
and decreases the intergrain spacing. Adjacent grains begin to
agglomerate and coalesce into larger entities during the subsequent
anneal stage. If the seeding time is not carefully optimized, the overall area enhancement and capacitance may be at jeopardy, since the
expected increase in area associated with scattered stand-alone
grains is significantly higher than coalesced bodies. Figure 9 illustrates the effect of seeding time on HSG growth for a heavily doped
a-Si films (4.0 3 1020 atm/cm3). Figure 10 shows the relationship
between area enhancement factor (AEF) of blanket MOSCAPs and
grain/a-Si characteristics for a doped film (4.0 3 1020 atm/cm3) with
post-HSG phosphine gas phase doping. At such high dopant concentration surface mobility of atomic silicon is limited and grain
Figure 8. Effect of a-Si deposition temperature on bald defect formation.
Figure 9. Planar TEM illustration of the effect of seeding time on HSG grain
growth.
growth is only possible by longer seeding. As a result of grain
growth, the roughness of the surface increases, the mean reflectance
value decreases, and the overall AEF increases.
Grain growth occurs during the isothermal postincubation anneal
at UHV base pressure (2.0 3 1028 Torr). Silicon atoms that overcome the “diffusion length” activation barrier begin surface migration and contribute to grain growth. The height of a stand alone HSG
grain can reach up to 60 to 70% of the grain diameter from the original a-Si surface. Once all neighboring atomic silicon reach the nearest HSG grain, grain growth stops. Further annealing of the surface
will not lead to continued grain growth. Like seeding time, optimum
anneal time should allow for maximum permissible grain height and
diameter (for maximum AEF) while maintaining sufficient intergrain spacing for the deposition of the dielectric and top electrode.
Figure 11 illustrates the effect of anneal time on grain growth on a
blanket undoped a-Si layer. As shown in this figure, grain density is
not impacted by increasing the anneal time. What has changed, however, is the average grain diameter.
Capacitor storage nodes are isolated by field dielectric. Film
properties of the isolation dielectric are critical to HSG formation
and area enhancement. Due to impurity outgassing, HSG formation
on protruded 3-D node structures is least impacted by nitride and
most inhibited by undensified tetraethylorthosilicate- (TEOS) based
SiO2 field dielectric. Figure 12 illustrates the effect of substrate type
on HSG formation. HSG growth on Si3N4 and thermal oxide (Tox)
isolation dielectrics is significantly superior to that on TEOS SiO2.
Contaminant outgassing from the field dielectric may result in
reduced grain density and grain size on the outer crown or cylinder
node walls. This discrepancy can complicate process tuning, since
process optimization requires a narrow distribution for both grain
density as well as average grain size. If the process is optimized
based on grain growth on the outer cell walls, HSG formation on the
Figure 10. Relationship between seeding time, grain characteristics, and a-Si
consumption.
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Journal of The Electrochemical Society, 146 (10) 3827-3832 (1999)
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Figure 13. Effect of anneal time on HSG growth for 256 MB crown structure.
Figure 11. Planar TEM demonstration of the effect of anneal time on HSG
transformation.
Figure 12. Effect of substrate type on HSG formation on stack capacitor cell 1.
inner walls may suffer from overseeding and/or overannealing. On
the other hand, if one bases the process tuning on HSG characteristics of the inner wall grains, the outer grain may suffer from underseeding and/or underannealing. The same discrepancy may also be
expected between the grains formed on the horizontal surface of a
stack storage node structure as compared to the sidewalls.
Figure 14. Relationship between anneal time, grain characteristics, and a-Si
consumption.
HSG transformation extended to 3-D structures.—On an undoped a-Si layer, 20 min of anneal at 3.0 3 1028 Torr consumes
40 nm of the original a-Si surface, whereas 60 min of anneal on a
heavily phosphorous doped layer (4.0 3 1020 atm/cm3) consumes
only 5 nm of the a-Si. For high density applications (256 MB, 1 GB,
4 GB) with complex 3-D device structures (such as cylinders and
crowns), surface consumption should carefully be examined and
optimized in order to maintain good structural integrity of the bottom electrode. Overconsumption of the wall thickness may result in
weak crown wall cores and unstable structures. Figure 13 shows the
effect of anneal time on HSG growth for 256 MB crown structures.
With Teff of 45 Å for NO dielectric and polysilicon top electrode, an
AEF of 1.7 (compared to crowns without HSG) was realized. Figure 14 shows the relationship between AEF of blanket MOSCAP
and grain/a-Si characteristics for an undoped film with post-HSG
gas phase doping.
For effective charge accumulation and enhanced capacitance, it is
important to have sufficient dopant near the outer surface of the
transformed bottom electrode. Results have shown that the Cmin may
be compromised by up to 30 to 40% as a result of insufficient dopant
near the outer surface of the transformed bottom electrode. During
the anneal stage of HSG transformation, silicon atoms migrate on
the surface, while the dopant atoms of the starting a-Si diffuse
upward and segregate in between the grain boundaries of polycrys-
talline HSG grains. Surface migration of silicon atoms, however, is
faster than dopant up-diffusion. This is based on a simple comparison between the activation energies associated with of the two
processes. Table I reports the activation energies of phosphorous diffusion in different silicon crystalline structures.6 Activation energy
of dopant diffusion through HSG grains is not documented, but it
should be close to 3.4 eV. Kinetic studies of grain growth have
repeatedly shown that the activation energy for silicon atom surface
migration is approximately 2.3 eV. Based on a simple comparison,
silicon migration during anneal stage requires less energy than phosphorous up-diffusion. Therefore, after the HSG processing, the
grains may lack sufficient dopant levels. Once the HSG transformed
a-Si undergoes a doping process (PH3 anneal), gas phase phosphorous diffuses into the grains and provides sufficient dopant for effective charge accumulation. In another study, we have shown that
Cmin/Cmax ratio >0.95 may be achieved for both doped and undoped
a-Si by proper gas phase doping. Concern about grain integrity and
loss of surface roughness as a result of doping process was also
investigated. 5 min post-HSG phosphine anneal doping at 8008C
does not have an adverse effect on HSG grain characteristics
(reflectance value change from 0.0664 to 0.0645). Smoothening of
rugged surfaces (especially HSG transformed surface) by the
implantation of heavy-mass ions is also documented.1 In order to
Table I. Activation energies for phosphorous diffusion in silicon.
Activation energies
Migrating
species
Phosphorous
(low concentration)
P in monocrystalline
P in polycrystalline
3.85 eV
n/a
Phosphorous
(intermediate concentration)
4.44 eV
3.40 eV
Phosphorous
(high concentration)
4.42 eV
n/a
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3832
Journal of The Electrochemical Society, 146 (10) 3827-3832 (1999)
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Table II. Reflectance and capacitance nonuniformity performance of the ASM’s selective UHV/CVD HSG process.
Phosphorous
doping
Seed/
anneal
(min)
Within wafer
reflectance uniformity
(%)
Wafer-to-wafer
reflectance uniformity
(%)
Within wafer
capacitance uniformity
(%)
Wafer-to-wafer
capacitance uniformity
(%)
Control
Undoped
4.0 3 10220
n/a
15/10
25/50
—
3.0
1.7
—
5.7
1.2
1.26
3.30
2.50
—
3.8
2.6
protect the surface, a thin layer of CVD SiO2 (typically 300 Å) may
be deposited on top of the surface prior to ion implantation. This
suppresses the smoothening of the surface. Ion implantation of HSG
grains should be avoided if the thermal budget of the process flow
allows for alternative thermal gas phase doping processes.
Depending on device architecture and the density of the DRAM,
starting a-Si layer thickness could range from 250 up to 8000 Å. The
number of silicon atoms available for migration is dependent upon
the a-Si layer thickness. As the technology reaches the limits of lithography and patterning capabilities, high density DRAM 3-D structures (such as cylinders and crowns) for 256 MB and 1 GB application demand thiner cell walls. HSG growth on crowns and cylinder
walls is bidirectional. Figure 15 is a cross-sectional TEM image of a
transformed crown cell structure. Bilateral grain growth is clearly
evident in this picture. As a result, layer consumption has to be carefully examined so that the cell walls maintain their structural stability. This figure also shows that after HSG process, there is at least
50 Å of untransformed a-Si core remaining. Maintaining an untransformed a-Si core is important for the structural stability of HSG
transformed crowns. Without an amorphous core, crystallized polysilicon crowns with high aspect ratio are not structurally stable, and
can break easily.
Uniformity, defects, and particle performance.—UHV/CVD
reactor provides a uniform processing environment that results in
low within-wafer and wafer-to-wafer reflectance and capacitance
nonuniformities. Table II shows reflectance and capacitance nonuniformity for a typical HSG process. Mean reflectance values were
measured on blanket a-Si monitor wafers at 650 nm wavelength.
Capacitance nonuniformity data corresponds to gas phase doped
(PH3 anneal at 8008C for 300 s in a single wafer tool)
HSG/Ta2O5/TiN crown capacitor cells. The frequency of capacitance measurements was 100 kHz. Capacitance values were measured at 0 V with 444 and 360 pF for undoped and doped planar
MOSCAPs, respectively.
Reflectance uniformity (measured at 650 nm) of HSG films
across 50 blanket p- wafers inside the vertical batch reactor was calculated to be 0.94% with average within wafer nonuniformity of
2.6%. Continuous particle (>0.136 mm, latex sphere equivalent)
monitoring of 15 HSG process runs showed an average particle
count increase of 8 per wafer (200 mm). HSG films were generated
from 400 Å a-Si, and analyzed under KLA 2138 for defect analysis.
Defects were reviewed under ultrapointe and JEOL JWS7515 scanning electron microscope. On average, one small (>1 mm) and 20
large (<1 mm) particles were added during standard HSG processes.
Maximum number of structural defects was 28 counts per wafer.
These structural defects refer to missing areas of HSG grains. Figure
7 showed the image of a missing patch of grains. The patches are
typically 0.1 mm in size. These structural defects signify that the
HSG transformation process is very sensitive to the surface quality
of a-Si. However, the number of such defects were small and renders
the HSG quality very favorable for advanced DRAM applications.
Conclusion
A UHV vertical batch reactor (ASM A600 UHV HSG) for selective CVD of HSG polysilicon on planar and 3-D capacitor storage
nodes was introduced. Selective polysilicon growth rates under
UHV processing conditions were reported. An optimized HSG preclean method applicable to both single- and multitank clean modules
was suggested. It was found that the optimum DHF step in preclean
should target for lowest overall oxide etch, while providing a repeatable HSG process. We have found that post-HSG gas phase doping
does not impact surface morphology of HSG transformed a-Si film,
but it is a necessary step in capacitor process flow in order to obtain
maximum Cmin. This study recommends a moderately doped a-Si
(1.0 to 2.0 3 1020 atm/cm3) deposited at lowest possible temperature
(5108C) prior to HSG transformation. We propose that under UHV
conditions selective HSG process is most sensitive to temperature
and least sensitive to system pressure or silane partial pressure, indicating that the overall process is controlled by surface reaction
mechanisms and is not impacted by mass transfer limitations. Process tuning requires simultaneous seeding and anneal time optimization for maximum AEF, given the spatial constraints for high
density DRAM. Our studies have shown that nitride field dielectric
(selectivity loss limit of 25 to 28 min) is the right candidate for highdensity applications.
Acknowledgment
The authors wish to thank Dr. G. Hames for assistance in HSG
preclean (Texas Instruments). Special appreciation also goes to L.
Bode and H. Weijtmans for ASM support.
ASM America, assisted in meeting the publication costs of this article.
References
Figure 15. HSG formation on crown structures.
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