Tutorial Slides for Week 10
ENEL 353: Digital Circuits — Fall 2015 Term
Steve Norman, PhD, PEng
Electrical & Computer Engineering
Schulich School of Engineering
University of Calgary
10 November, 2015
ENEL 353 F15 Tutorial Slides for Week 10
Topics for today
D flip-flops and finite state machines.
slide 2/11
slide 3/11
ENEL 353 F15 Tutorial Slides for Week 10
Exercise 1: Moore FSMs and the clock divider
This is the general structure of a Moore FSM . . .
inputs
M
CLK
next
state
logic
next
k state
k state
And this is a clock divider circuit . . .
CLK
Y
output
logic
N
outputs
ENEL 353 F15 Tutorial Slides for Week 10
slide 4/11
The clock divider circuit is just about the simplest possible
Moore FSM.
For the clock divider,
I What is M, the number of input bits?
I What is k, the number of state bits?
I What is N, the number of output bits?
I What is correct Boolean algebra for the next-state logic?
I What is correct Boolean algebra for the output logic?
ENEL 353 F15 Tutorial Slides for Week 10
slide 5/11
Notes about notation for FSMs
Your ENEL 353 instructors will follow notation used in the
course textbook.
S0, S1, S2 and so on are names of states. Note that the
numbers are the same size as the S, on the same level.
S0 , S1 , S2 and so on are state bits—Q outputs of DFFs.
Note that the numbers are subscripts.
Si0 is the next value of the state bit Si .
Many books use the 0 operator for NOT. (For example, in
those books A0 means what our textbook would write as A.)
Watch out for that!
In discussion of FSMs, some books use Qi for the ith state bit,
and Qi? for the next value of Qi .
ENEL 353 F15 Tutorial Slides for Week 10
slide 6/11
Exercise 2
CLK
A
S00
S0
S10
S1
S20
S2
r
R
Y
For this Moore FSM, what are
I M, the number of inputs?
I k, the number of state
bits?
I the number of possible
states of the machine?
I N, the number of output
bits?
I next-state equations?
I output equations?
ENEL 353 F15 Tutorial Slides for Week 10
slide 7/11
Exercise 2, continued
CLK
A
S00
S0
S10
S1
S20
S2
r
R
1
CLK
R
A
0
1
0
1
0
Let’s add waveforms for S0 ,
S1 and S2 to the timing
diagram.
Y
Let’s assume synchronous
reset for the three DFFs in
the register.
ENEL 353 F15 Tutorial Slides for Week 10
slide 8/11
Remark about Exercise 2
We found the waveforms for S0 , S1 and S2 based on rules
about the behaviour of DFFs.
Next week in lectures, we’ll see another method for solving the
problem. The textbook calls this method, “Deriving an FSM
from its schematic.” Your instructors might sometimes call it
“FSM analysis.”
slide 9/11
ENEL 353 F15 Tutorial Slides for Week 10
Exercise 3: More DFF practice
CLK
Q0
A
r
Q1
r
Q2
r
R
Let’s add waveforms for Q0 , Q1 and Q2 to the timing diagram.
1
CLK
R
A
0
1
0
1
0
ENEL 353 F15 Tutorial Slides for Week 10
slide 10/11
Exercise 4: Simple FSM design
Design an FSM with a single output bit, such that
I on reset the output goes to 0;
I when reset is turned off, the output repeats the sequence
of 0 for one clock cycle, 1 for three cycles, 0 for one
cycle, 1 for three cycles, and so on.
ENEL 353 F15 Tutorial Slides for Week 10
slide 11/11
Next week
Tue Nov 17: Quiz #4—exact topics to be announced closer to
the date of the quiz.
Likely topics include SR latches, D latches, DFFs, and simple
FSM designs.
The Problem Set #4 exercises on sequential logic are highly
recommended as preparation.