WC4
17:45 – 18:00
Efficient Mode Converter for Coupling between Fiber and
Micrometer Size Silicon Waveguides
Assia Barkai1, Ansheng Liu2, Daewoong Kim2, Rami Cohen1, Nomi Elek1, Hsu-Hao Chang3,
Bilal H Malik4, Rami Gabay1, Richard Jones2, Mario Paniccia2 and Nahum Izhaky1
1. Intel corporation, S.B.I. Park Har Hotzvim, Jerusalem, 91031 Israel
2. Intel Corporation, 2200 Mission College Blvd.,. Santa Clara CA, 95054 USA
3. University of California Santa Barbara, ECE Department, Santa Barbara, CA 93106, USA
4. Dept of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843,
USA
Abstract
A low-loss polarization independent mode converter for coupling standard single
mode fiber to a silicon chip is presented. For a micrometer size silicon waveguide,
we demonstrate a coupling loss of 1-1.5 dB/facet.
I. Introduction
Silicon-on-Isolator (SOI) provides an attractive platform for the monolithic integration of optical
and electrical devices using the infrastructure and low-cost, high-volume, manufacturing
technologies from the microelectronics industry. The large difference between the refractive
indices of the core silicon and the SiO2 cladding enables the realization of small footprint optical
devices with micron and submicron waveguide dimensions. However, coupling light to small
waveguides (WG) with ~1µm2 dimensions is challenging especially from standard single mode
fiber (SMF) which has a symmetrical mode field with a diameter of 9µm, the large modal
mismatch between SMF and 1 µm silicon waveguide leads to at least 14dB coupling loss. Fig. 1
shows the adiabatic mode conversion needed between a standard SMF mode and an SOI rib
waveguide.
Fiber Output
Middle
WG input
~10 µm
Fig. 1 Mode convert: left fiber mode right WG mode.
~1 um
Several mode converters have been suggested in the literature to reduce the coupling loss of SMF
to micron and submicron WG’s. They include waveguide gratings [1], inverse tapers for
submicron WG’s (~ 0.2µm) [2],[3] and a dual-grating assisted directional coupler [4]. These
solutions all require some trade-offs, being either polarization dependent, having limited
bandwidth or requiring challenging process requirements and new material development, e.g.
polymers, which are unsuitable for CMOS fabrication facilities.
We have developed a two-dimensional tapered-WG mode converter [5-7] which has very low
polarization dependence, is compatible with CMOS processing, and can be easily integrated with
other active and passive silicon based devices. The taper design consist of a double stage taper,
1-4244-0935-7/07/$25.00©2007 IEEE
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DST, with 3 processing steps: 1) bottom taper (BT); 2) WG definition; and 3) upper taper (UT)
(Fig. 2). This paper describes the design, process and optical testing of the DST. The processing
of such device is not trivial, creating two stage of taper with low WG damage. We achieved
polarization independent 1.5dB/facet total taper loss, using standard SMF. Moreover, the taper
performance preserved over a wide wavelength range (1.31, 1.55µm)
Tip
UT
H2
BT
h
H1
∆L
L
Rib
Fig. 2: A DST design rule, lower part 12µm width is the WG input; BT is the lower taper with input of
12µm and UT with the input of 11µm. ∆L=150µm represent the spacing between the tip of the BT to UT.
Where h=1.5µm, H1=2.5µm and H2=5.5µm.
II. Design and Fabrication
The DST design was optimized for 1-1.5 µm2 WG’s, and considers taper dimensions at the device
facet and at the WG input. At the device facet, the dimensions should be close to the near field
SMF mode, and the at the WG input the taper tip should be as small as possible to prevent any
additional loss. Our simulations show low loss performance for taper tip size of 0.3µm. The
taper length should be long enough for adiabatic 2D conversion from the 12µm taper input to tip
dimensions.
DST processing starts with SOI wafers with 4.0µm (+/-0.1µm) Epi-silicon layer and 1µm buried
oxide layer. Silicon dioxide is used as hard mask for the BT etch. Here the silicon etch depth is
targeted to 2.50um (+/- 0.08um) with 90 deg side walls angle, producing WG with a final height
of 1.5um. Next the Rib WG’s are formed by additional silicon dioxide deposition, oxide etch
and silicon dry etch of 0.700µm (+/-0.025um). At this stage low stress silicon dioxide is
deposited as cladding layer for passive device. For active device, silicon implant and
metallization is performed. During UT growth, it is important to protect the rib WG and the BT
by silicon dioxide. Final processing steps are: seed opening for DST silicon epitaxial growth and
UT dry etch (Fig.3). The most delicate process step is the BT etch, which has the potential to
cause WG surface damage, and increase the propagation loss. Several silicon etch recipes have
been developed with different chemistries to achieve a low loss WG. Fig. 3 shows a top view
SEM of the DST taper at the tip area. As illustrated in Fig. 2, the first taper stage is wider than
the second taper stage, keeping the top surface area smooth.
WG
BT
UT
BT
WG
WG
UT
UT TIP
Fig.3: a. left, SEM cross section of the DST; b. center, SEM top view of UT tip; c. right, tilt image of BT
WG
and UT tip.
2
50
DCW
Taper
BT Tip
III. Results and Conclusions
Optical testing is performed by using cleaved SMF, the taper to WG transition loss; waveguide
propagation loss and fiber to taper facet coupling loss are measured using the Fabry-Perot
method. Taper transition loss is calculated by subtracting the loss of the straight WG without
tapers to the tapered WG loss. Figure 4 shows the variation of total taper loss (coupling + taper
transition loss) with taper length. Experimental results show that this DST taper is polarization
insensitive and can operate over a wide wavelength range at 1.31µm and across the full c-band.
The optimal taper length is 1050µm revealing loss of 1.5dB/facet.
dB/facet
972T17-28
4
3.5
3
2.5
2
1.5
1
0.5
0
TE
TM
1250
1150
1050
950
850
750
650
550
Taper Length
Fig. 4: Total DST loss/ facet vs. taper length for TE and TM polarization, measured at 1.55µm.
This taper design can be optimized by using antireflective coatings and modifying the cross
section at the taper facet. Once the reflections and mode mismatch losses are minimized the main
remaining loss is the taper transition loss, which is very low, ~1dB/Facet, as shown in our work.
DST has several packaging applications; the taper configuration enables integration of coupling
parallel components to silicon device such as, edge emitting laser and fiber placement in vgroove, supported by the same SOI substrate
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