Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with
Four {111} Facets by Dry Etch Technology
Yao-Jen Lee1*, Fu-Ju Hou1, 2, Shang-Shiun Chuang2, Fu-Kuo Hsueh1, 3, Kuo-Hsing Kao4, Po-Jung Sung1, 3,
Wei-You Yuan5, Jay-Yi Yao1, Yu-Chi Lu3, Kun-Lin Lin1, Chien-Ting Wu1, Hisu-Chih Chen1, Bo-Yuan
Chen1, Guo-Wei Huang1, 2, Henry J. H. Chen5, Jiun-Yun Li6, Yiming Li7, Seiji Samukawa8, Tien-Sheng
Chao3, Tseung-Yuen Tseng2, Wen-Fa Wu1, Tuo-Hung Hou2, and Wen-Kuan Yeh1
1
National Nano Device Laboratories, Hsinchu, Taiwan; 2Dept. of Electronics Engineering & Institute of Electronics, National
Chiao Tung University, Hsinchu, Taiwan; 3Dept. of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan; 4Dept. of
Electrical Engineering, National Cheng Kung University, Tainan, Taiwan; 5Dept. of Electrical Engineering, National Chi Nan
University, Nantao, Taiwan. 6Dept. of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan
University, Taipei, Taiwan; 7Dept. of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan;
8
Institute of Fluid Science, Tohoku University, Sendai, Japan. Tel: +886-3-5726100-7793, Fax: +886-3-5722715, *Email:
[email protected]
Abstract
We propose a feasible pathway to scale the Ge MOSFET
technology by using a novel diamond-shaped Ge and Ge0.9Si0.1
gate-all-around (GAA) nanowire (NW) FETs with four {111}
facets. The device fabrication requires only simple top-down
dry etching and blanket Ge epitaxy techniques readily available
in mass production. The proposed dry etching process involves
three isotropic/anisotropic etching steps with different Cl2/HBr
ratios for forming the suspended diamond-shaped channel.
Taking advantages of the GAA configuration, favorable carrier
mobility of the {111} surface, nearly defect-free suspended
channel, and improved dopant activation by incorporating Si,
nFET and pFET with excellent performance have been
8
demonstrated, including an Ion/Ioff ratio exceeding 10 , the
highest ever reported for Ge-based pFETs.
Introduction
High-mobility channel materials, such as Ge, and multigate device configurations, such as FinFETs or GAA NWFETs,
are proposed to extend the Moore’s law beyond the 10-nm
technology node [1-4]. However, the Ge MOSFET technology
is facing several serious challenges, including fast n-type
dopant diffusion, high junction leakage, and enormous
dislocation defects in the Ge epi-layer because of the large
lattice mismatch to Si. Furthermore, the {111} channel surface
is favorable for Ge MOSFETs because of its higher electron
mobility and comparable hole mobility compared with the
{100} surface [5, 6]. However, fabricating GAA Ge NWFETs
completely on the {111} surface has yet to be demonstrated [3].
In this work, a simple dry etching technique was utilized to
form NWs with highly tunable shapes on blanket epitaxial
layers. The fabricated GAA Ge NWFET exhibits the following
unique features: (1) Accomplishing a diamond-shaped GAA
978-1-4673-9894-7/15/$31.00 ©2015 IEEE
configuration with four {111} facets. (2) Achieving a nearly
defect-free epitaxial channel by removing the dislocations near
the Si/Ge interface. (3) Incorporating 10 % Si in Ge to improve
dopant activation and dielectric interface. Record-high Ion/Ioff
8
ratio of pFET > 10 and promising nFET performance have
been demonstrated.
Nanowire Formation and Device Fabrication
Figs. 1 and 2 show the process flow used for fabricating
diamond-shaped GAA Ge NWFETs and rectangular FinFETs.
The un-doped Ge (Ge0.9Si0.1) epitaxial layers of 120 nm were
deposited on the (001) SOI wafers after thinning the thickness
of the SOI Si layer to 20 nm by wet oxidation. The epitaxial
layer was patterned into desired NW shapes by using e-beam
lithography and dry etching. After the hard-mask (HM)
opening, the rectangular fin was formed by anisotropic plasma
etching using Cl2/O2, while the diamond-shaped NW was
formed using a three-step etching process. Fig. 3a shows the
first isotropic etching step using Cl2/HBr formed a triangular
ridge self-saturated at two {111} facets. The second anisotropic
step using Cl2 and chuck bias formed a tower-shaped pillar.
The final self-saturated isotropic etching step using Cl2/HBr
undercut the dislocated Ge region near Si and completed the
suspended diamond-shaped NW as shown in Fig. 3b. The
cross-sectional SEM images (Fig. 4) show ideal intersection
o
o
angles of 70.5 and 109.5 among four {111} facets in the [110]
zone axis, which is also confirmed by selected area diffraction
pattern (SADP) as shown in Fig. 3c. The short diagonal is
defined by the mask width WMASK, and the length of the long
diagonal is 1.41 times of WMASK. The suspended height HNW can
be designed using the Ge thickness, WMASK, and the Ge recess
during the HM etching to achieve nearly defect-free Ge
channels. To fabricate GAA NWFETs, after GeO2/Al2O3/TiN
gate formation, the S/D regions were implanted with boron for
15.1.1
IEDM15-382
pFETs and phosphorous for nFETs, and activated by RTA at
550°C for 30s. Fig. 5 shows the TEM images of the fabricated
diamond-shaped GAA NWFET and rectangular FinFET.
Characteristics of Ge and Ge0.9Si0.1 GAA NWFETs
Fig. 6 shows the Ioff of Ge GAA p-type NWFETs can be
effectively suppressed by removing the defective Ge region
when WMASK ≤ 35 nm. The apparent Ioff reduction of 4 orders of
magnitudes was achieved in the nearly defect-free diamondshaped GAA NWFETs compared with the rectangular FinFETs.
Fig. 7 shows the Id-Vg characteristics of the Ge GAA p-type
NWFET with WMASK/L=20 nm/100 nm. The extremely low Ioff
8
was obtained, resulting in a record-high Ion/Ioff ratio of 10
among all reported Ge-based pFETs, and far superior to the
4
rectangular FinFETs with an Ion/Ioff ratio of 4.1 × 10 (the inset
in Fig. 7). For nFETs, the diamond-shaped GAA NWFET
4
2
shows an Ion/Ioff ratio of 1.8 × 10 , as compared with 2.3 × 10
for the rectangular FinFET as shown in Fig. 8. This is because
of the improved electron mobility and reduced interface states
Dit near the conduction band [6], in addition to the dislocation
removal. Fig. 9 shows well-behaved Id-Vd curves for both
diamond-shaped Ge GAA nFET and pFET.
The effect of Si incorporation was also investigated using
10 % Si during the Ge epitaxial growth. Figs. 10 (a) and (b)
show the reciprocal spacing maps (RSMs) with symmetric and
asymmetric planes for GexSi1-x. Both symmetric (004) and
asymmetric (224) data indicate the Si composition of Ge0.9Si0.1.
The SIMS analysis displays the uniform Ge and Si profiles
with a depth of 120 nm in the Ge0.9Si0.1 epitaxial film, as shown
in Fig. 11. Fig. 12 shows that similar diamond-shaped GAA
NWFETs in the [110] zone axis can be fabricated using the
Ge0.9Si0.1 film and similar three-step etching process, except
that the etching rate was slightly lower for the Ge0.9Si0.1 film
than that for the pure Ge film.
Fig. 13 shows the sheet resistance comparison between
2
pure Ge and Ge0.9Si0.1. Boron of 1 x 15 cm 10 KeV and BF2 of
2
1 x 15 cm 15KeV were implanted into the undoped Ge and
Ge0.9Si0.1 epitaxial layers, respectively. The as-implanted sheet
resistance of four samples were about 18 ~ 24 k /square. After
performing the RTA process from 500℃ to 700℃, the lower
sheet resistance of Ge0.9Si0.1 with the same implant condition
suggests a higher efficiency of dopant activation in Ge0.9Si0.1
compared to pure Ge. The Hall effect measurement estimated
19
-3
the carrier concentration of boron implant was 3.81 × 10 cm
20
-3
for Ge and 1.23 × 10 cm for Ge0.9Si0.1 at the RTA temperature
of 600℃. Compared to the pure Ge device, the Ge0.9Si0.1 device
shows improved S. S. (Fig. 14) and 2.25x enhancement of Ion
(Fig. 15), which is attributed to the reduced parasitic S/D
resistance and improved dielectric interface by incorporating Si.
IEDM15-383
In a device with WMASK/L= 35 nm / 70 nm, Ion can be improved
to 607 μA/μm at Vg-Vt = -2 V and Vd = -2 V (Fig. 16). Larger
WMASK reduces parasitic S/D resistance but adversely affects Ioff
when HNW is not sufficient. This tradeoff can be resolved when
the S/D germanide is adopted. Fig. 17 demonstrates excellent
short channel control down to L = 50 nm with WMASK = 20 nm
by using the GAA configuration. These superior results suggest
the excellent scalability to Ge-base FETs. Table 1 compares
the performance of the Ge & Ge0.9Si0,1 GAA NWFETs of this
work with previous studies, showing the higher Ion/Ioff ratios for
both pure Ge and Ge0.9Si0.1 diamond-shape p-type NWFETs.
Conclusion
This work proposes a feasible pathway to scale Ge
NWFETs beyond the 10 nm node. The GAA configuration
provides excellent electrostatics. The suspended diamondshaped NW channel utilizes only the favorable {111} surfaces
with high carrier mobility and low Dit and undercuts the
dislocations near the Si/Ge interface. The Si incorporation
improves dopant activation and dielectric interface. More
importantly, the device can be fabricated easily using the
simple dry etching and blanket Ge epitaxy techniques.
Acknowledgement
The authors would like to thank DSG Technologies for the
useful suggestions, and support by Ministry of Science and
Technology (MOST 103-2221-E-492 -045 and MOST 1042221-E-492 -015). T.-H. Hou acknowledges support by
NCTU-UCB I-RiCE program, under grant MOST 104-2911-I009-301.
References:
[1] J. W. Peng et al., “CMOS Compatible Ge/Si Core/Shell Nanowire GateAll-Around pMOSFET Integrated with HfO2/TaN Gate Stack,” in IEDM
Tech. Dig., p. 931, 2009.
[2] Shu-Han Hsu et al., ”Nearly Defect-free Ge Gate-All-Around FETs on Si
Substrates,” in IEDM Tech. Dig., p.825, 2011.
[3] Shu-Han Hsu et al., “Triangular-channel Ge NFETs on Si with (111)
Sidewall-Enhanced Ion and Nearly Defect-free Channels,” in IEDM Tech.
Dig. , P. 525, 2012.
[4] Sylvain Barraud et al., “Top-Down Fabrication of Epitaxial SiGe/Si Multi(Core/Shell) p-FET Nanowire Transistors,” IEEE Trans. Electron Devices,
vol. 61, no. 4, p.9535, Apr. 2014.
[5] A. Toriumi et al., “Material Potential and Scalability Challenges of
Germanium CMOS,” in IEDM Tech. Dig., p646, 2011.
[6] Khairul Alam et al., “A Ge Ultrathin-Body n-Channel Tunnel FET: Effects
15.1.2
of Surface Orientation,” IEEE Trans. Electron Devices, vol. 61, no. 11, p.
3594, 2014.
Nanowire Formation & Process Flow
zEpitaxial of 120nm Ge or Ge0.9Si0.1
on SOI and deposit hard mask
zNW patterning by E-beam (a) and
hard mask etching
zNW Formation:
1. Etch 1 (Cl2/ HBr) (b)
w/o bias/isotropic
(111)
(111)
2. Etch 2 (Cl2 only) (c)
(111)
(111)
w/ bias/anisotropic
3. Etch 3 (Cl2/ HBr) (d)
w/o bias/isotropic
Etch 2
(Cl2 Only)
Anisotropic
Etch 1
(Cl2/ HBr)
Isotropic
(b)
PR
Etch 3
(Cl2/ HBr)
Isotropic
(c)
Fig. 2. Schematic flow for Ge
diamond-shaped
NWFETs
and rectangular FinFETs. (a)
120-nm Ge and Ge0.9Si0.1
grown on (001) SOI (Si 20
nm). (b) & (b)' NW
patterning and etching using
isotropic
Cl2/HBr
for
diamond-shaped NWs and
anisotropic
Cl2/O2
for
rectangular
fins
(c)
Anisotropic etching using Cl2
gas only, (d) Isotropic Cl2/
HBr etching. (e) & (e)' Gate
formation with high k/metal
gate stack.
Gate formation
and patterning
(e)
(d)
SOI
(b)'
(e)'
(100)
Etch for rectangular
(b)'
fin(Cl2/O2)
w/ bias/anisotropic
*Ratio of Cl2/ HBr in Etch 1> Etch 3.
*Etch time: Ge0.9Si0.1> Ge.
*Side wall passivation formed by O2
in anisotropic etch.
zPR & hard mask removal
zGeO2 500°C 30s oxidation
zAl2O3 deposition by ALD
zTiN deposition & gate patterning
(e)& (e)'
S/D implantation & annealing
nFETs: 31P/1E15/15 KeV
pFETs: B/1E15/10 KeV
RTA 550 °C 30s
(110)
(a)
(110)
Rectangular fin
etch (Cl2/ O2)
Anisotropic
Gate formation
and patterning
Self-saturated at {111} plane
Isotropic
etching
Ge
Ge
Ge
Isotropic
etching
Si
(a)
BOX
50nm
Fig.1 Process flow of p & n-channel Ge
NWFETs fabrication. The three dry
etching steps using Cl2/ HBr to form the
suspended diamond-shaped channel are
highlighted.
(b)
50nm
Ge
Si
(c)
BOX
Fig. 3 (a) Isotropic Etch 1 self-saturated at {111} forms the two top facets of the rhombus. (b) Isotropic Etch 3 selfsaturated at {111} forms the two bottom facets of the rhombus. (c) Cross-section TEM image for the Ge diamond-shaped
NW in the [110] zone axis. SADP in the inset of (c) identifies the {111} planes of the NW surface.
70.5o
50 nm
(1-1-1)
BOX
Ioff (μA/μm)
10
(a)
-1
Defect
-4
10
-3
10
-5
10
I on/Ioff
Ge GAA pNWFETs
Ge pFinFETs
-7
10
-8
20
30
40
WMASK (nm)
50
60
Fig. 6 Ioff vs. WMASK. Ioff can be effectively
suppressed as WMASK scales below 35 nm by
removing dislocations near the Si/Ge interface.
Vd= -0.1 V
8
2
Vd = -1 V
Ge pFinFETs
10
V d = − 0.1 V
-5
Io n/Io ff
-2
10
-7
10
-2
-2
-1
-1
0
(b)
BOX
1
2
10
1
Vd = 0.1V
10
0
Vd = 1 V
W MASK/L = 45 nm / 80 nm
3
10
2
10
-1
0
1
2
Fig. 7 Id-Vg characteristics of the Ge GAA p-type
NWFET with WMASK/L = 20 nm/90 nm. The Ge
GAA device shows a much improved Ion/Ioff ratio
compared to the Ge FinFET shown in the inset.
15.1.3
Ge nFinFETs
10
10
10- 2
-0.5
0.0
= 1.8 × 10
= 2.3 × 102
10- 1
-3
4
Ion /Iof f
0
-2
Ion/Ioff
Vd = 0.1 V
1
10
2
Vg (V)
BOX
Ge GAA nNWFETs
10
10
= 4.1× 104
-4
10
Si
10
0
10
10
-6
10
WMASK/L = 20 nm/ 90 nm
= 5.1 × 10
Fin
Fig. 5 Cross-sectional TEM images of diamond-shaped
NWFET and FinFET.
Ge GAA pNWFETs
1
10
-3
10
10
10
(1-10) Ge (-110)
(-11-1)
Si
Drain Current (μA/ μm)
-2
Drain Current (μA/μ m)
-1
Ge
GeO2/Al2O3
1.4 WMASK
Fig. 4 Suspended height of NW is tunable using the Ge thickness, WMASK, and the Ge recess during
the HM etching to achieve nearly defect-free Ge channels. The more Ge recess during HM opening
is, the smaller suspended height becomes.
10
(001)
(-111)
(1-11)
Suspended
Height
H=0
Si
20 nm
Si
TiN
TiN
109.5o
WMASK
Ge
Suspended
Height H
(-111)
-1
0.5
0
1
1.0
Vg (V)
2
1.5
2.0
Fig. 8 Id-Vg characteristics of the Ge GAA n-type
NWFET with WMASK/L = 45 nm/80 nm. The Ge
GAA device shows a much improved Ion/Ioff ratio
compared to the Ge FinFET shown in the inset.
IEDM15-384
Drain Current (μA/μm)
80
Ge GAA pNWFETs
Ge GAA nNWFETs
WMASK/L = 20 nm/ 90 nm WMASK/L = 45 nm / 80 nm
60
Vg − Vt = 0 ~ −2 V
Vg − Vt = 0 ~ 2 V
Vstep = −0.4 V
Vstep = 0.4 V
40
20
0
-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00
Vd (V)
Fig. 10 Reciprocal spacing map (RSM) with symmetric and asymmetric planes for GexSi1-x.
(a) symmetric (004), and (b) asymmetric (224) data indicate th
he composition of Ge0.9Si0.1.
as-implanted
26000
100
80
40
SiO2
Si
Ge0.9Si0.1
20
0
0
50
100
150
Vd = − 0.1 V and − 1 V
S.S = 142 mV / decade
0
10
10
-2
10
-4
10
-6
10
-8
S.S = 167 mV / decade
Ge0.9Si0.1 GAA pNWFETs
Ge GAA pNWFETs
WMASK/L = 20 nm / 100 nm
-2.0 -1.5 -1.0 -0.5
0.0
Vg (V)
0.5
1.0
1.5
Open: DIBL
Solid: S.S.
250
150
100
100
0
Ge0.9Si0.1 GAA pNWFETs
1
100
Ge GAA pNWFETs
WMASK/L = 20 nm / 100 nm
50
50
100
150
Channel Length (nm)
200
400
19
-3
Bact. coon. = 3.81 × 10 cm
300
200
100
20
-3
Bact. conn. = 1.23 × 10 cm
0
500
550
Vg − Vt = 0 ~ − 1.6 V
600
o
650
700
Ge0.9Si0.1 GAA pFETs
WMASK/L = 35nm / 70nm
Vg-Vt= 0 ~ -2V
400
Vstep = − 0.4 V
Vstep= -0.4V
300
200
40
100
20
0
607μA/μm
500
60
Fig. 17 GAA NWFETs suppress the degradation of S.S. annd
DIBL because of the excellent electrostatics.
IEDM15-385
2.25X
80
0
-2.0
-1.5
-1.0
Vd (V)
-0.5
0.0
Figg.15 Id-Vd characteristics of the p-type Ge &
Ge00.9Si0.1 GAA NWFETs with WMASK/L = 20
nm//100 nm.
200
200
BF2 in Ge0.9Si0.1
600
1
120
300
Ge0.9Si0.1 GAA pNWFETs
BF2 in Ge
Fig.13 The sheet resisttance (Rs) value of Ge0.9Si0.1 is
lower than that of Gee because of the higher dopant
activation efficiency. The estimated activation
concentration of boron in Ge0.9Si0.1 is 1.23×1020 cm-3.
Fig. 12 Ge0.9Si0.1 diamond-shaped NW in
the [110] zone axis.
S. S. (mV/decade)
300
B in Ge
B in Ge0.9Si0.1
Teemperature ( C)
Fig. 14 Id-Vg characteristics of the p-type Ge &
Ge0.9Si0.1 GAA NWFETs with WMASK/L = 20
nm/100 nm, showing improved Ion and S.S by
using Ge0.9Si0.1.
400
-2
500
0
Drain Current (μA/μm)
Drain Current (μA/μ m)
2
10
600
200
Depth (nm)
15
B : 1×10 cm
m @ 10keV
15
-2
BF2 : 1×10 cm
c
@ 15keV
Drain Current (μA/μm)
Si
Ge
60
Fig. 11 SIMS profiles of the GSOI substrate, showing
uniform Si and Ge profiles with a near 90% Ge content.
DIBL (mV/V)
Sheet Resistance (Ω/square)
Concentration Persentage (atom%)
Fig. 9 Id-Vd of the diamond-shaped Ge GAA n-type and
p-type NWFETs.
0
-2.0
-1
1.5
-1.0
-0.5
Vd (V)
0.0
Fig.16 Id-Vd characteristics of the p-type Ge0.9Si0.1
GAA NWFETs wiith WMASK/L = 35 nm/70 nm.
Table 1 Comparison of the device characteristics of Ge & Ge0.9Si0,1 GAA NWFETs in this work with
previous studies.
Ref [1]
Material
Ge
Ref [2]
Ge/Si
(core/shell)
Ref [4
4]
This work
Ge
Si0.7Gee0.3
Ge
Ge0.9Si0.1
Diamond-shaped
GAA
Diamondshaped GAA
Structure
NW-Ω Gate
NW-GAA
Triangular-GAA
onal
Hexago
Multi-Corre/Shell
Dielectric
7nm GeO2/
11 nm HfO2
11nm HfO2
4nm GeO2/
3nm Al2O3
1.9nm HffSiON
GeO2/
3nm Al2O3
GeSiO2/
3nm Al2O3
WFin (nm)
14 (Diameter)
35 (Diameter)
52
~ 25
5
20
20
Lg (nm)
300
200
183
15
100
100
Ion/Ioff
~106
~104
~105
105
SS (mV/dec.)
92
160
130
15.1.4
>
100
>
108
167
> 107
142