Tutorial 6
Flip-Flops and Sequential Logic Circuits
Question 1
a)
Explain the differences between a combinational with a sequential logic circuit.
b)
What are the advantages of sequential logic circuit over combinational logic circuit?
c)
Derive the truth-table for the SR latch shown.
Question 2
a)
Draw the diagram of a JK flip-flop. Hence, draw its truth table.
b)
Why clock is important in the operation of a JK flip-flop?
c)
Is there any difference between a positive edge triggered with the negative edge
triggered JK flip-flop? If yes, explain.
d)
JK inputs are called synchronous inputs, what does this means?
e)
Most flip-flop have asynchronous inputs, describe what are these inputs.
f)
Why JK flip-flop is regarded as the universal flip-flop?
Question 3
If the following waveforms are applied to the JK flip-flop, determine the output Q,
assuming the flip-flop is initially reset and the SET and CLR inputs are low.
CLK
J
SET
Q
J
K
K
CLR
Q
Question 4
Draw the timing diagram of a positive edge triggered JK flip-flop for 5 clock pulses when
both of its input J=K=1.
Repeat for a negative edge triggered JK flip-flop. Are the results the same? If not, why?
Question 5
a)
What is an asynchronous counter? What is the MOD number of a counter?
i)
What a ripple counter?
ii)
What is a ring counter?
iii)
What is a register?
iv)
What is Johnson counter?
v)
What is a Cascaded counter?
b)
Design an asynchronous counter that counts 0-1-2-3-4-5 continuously. Draw the
circuit diagram using T flip-flops and its timing diagram.
If the count is changed to 0-1-5-6-7, how would you redesign the circuit?
Hint: When the count reaches 2, make the count jump to 5.
FlipFlopsandSequentialCircuits/page 1 of 2
Question 6
Using T flip-flops, design a ripple counter that count up from 3 to 6. Show the timing
diagram of the counter for at least 8 clock pulses. Assume the counter initially starts from 5.
All unused states are regarded as don’t care states.
Question 7
a)
Explain the differences between an asynchronous with a synchronous counter.
b)
Design a synchronous counter that counts 0-1-2-3-4-5-6-7 continuously. Draw the
circuit diagram using JK flip-flops and its timing diagram.
Question 8
Design a synchronous counter that counts 0-1-3-5-6-7 continuously. Draw the circuit
diagram and its timing diagram. The unused states must jump to count 0. Implement the
counter using:
i) JK flip-flops
ii) D flip-flops.
Compare the two circuit.
Question 9
Design a 3-bit up-down counter using D flip-flops. The input X acts as the controller for
counting up or down, if equal to 0 will cause the counter to count up and if equal to 1 will
count down.
Question 10
Design a 3-bit up-down counter using JK flip-flops. The input AB acts as the controller in
which will control the counter as follows:
AB
Counter action
00
Counter reset to 0
01
Counting up
10
Counting down
11
Counting stop at the current count
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