Course Topics - Outline
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Lecture 1 - Introduction
Lecture 2 - Lexical conventions
Lecture 3 - Data types
Lecture 4 - Operators
Lecture 5 - Behavioral modeling
Lecture 6 - Data flow modeling
Lecture 7 - Gate Level modeling
Lecture 8 - Tasks and Functions
Lecture 9 - Advanced Modeling Techniques
Lecture 10 - System Tasks and Compiler directives
Lecture 11 - Switch Level modeling
Lecture 12 - Coding Styles and Test Benches
Lecture 13 - Synthesis issues
1
Lecture 2 – Lexical conventions
 Case sensitivity, Keywords, White space Characters
 Identifiers
 Comments
 Integer Numbers
 Signed and Unsigned Numbers
 Real Numbers
 Strings
 Verilog Logic Value Set
 Integer Arithmetic
 Exercise 2
2
Lexical conventions
 The basic lexical conventions used by Verilog HDL are
similar to those in the C programming language.
 Verilog HDL is a case-sensitive language.
 All keywords are in lowercase.
 White space characters are:
 Blank
spaces
 Tabs
 New-line
3
Verilog Statement Terminator
 Verilog models consist of a list of statements declaring
relationships between a model and its environment,
and between signals within a model.
 Statements are terminated by a semicolon( ; )
module full_addr (A, B, Cin, S, Cout) ;
input
A, B, Cin ;
output wire S, Cout ;
assign {Cout, S} = A + B + Cin ;
endmodule
4
Identifiers
 Identifiers are names given to an object, such as a
register or a function or a module, so that it can be
referenced from other places in a description
 Identifiers must begin with an alphabetic character or
the underscore character (a-z A-Z _ )
 Identifiers may contain alphabetic characters, numeric
characters, underscore, and dollar sign (a-z A-Z 0-9 _ $ )
 Identifiers can be up to 1024 characters long
 Identifier cannot start with a number or dollar sign ($)
 Escaped Identifiers begin with backslash (\) and end
with white space (space, tab or new line)
5
Identifiers cont.
 All characters within the Escape Identifier, are
processed literally. Any printable ASCII character can be
included.
 Identifiers examples:
wire a1 ;
reg sum ;
// wire is a keyword, a1 is an identifier
// reg is a keyword, sum is an identifier
 Escaped Identifier examples:
\a+b-c
\**my_name**
6
Comments
 There are two forms to introduce comments.
o
Single line comments begin with the “// “and end
with a carriage return.
// This is one line comment
o
Multi Line comments begin with the “/*” and end
with the “*/”
/* This is a multiple
lines
comments */
7
Integer Numbers
Verilog HDL allows integer numbers to be specified as:
 Sized or Unsized numbers ( Unsized size is 32 bits )
 In a radix of binary, octal, decimal, or hexadecimal
 Radix and hex digits (a, b, c, d, e, f) are case insensitive
 Spaces are allowed between the size, radix and value
 Syntax: <size> '<radix> <value>
size in bits, radix in b, d, o, h
8
Number Representation
549
// unsized decimal number
‘h 8FF
// unsized hex number
‘o765
// unsized octal number
4 ’b11
// 4-bit binary number 0011
3 ’b10x // 3-bit binary number with LSB unknown
5 ’d3
// 5-bit decimal number
-4 ’b11 // 4-bit two’s complement of 0011 = 1101 = 4’hd
9
Integer Numbers - Examples
 Unsized Numbers:
792
// a decimal number
8d9
// Illegal, hexadecimal must be specified with ‘h
‘h 7d9 // an unsized hexadecimal number - 000007d9
‘o 7746 // an unsized octal number - 00000007746
1
// stored as 00000000000000000000000000000001
 Sized Numbers:
12 ‘h x
// a 12 bit unknown number
10 ‘d 17 // a 10 bit constant with the value 17
4 ‘b 110z // a 4 bit binary number
8’hAA
// stored as 10101010
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Integer Numbers (2)
 If size is ommitted:
 It
is inferred from the value or
 It
takes the simulation specific number of bits or
 It
takes the machine specific number of bits (32/64b)
 If radix is ommitted too, decimal is assumed
 15
11
= <size> ’d 15
Integer Numbers (3)
 One can insert “_” to improve readability,
12 ’b 000_111_010_100
12 ’b 000111010100
12 ’o 07_24
 “?” question mark – substitutes z in numbers for better
readability: 8 `b111?
// == 8 `b111Z
 Zero fill / bit extension: If a numeric value does not contain
enough digits to fill the specified number of bits, the high
order bits are filled with zeros. If the specified MSB is an x
or z, the x/z is left extended to fill the bit field.
16 ’h39  16 ’h0039  16 ’b0000 0000 0011 1001
8 ’hz  8 ’hzz  16 ’bzzzz zzzz
12
Signed and Unsigned Numbers
 Verilog Supports both the type of numbers, but with
certain restrictions.
 Any number that does not have negative sign prefix is
a positive number. Or indirect way would be
"Unsigned"
 Negative numbers can be specified by putting a minus
sign before the size for a constant number, thus
become signed numbers.
 Verilog internally represents negative numbers in
2's compliment format.
1313
Verilog Essentials by Dr. Abramov B.
Signed and Unsigned Numbers Examples
 Negative numbers (- sign before the size) are represented
in 2's complement form.
Any number without a – sign is an unsigned number
-4’d7
-6sd3
4’d-2
-5’ha
// stored as 1001
// used for performing signed integer math
// Illegal specification
// stored as 10110
-4’b101
// stored as 1011
 wire signed [N-1:0] din ; // a net that holds a signed value
 reg signed [M-1:0] dout ; /* a variable that holds a signed
value */
14
Real Numbers
 Verilog supports real constants and variables
 Real Numbers can not contain 'Z' and 'X'
 Real numbers may be specified in either decimal or
scientific notation:
<
value >.< value >
<
mantissa >E< exponent >
 Verilog converts real numbers to integers by rounding.
 Real numbers are rounded off to the nearest integer
when assigning to integer.
15
Real Numbers - Examples
Real Number
Decimal Notation
1.2
1.2
0.6
0.6
3.5E6
3500000.0
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String
 A sequence of characters enclosed in double quotes.
Must be contained in a single line (w/o carriage return).
String is treated as a sequence of one-byte ASCII values.
Example: “Verilog HDL Concepts”
 Verilog strings are implemented with regs. The reg
holds the ASCII values of each character of the string.
reg [8*12:0] string_val;
// can hold up to 13 chars
string_val = “Hello Verilog”;
string_val = “hello”;
// MS Bytes are filled with 0
string_val = “I am overflowed”; // “I ” is truncated
 Accept C-like escape characters: \n = newline, \t = tab,
\b = backslash, \” = quote mark (“), %% = % sign
17
Verilog Value Set
0
represents low logic level or false condition
1
represents high logic level or true condition
X
represents unknown logic level
Z
represents high impedance logic level
18
Four-valued Logic
 Logical operators work on three-valued logic
0
1
X
Z
19
0
0
0
0
0
1
0
1
X
X
X
0
X
X
X
Z
0
X
X
X
Output 0 if one input is 0
Output X if both
inputs are gibberish
The Power of Verilog: Integer Arithmetic
 Verilog’s built-in arithmetic makes a 32-bit adder easy:
module add32 (a, b, sum) ;
input [31:0] a, b ;
output wire [31:0] sum ;
assign sum = a + b ;
endmodule
 A 32-bit adder with carry-in and carry-out:
module add32_carry (a, b, cin, sum, cout) ;
input [31:0] a, b ;
input cin ;
output wire [31:0] sum ;
output wire cout ;
assign {cout, sum} = a + b + cin ;
endmodule
20
Quiz – Practice
 Practice writing the following numbers:
1. Decimal number 123 as a sized 8-bit number
in binary.
Use _ for readability.
8’b0111_1011
2. A 16-bit hexadecimal unknown number
with all x’s.
16’hX
3. A 4-bit negative 2 in decimal.
Write the 2’s complement for this number.
-4’d2
4’d14
4. An unsized hex number 1234.
’h1234
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Quiz – Practice cont.
 Are the following legal strings?
If not, write the correct strings.
a. “this is a string ‘displaying
the % sign”
Not-legal, string must contain on a single line
b. “out = in1 + in2”
Legal
c. “Please ring the bell \007”
Legal
d. “This is a backslash \ character\n”
Not-legal, includes \n = new line
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Quiz – Practice cont.
 Are these legal identifiers?
a. system1
Legal
b. 1reg
Not-legal, starts with a digit (number)
c. $latch
Not-legal, starts with a $ sign
d. exec$
Legal
23
Quiz – Practice cont.
 Declare the following variables in Verilog:
a. An 8-bit vector net called a_in
wire [7:0] a_in ;
b. A 32-bit storage register called address.
Bit 31 must be the MSB (Little- Endian).
reg [31:0] address ;
c. Set the value of the register to a 32-bit decimal
number equal to 3
address = 32’d3 ;
d. An integer called count
integer count ;
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Quiz – Practice cont.
e. A time variable called snap_shot
time snap_shot ;
f. An-array called delays. Array contains 20 elements
of the type integer
integer delays[0:19] ;
g. A memory MEM containing 256 words of 64 bits each
reg [63:0] MEM[0:255] ;
h. A parameter cache_size equal to 512
parameter cache_size = 512 ;
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Exercise 2 – Half & Full Adders
 1bit Half Adder in Dataflow abstraction level
 1bit Full Adder in Dataflow abstraction level
 4bit Ripple carry Full Adder,
created from the above 4 1bit Full Adder units
 8bit Adder / Subtractor in Behavioral abstraction level
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