100GbE alignment markers
Pete Anslow, Ciena
IEEE P802.3cd Task Force, San Diego, July 2016
1
Introduction
nicholl_3cd_01_0716 proposes a similar alignment marker mapping to
FEC lanes as is used in Clause 91.
If the scheme is adopted as for Clause 91, this gives:
FEC lane 0
AM0 BIP AM0 BIP AM4 BIP AM4 BIP AM8 BIP AM8 BIP AM12 BIP AM12 BIP AM16 BIP AM16 BIP
Pad
Data
FEC lane 1
AM0 BIP AM0 BIP AM5 BIP AM5 BIP AM9 BIP AM9 BIP AM13 BIP AM13 BIP AM16 BIP AM16 BIP
Data
FEC lane 2
AM0 BIP AM0 BIP AM6 BIP AM6 BIP AM10 BIP AM10 BIP AM14 BIP AM14 BIP AM16 BIP AM16 BIP
Data
FEC lane 3
AM0 BIP AM0 BIP AM7 BIP AM7 BIP AM11 BIP AM11 BIP AM15 BIP AM15 BIP AM16 BIP AM16 BIP
Data
This contribution analyses the performance of this set of alignment
markers for 100 Gb/s Ethernet.
2
Baseline wander
Previous NRZ contributions have used a “baseline wander” parameter
This was defined as:
Baseline wander is the instantaneous offset (in %) in the signal
generated by AC coupling at the Baud rate / 10,000.
This analysis re-uses this definition unmodified, but it should be noted
that for PAM4, the eye height is 1/3 that of NRZ so the effects of a given
amount of baseline wander will be greater.
3
Clock content
The “clock content” parameter is defined here as:
Create a function which is a 1 for a transition and a 0 for no transition
and then filter the resulting sequence with a corner frequency of
Baud/5313 or Baud/13281.
This analysis defines a transition as one of three possibilities (as per
healey_3bs_01_1115):
• Symmetrical transitions through the signal average
• Transitions through the signal average
• All transitions
Filter with corner
frequency
Baud/5313 or
Baud/13281
Symbol
Stream
1 symbol
delay
Transition = 1
No transition = 0
Output
4
Clock content illustration
Symmetrical
transitions
through the
signal average
All transitions
Transitions
through the
signal average
5
Simulations
Using these alignment codes, all possible combinations of FEC lanes
for 4:1 bit interleaving for a 100 Gb/s lane were then analysed to find the
worst cases for Baseline Wander (BW) and Clock Content (CC) after
Gray coding to PAM4 symbols. These searches included lane delays of
-40 to +40 UI.
The worst case FEC lane combinations and delays were then used to
generate the worst case PDFs for 100 GbE scrambled idle over a single
100 Gb/s lane.
6
Scrambled idle construction
The scrambled idle symbol streams generated for this analysis were:
•
Idle control characters
•
Scrambled
•
256B/257B transcoded
•
Used to fill FEC codewords which start with alignment markers
followed by the 5 bit pad once in every 4096 codewords
•
BIP bits taken as random
•
300 bits of RS(544,514) FEC parity added
•
Interleaved 10 bits at a time to form FEC lanes
•
Bit interleaved with worst case FEC lane combinations and delays
The results for baseline wander and clock content are in the following
slides.
7
Baseline wander
10,000 year limit
10,000 year limit
1
Scrambled idle worst
case for max BW
0.01
0.0001
Scrambled idle worst
case for min BW
PRBS31Q
1E-08
Random
1E-10
1E-12
PRBS13Q
Probability of ocurrence
1E-06
1E-14
1E-16
1E-18
1E-20
1E-22
1E-24
Fit to
random
1E-26
-10%
-5%
0%
Baseline Wander
5%
10%
8
Clock, sym trans through ave, Bd/5313
10,000 year limit
10,000 year limit
1
0.01
0.0001
Scrambled idle worst
case for min CC
Scrambled idle worst
case for max CC
1E-06
Random
1E-10
1E-12
PRBS13Q
Probability of ocurrence
PRBS31Q
1E-08
1E-14
1E-16
1E-18
1E-20
1E-22
1E-24
Fit to
random
1E-26
0.10
0.15
0.20
0.25
Clock Content
0.30
0.35
0.40
9
Clock, sym trans through ave, Bd/13281
10,000 year limit
10,000 year limit
1
0.01
0.0001
PRBS31Q
Scrambled idle
worst case for
max CC
Random
1E-08
1E-10
1E-12
1E-14
1E-16
Scrambled idle
worst case for
min CC
PRBS13Q
Probability of ocurrence
1E-06
1E-18
1E-20
1E-22
Fit to
random
1E-24
1E-26
0.15
0.20
0.25
Clock Content
0.30
0.35
10
Clock, trans through ave, Bd/5313
10,000 year limit
10,000 year limit
1
0.01
Scrambled idle worst
case for min CC
0.0001
PRBS31Q
Random
1E-08
1E-10
1E-12
PRBS13Q
Probability of ocurrence
1E-06
Scrambled idle worst
case for max CC
1E-14
1E-16
1E-18
1E-20
Fit to
random
1E-22
1E-24
1E-26
0.25
0.35
0.45
0.55
Clock Content
0.65
0.75
11
Clock, trans through ave, Bd/13281
10,000 year limit
10,000 year limit
1
0.01
0.0001
Random
PRBS31Q
1E-08
1E-10
1E-12
Scrambled idle
worst case for
min CC
1E-14
Scrambled idle
worst case for
max CC
PRBS13Q
Probability of ocurrence
1E-06
1E-16
1E-18
1E-20
Fit to
random
1E-22
1E-24
1E-26
0.35
0.40
0.45
0.50
Clock Content
0.55
0.60
0.65
12
Clock, all transitions, Bd/5313
10,000 year limit
10,000 year limit
1
0.01
0.0001
Scrambled idle worst
case for max CC
PRBS31Q
1E-08
Random
1E-10
1E-12
PRBS13Q
Probability of ocurrence
1E-06
Scrambled idle worst
case for min CC
1E-14
1E-16
1E-18
1E-20
1E-22
Fit to
random
1E-24
1E-26
0.50
0.60
0.70
Clock Content
0.80
0.90
13
Clock, all transitions, Bd/13281
10,000 year limit
10,000 year limit
1
0.01
0.0001
PRBS31Q
Scrambled idle
worst case for
max CC
1E-08
1E-10
Random
1E-12
Scrambled idle
worst case for
min CC
1E-14
PRBS13Q
Probability of ocurrence
1E-06
1E-16
1E-18
1E-20
1E-22
Fit to
random
1E-24
1E-26
0.60
0.65
0.70
0.75
Clock Content
0.80
0.85
0.90
14
Clause 91 results
As expected from the previous analysis done for 400 Gb/s Ethernet (see
anslow_01_1215_logic), the common AM0 and AM16 markers cause a
significant “shoulder” on the clock content plots for 4:1 bit interleaving
for a 100 Gb/s lane which cause the plots to go outside those for
PRBS31Q.
Removing the second common AM would result in:
FEC lane 0
AM0 BIP AM0 BIP AM4 BIP AM4 BIP AM8 BIP AM8 BIP AM12 BIP AM12 BIP AM16 BIP AM16 BIP
Pad
Data
FEC lane 1
AM0 BIP AM0 BIP AM5 BIP AM5 BIP AM9 BIP AM9 BIP AM13 BIP AM13 BIP AM17 BIP AM17 BIP
Data
FEC lane 2
AM0 BIP AM0 BIP AM6 BIP AM6 BIP AM10 BIP AM10 BIP AM14 BIP AM14 BIP AM18 BIP AM18 BIP
Data
FEC lane 3
AM0 BIP AM0 BIP AM7 BIP AM7 BIP AM11 BIP AM11 BIP AM15 BIP AM15 BIP AM19 BIP AM19 BIP
Data
The performance of this revised scheme is shown on the following
slides.
15
Baseline wander
10,000 year limit
10,000 year limit
1
Scrambled idle worst
case for max BW
0.01
0.0001
Scrambled idle worst
case for min BW
PRBS31Q
1E-08
Random
1E-10
1E-12
PRBS13Q
Probability of ocurrence
1E-06
1E-14
1E-16
1E-18
1E-20
1E-22
1E-24
Fit to
random
1E-26
-10%
-5%
0%
Baseline Wander
5%
10%
16
Clock, sym trans through ave, Bd/5313
10,000 year limit
10,000 year limit
1
0.01
Scrambled idle worst
case for max CC
0.0001
1E-06
Random
1E-10
1E-12
1E-14
Scrambled
idle worst
case for min
CC
1E-16
1E-18
PRBS13Q
Probability of ocurrence
PRBS31Q
1E-08
1E-20
1E-22
1E-24
Fit to
random
1E-26
0.10
0.15
0.20
0.25
Clock Content
0.30
0.35
0.40
17
Clock, sym trans through ave, Bd/13281
10,000 year limit
10,000 year limit
1
0.01
0.0001
PRBS31Q
Scrambled idle
worst case for
max CC
Random
1E-08
1E-10
1E-12
1E-14
1E-16
Scrambled idle
worst case for
min CC
PRBS13Q
Probability of ocurrence
1E-06
1E-18
1E-20
1E-22
Fit to
random
1E-24
1E-26
0.15
0.20
0.25
Clock Content
0.30
0.35
18
Clock, trans through ave, Bd/5313
10,000 year limit
10,000 year limit
1
0.01
Scrambled idle worst
case for min CC
0.0001
PRBS31Q
Random
1E-08
1E-10
1E-12
PRBS13Q
Probability of ocurrence
1E-06
Scrambled idle worst
case for max CC
1E-14
1E-16
1E-18
1E-20
Fit to
random
1E-22
1E-24
1E-26
0.25
0.35
0.45
0.55
Clock Content
0.65
0.75
19
Clock, trans through ave, Bd/13281
10,000 year limit
10,000 year limit
1
0.01
0.0001
Random
PRBS31Q
1E-08
1E-10
1E-12
Scrambled idle
worst case for
min CC
1E-14
Scrambled idle
worst case for
max CC
PRBS13Q
Probability of ocurrence
1E-06
1E-16
1E-18
1E-20
Fit to
random
1E-22
1E-24
1E-26
0.35
0.40
0.45
0.50
Clock Content
0.55
0.60
0.65
20
Clock, all transitions, Bd/5313
10,000 year limit
10,000 year limit
1
0.01
0.0001
Scrambled idle worst
case for max CC
PRBS31Q
1E-08
Random
1E-10
1E-12
PRBS13Q
Probability of ocurrence
1E-06
Scrambled idle worst
case for min CC
1E-14
1E-16
1E-18
1E-20
1E-22
Fit to
random
1E-24
1E-26
0.50
0.60
0.70
Clock Content
0.80
0.90
21
Clock, all transitions, Bd/13281
10,000 year limit
10,000 year limit
1
0.01
0.0001
PRBS31Q
Scrambled idle
worst case for
max CC
1E-08
1E-10
Random
1E-12
Scrambled idle
worst case for
min CC
1E-14
PRBS13Q
Probability of ocurrence
1E-06
1E-16
1E-18
1E-20
1E-22
Fit to
random
1E-24
1E-26
0.60
0.65
0.70
0.75
Clock Content
0.80
0.85
0.90
22
Conclusion
Removing the second common AM as in:
FEC lane 0
AM0 BIP AM0 BIP AM4 BIP AM4 BIP AM8 BIP AM8 BIP AM12 BIP AM12 BIP AM16 BIP AM16 BIP
Pad
Data
FEC lane 1
AM0 BIP AM0 BIP AM5 BIP AM5 BIP AM9 BIP AM9 BIP AM13 BIP AM13 BIP AM17 BIP AM17 BIP
Data
FEC lane 2
AM0 BIP AM0 BIP AM6 BIP AM6 BIP AM10 BIP AM10 BIP AM14 BIP AM14 BIP AM18 BIP AM18 BIP
Data
FEC lane 3
AM0 BIP AM0 BIP AM7 BIP AM7 BIP AM11 BIP AM11 BIP AM15 BIP AM15 BIP AM19 BIP AM19 BIP
Data
significantly reduces the magnitude of the “shoulder” on the clock
content plots for 4:1 bit interleaving, so would be a better candidate AM
mapping.
Choosing AM1, AM2, or AM3 as the first common AM might improve
this further.
23
Thanks!
24