HP ISS Technology Update
Volume 9, Number 2
Keeping you informed of the latest ISS technology
Smart Array flash-backed write-cache..................................................................................................... 2
HP Smart Array Erase Drive function ...................................................................................................... 4
Meet the Expert—Bill Hanlon ................................................................................................................ 5
Contact us .......................................................................................................................................... 6
Recently published Industry-Standard Server technology papers
Title
URL
HP Virtual Connect technology implementation
for the HP BladeSystem c-Class, 4th edition
http://h20000.www2.hp.com/bc/docs/support/SupportMa
nual/c00814156/c00814156.pdf
HP VMware ESXi management environment
http://h20000.www2.hp.com/bc/docs/support/SupportMa
nual/c02000740/c02000740.pdf
HP ProLiant Server Power Management on SUSE http://h20000.www2.hp.com/bc/docs/support/SupportMa
Linux Enterprise Server 11
nual/c02011017/c02011017.pdf
Drive technology overview, 3rd edition
http://h20000.www2.hp.com/bc/docs/support/SupportMa
nual/c01071496/c01071496.pdf
HP power and cooling technologies for the data http://h20000.www2.hp.com/bc/docs/support/SupportMa
center
nual/c02018535/c02018535.pdf
HP Industry Standard Server technical papers can be found at www.hp.com/servers/technology
Smart Array flash-backed write-cache
The HP flash-backed write-cache (FBWC) system offers important advantages over battery-backed write-cache (BBWC)
systems. HP designed the FBWC with NAND 1 flash devices so that power is not required to retain cache data. There is no
longer a 48-hour battery life limitation and the data will be posted to the disk drive the next time you power up the server.
HP has engineered the FBWC to function with long-life super-capacitors (Super-caps) instead of a battery. The Super-cap is
only used to power the FBWC system during data backup. The result is that the FBWC retains cache data regardless of
server power states and you can adjust maintenance and replacement schedules to accommodate the longer Super-cap
lifecycle. Figure 1-1 displays the FBWC module and the Super-cap housing.
Figure 1-1. HP flash-backed write-cache and Super-cap power supply housing
NOTE:
The Super-cap is a capacitor, not a battery. The Super-cap module is contained within the same form factor and
housing as the HP-650 mAh P-Series battery used in the HP BBWC. The NAND flash devices do not require
sustained power to retain data. However, if server power fails, the FBWC does require power from the Super-cap
to copy data contained in the DRAM to the flash devices. Always install the Super Cap module with the FBWC.
FBWC architecture
The FBWC DDR2 mini-DIMM cache module is specifically designed for the present generation of PCIe2.0, SAS-based Smart
Array controllers based on the PMC PM8011 max SAS SRC 8x6G RAID on a chip (RoC). The primary FBWC components
are the cache module, Super-caps with integrated charger, and a RoC located on the system board, shown in Figure 1-2.
1
Non-volatile semiconductor memory that can be electronically erased and reprogrammed. No power is needed to maintain data stored in the chip
2
Figure 1-2. FBWC cache module block diagram
Side band
control
signals
NAND Flash
4b 33MHz
4b 33MHz
Data
FPGA
Command
& address
Super-cap
NAND Flash
In off-module pack connecting to
cache module
PROM
DRAM
8X
DRAM
8X
DRAM
8X
133 MHZ DDR IF
Register
Cache module
System board
400 MHZ DDR IF
Cache dirty N*
Reset N
Reg reset N
RoC
TWI**
* Cache tracks that have been written over are designated as "dirty"
** Two wire interface (TWI)
FBWC cache module
The FBWC cache module has a field programmable gate array (FPGA), DDR2 DRAMs, and NAND flash devices. The
module supports up to 1GiB of DDR2 memory and up to 72 data bits (64 data bits plus 8 ECC bits). The FBWC module
connects to the Smart Array controller through a 244-pin mini-DIMM connector. When the Smart Array controller is driving
the DDR2 bus, data rates of up to 800Mbps are supported. When the FPGA is driving the bus in a data recovery situation,
the data rate is 266Mbps.
Super-capacitor
The Super-cap module sub-assembly consists of two 35-Farad, 2.7-V capacitors configured in series, providing 17 Farads at
up to 5.4 V. The charger maintains the Super-cap at 4.8 V, providing the required amount of power to complete backup
operations while extending the life of the Super-cap. The charger also monitors Super-cap health and activates LED indicators
on the FBWC module to warn of impending failure. The Super-cap module is contained within the same form factor and
housing as the HP-650 mAh P-Series battery used in the HP BBWC.
Capturing data during power loss
Loss of power in a server using the FBWC prompts the FPGA to copy data contained in the DRAM to the NAND flash
devices residing on the cache module. The Super-cap supplies the energy needed to power the FBWC system while
performing the data backup operation.
Recovering data from the flash-backed cache
When system power is present, the FPGA is in its idle state. In the idle state, the FPGA simply monitors the voltage status, the
resets, and the control signals managed by the Smart Array controller. The FPGA DDR2 I/O pins are held in “tri-state,”
3
which is equivalent to a disabled mode to avoid bus contention. When system power is lost, the FPGA waits for the clock
enable signal of the Smart Array controller to transition to low, signaling that the controller has stopped driving the DDR2
bus. At this time, the FPGA assumes control of the bus and begins moving data from the DRAMs to the non-volatile NAND
flash memory on the cache module. Upon the next power up, the FPGA restores the cache by moving data from the flash
memory to the DRAMs. After the cache has been restored to the DRAMs, the Smart Array controller verifies that the data has
been retained correctly. If verified, the data is transferred to the disk drives.
HP Smart Array support
At the time of publication, the FBWC is supported on the Smart Array P410, P410i, P411, P212, P812, and P712m
controllers. The FBWC is another instance where HP design and engineering have increased reliability and reduced
maintenance issues for customers.
HP Smart Array Erase Drive function
Securely sanitizing disk drives involves completely overwriting the drive data at the lowest level, below the OS file system
and partition tables. With SAS and SATA drives, this means overwriting all of the logical blocks on the drive. Third-party
utilities can perform this task; however, HP Smart Array controllers with Smart Array Advanced Pack (SAAP) include an
integrated Erase Drive feature that can quickly and efficiently erase data without installing additional software. This feature is
accessed through the Array Configuration Utility (ACU).
Smart Array Erase Drive
The Smart Array Erase Drive function is available through the ACU for any logical or physical drive in an array. When a
physical drive is to be erased, it is taken offline (as if failed) to maintain the data integrity of any of the fault-tolerant logical
drives that it was a part of. Typically, an administrator would use this feature to erase a physical drive that is reporting a
predictive failure, in preparation for replacing it.
The Erase Drive function operates by writing zeroes to every logical block on the logical or physical drive. This overwrites all
file contents as well as the metadata, including all RAID controller, partition, and file system metadata. At a simplified level,
erasing a drive can be seen as serial write process, because its speed is governed by the average sequential write
throughput of the drive. As a result, a drive erase can take several hours to complete on a moderately sized 500-GB midline
SATA drive.
Selecting an erase pattern
Overwriting information with a single pass on a modern disk drive provides a reasonable level of data protection when
retiring drives from service (see Dr. Craig Wright’s article in Additional resources). However, some users are concerned that
sophisticated instrumentation can be used to detect the small residual magnetic flux that is left when a value of one is
overwritten with a zero versus a zero being overwritten with a zero. To eliminate the ability to recover data from an erased
drive, an administrator can configure the Smart Array Erase Drive function to perform a two-pass or three-pass erase pattern.
In both cases, the drive is overwritten with a random pattern of ones and zeroes before being overwritten with zeroes on the
final pass. A multi-pass erase will, of course, either double or triple the time needed to complete the erase drive operation.
Additional resources
Resource
URL
"Overwriting Hard Drive Data" by Dr. Craig
Wright, 2009
https://blogs.sans.org/computer-forensics/2009/01/15/overwritinghard-drive-data
Overview of and link to Guidelines for Media http://www.nist.org/nist_plugins/content/content.php?content.52
Sanitization. NIST publication SP 800-88
4
Meet the Expert—Bill Hanlon
Bill Hanlon’s title is Master, ISS Integrated System Test, but his unofficial title should
be “One of a kind” because of his unique skills and mode of transportation—he
drives to work everyday in his reliable 1957 GMC pickup truck. Bill joined
Compaq in 1987 as a member of the third level support organization. Now, he
writes test software for new server products and helps to debug problems that his
software discovers. Unlike his pickup truck, his job is unpredictable. He says
“When I arrive at work in the morning, I often have no idea what I’ll be working on
that day.”
According to his manager, Randy Dow, “Bill has deep technical knowledge of
servers that ranges from customer usage down to the inner workings of processors
and chipsets. He uses this knowledge to develop tools that stress the systems as well
as the chipsets and processors in unique and realistic ways. Bill’s years of
experience tracking down elusive problems combined with his willingness and
ability to whip up new tools as needed make him a highly sought-after debug
expert in ISS.”
His interests and inspiration
Name: Bill Hanlon
Title: Master, ISS Integrated System Test
Years at HP: 23
Military Service: U.S. Air Force
Bill’s interest in how things work stemmed from what he describes as being “the oldest son of a self-educated tinkerer.” He
started college at an early age but left to join the U.S. Air Force, where he served for over 3 years and achieved the rank of
sergeant. Bill loves to ski, but wishes he were a lot better at it.
He and his wife Cathy (married since 1967), have one daughter, Andrea, and two granddaughters, Lauren (13) and
Megan (11). Megan is an inspiration. She has cerebral palsy, yet she attends 5th grade with children without disabilities.
Megan manipulates a powered chair and communicates through a computer by using a device that converts her eye
movements to mouse actions. Remarkably, Megan also skis with the aid of a sit-ski and the help of the people at
Breckenridge Outdoor Education Center. Bill constantly keeps his eyes open for technologies that will help her.
Old school programmer
Bill is a self-described “old school” programmer and he says that the upkeep of his pickup truck symbolizes his style of
programming—it takes a bit of time to keep it running but it is very satisfying. Years ago, he wrote a program (on his own
time) to replace an ineffective application that Compaq was using as a corporate telephone book. Bill’s program became
the company standard for more than 10 years and was still being used after 17 years because it had features that are still
not available in Outlook.
Looking out for customers
Bill’s direct customer is usually a hardware design engineer who needs a specific test performed in a hurry. If the system fails
Bill’s test, he reviews the logic analyzer traces with the engineer until they figure out what went wrong. Bill does not receive
direct external customer input, but he protects customer interests by ensuring the quality of the finished product, sort of like a
“customer ombudsman.” He writes tests in assembly language and runs them in a DOS environment to avoid interference
from the OS. Running these low-level, but extreme, tests in the DOS environment allows Bill to use up to 256 processor cores
and up to 4 terabytes of memory.
Doing whatever it takes
Randy sums him up pretty well: “You’ll find that Bill is always eager to help out in any way he can and even though he is a
highly ranked technical engineer, you’ll find him doing whatever it takes to help solve the problems brought to him.”
5
Contact us
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TC100405NL, April 2010