TM
ISTFA 2013
Conference Proceedings from the
39th International Symposium
for Testing and Failure Analysis
November 3–7, 2013
San Jose Convention Center
San Jose, California, USA
This false color SEM image represents damaged silicon active area
by electrical over stress (EOS) event. In order to observe this melted
silicon, a deprocessing has been performed to remove interconnect
layers. This melted silicon looks like an active volcano.
Photo submitted by, Julien Goxe, Freescale Semiconducteurs
France SAS
False Color 2nd Place Winner
EDFAS 2012 Photo Contest
Telescopic view of snow covered mountains, trees and people.
(Sample is polyimide over Si-etched by focused ion beam with
water).
Photo submitted by, Chad Rue, FEI Company, Hillsboro, OR
Black & White 1st Place Winner
EDFAS 2012 Photo Content
Sponsored by
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ISBN-13:978-1-62708-022-4
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EDFAS 2013-2014 BOARD OF DIRECTORS
EDFAS President
Jeremy A. Walraven
Sandia National Laboratories
EDFAS Vice President
Cheryl Hartfield
Oxford Instruments Company
EDFAS Board Members
Mr. Jeremy A. Walraven
Ms. Cheryl Hartfield
Mr. Matthew Thayer
Mr. Christopher L. Henderson
Dr. Thomas Moore
Mr. Randall S. Barnes
Mr. Nicholas Antoniou
Dr. Lee Knauss
Dr. Philippe Perdu
Mr. David P. Vallett
Dr. William E. Vanderlinde
Position
President
Vice President
Secretary
Financial Officer
Past President
Executive Director
Member at Large
Member at Large
Member at Large
Secretary
Member at Large
Affiliation
Sandia National Laboratories
Oxford Instruments Company
Advanced Micro Devices
Semitracks, Inc.
OmniProbe
EDFAS
Harvard University
Booz Allen Hamilton
CNES
IBM Systems and Technology
Laboratory for Physical Sciences
Board Committees
Dr. Gernant E. Maurer, FASM
Dr. Felix Beaudoin
Ms. Susan Li
Mr. Dan Bodoh
Dr. Thomas Moore
Dr. Thomas Moore
Dr. Philippe Perdu
Position
ASM BOT Liaison
EDFA Chair
Education Chair
Events Chair
Membership Chair
Nominating Chair
International Growth
Affiliation
Consultant
IBM
Spansion
Freescale Semiconductor
OmniProbe
OmniProbe
CNES
iii
ORGANIZING COMMITTEE
Zhiyong Wang
General Chair
Intel
Dan Bodoh
Vice General Chair
Freescale Semiconductor
James J. Demarest
Technical Program Chair
IBM
Becky Holdford
Tutorial Chair
Texas Instruments, Inc.
Mayue Xie
Tutorial Vice Chair
Intel
Philippe Perdu
Immediate Past General Chair
CNES
ACTIVITIES CHAIRS
Nicholas Antoniou
Publicity Chair
Harvard University
Sandra Delgado
Photo and Video Contest Chair &
Local Arrangements Chair
Nanolab Technologies
Susan Li
Short Course Chair
Spansion Inc.
David Su
International Co-Chair
TSMC
Felix Beaudoin
Super Session Chair &
User Groups Vice Chair
IBM
Martin Keim
Audio Visual Chair
Mentor Graphics Corporation
Rick Livengood
User Groups Chair
Intel
Sam Subramanian
Panel Chair
Freescale Semiconductor
iv
Lihong Cao
International Chair Co-Chair
AMD
Edward P. Keyes
Super Session Chair &
Panel Vice Chair
Solantro Semiconductor
Efrat Moyal
LatticeGear LLC
Expo Chair
Jerome Touzel
International Chair
Infineon Technologies
ISTFA 2013 SYMPOSIUM COMMITTEE
ISTFA 2013
Technical Program Chair
James J. Demarest
IBM
Super Session Chairs
Felix Beaudoin
Super Session Chair: Photon Based
Techniques, Emerging Concepts,
Nanoprobing and Nanoscale Electrical
Failure Analysis, Test and Diagnostics
IBM
James. J. Demarest
Super Session Chair: Circuit Edit,
Case Studies and the Failure Analysis
Process, Defect Characterization and
Metrology, Posters
IBM
Edward P. Keyes
Super Session Chair: Packaging and
Assembly Analysis, Sample
Preparation and Device Deprocessing,
3D Packages
Solantro Semiconductor
Session Chairs and Co-Chairs
3D Packages
Frank Altmann (Chair), Fraunhofer
Institute for Mechanics of Materials
Yan Li (Co-Chair), Intel
Case Studies and the Failure
Analysis Process
Rose Ring (Chair),
GLOBALFOUNDRIES Malta
David Burgess (Co-Chair),
Accelerated Analysis
Circuit Edit
Dane Scott (Chair), Intel
Mike DiBattista (Co-Chair), Qualcomm
Defect Characterization and
Metrology
Phil Kaszuba (Chair), IBM
Terence Kane (Co-Chair), IBM
Emerging Concepts and
Techniques
Mike Bruce (Chair), Consultant
Huimeng Wu (Co-Chair), Carl Zeiss
Microscopy , LLC
Nanoprobing and Nanoscale
Electrical Failure Analysis
John Sanders (Chair), DCG Systems
Andy Erickson (Co-Chair), Multiprobe
Packaging and Assembly Analysis
Becky Holdford (Chair), Texas
Instruments
Lihong Cao (Co-Chair), Advanced
Micro Devices
Photon Based Techniques
Frank Zachariasse (Chair), NXP
Semiconductors
Herve Deslandes (Co-Chair), DCG
Systems
Posters
Martin Versen (Chair), University of
Applied Sciences Rosenheim
David Grosjean (Co-Chair), Analog
Devices
Sample Prep and Device
Deprocessing
Bryan Tracy (Chair), Spansion
Roger Alvis (Co-Chair), FEI
Test and Diagnosis
Geir Eide (Chair), Mentor Graphics
Mark Kimball (Co-Chair), Maxim
v
USER GROUPS
Nanoprobing
Moderators
Vijay Chowdhury
EAGLABS
Randal Mulder
Silicon Laboratories
Contactless Fault Isolation
Moderators
Baohua Niu
Intel
Pat Pardy
Intel
Focused Ion Beam (FIB)
Moderators
Mike DiBattista
Qualcomm
Patrick Stallings
Pereine Semi
Sample Preparation / 3D Packages
Moderators
Jacob Klein
Texas Instruments
Lucas Copeland
Texas Instruments
vi
Contents
2013 IPFA Best Paper
Non-Destructive Open Fault Isolation in Flip-Chip Devices with
Space-Domain Reflectometry ..................................................................................................1
W. Qiu1, J. Gaudestad2, V.V. Talanov2, and M.S. Wei1
(1) Device Analysis Laboratory Advanced Micro Devices (Singapore) Pte. Ltd., Singapore
(2) Neocera, LLC, Beltsville MD, USA
3D Packages
3D Void Imaging in Through Silicon Vias by X-Ray Nanotomography in an SEM ..............7
David Laloum1, Pierre Bleuet2, Frédéric Lorut1, Guillaume Audoit2, and Celine Ribiere2
(1) ST Microelectronics, Crolles, France
(2) CEA, LETI, MINATEC Campus, Grenoble, France
Challenges for Physical Failure Analysis of 3D-Integrated Devices—
Sample Preparation and Analysis to Support Process Development of TSVs ................ 12
Andreas Meyer, Gabriele Grimm, Michael Hecker, Martin Weisheit, and Eckhard Langer
GlobalFoundries Dresden, Dresden, Germany
Sample Preparation Strategies for Fast and
Effective Failure Analysis of 3D Devices .............................................................................. 17
Laurens Kwakman1, Marcus Straw2, Gaëlle Coustillier3, Marc Sentis3, Jens Beyersdorfer4,
Jan Schischka4, Falk Naumann4, and Frank Altmann4
(1) FEI Europe B.V., Eindhoven, The Netherlands
(2) FEI Company, Hillsboro, OR, USA
(3) Aix-Marseille University - CNRS, Marseille, France
(4) Fraunhofer Institute for Mechanics of Materials, Halle, Germany
Fast and Precise 3D Tomography of TSV by Using Xe Plasma FIB ................................... 27
Tomáš Hrnčíř and Lukáš Hladík, TESCAN, Brno, Czech Republic
Case Studies and the Failure Analysis Process
22 nm BEOL TDDB Defect Localization and Root Cause Analysis .................................... 33
Terence Kane, and Yun Yu Wang
IBM Systems Technology Group, Hopewell Junction, NY, USA
Open Failure Diagnosis Candidate Selection Based on
Passive Voltage Contrast Potential and Processing Cost .................................................. 40
Yan Pan, Oh Chong Khiam, Nyi Ohnmar, Chuan Zhang, Sekar Kannan, Atul Chittora,
Goh Szu Huat, Ma Yinzhe, Don Nedeau, Lim Seng Keat, and Jeffrey Lam
GlobalFoundries Inc., Malta, NY, USA
vii
Effective Defect Localization on Nanoscale Short Failures ................................................ 46
Jiang Huang, Ryan Sweeney, Laurent Dumas, Mark Johnston,
Pei-Yi Chen, and Jeremy Russell
GlobalFoundries, Malta, NY, USA
Defect Isolation Tools Accelerate the Failure Analysis Process ........................................ 49
Adam Winterstrom1, Kevin Meehan1, Ralph Sanchez2, and Rich Ackerman2
(1) International Rectifier, Temecula, CA, USA
(2) Teseda Corporation, Portland, OR, USA
First in Operando SEM Observation of
Electromigration-Induced Voids in TSV Structures............................................................. 59
Simon Gousseau1, Stéphane Moreau1, David Bouchu1, Alexis Farcy2,
Pierre Montmitonnet3, Karim Inal3, and François Bay3
(1) CEA, LETI, Minatec Campus, Grenoble, France
(2) ST Microelectronics, Crolles, France
(3) MINES ParisTech CEMEF, Sophia Antipolis, France
The Application of Magnetic Force Microscopy for Detection of
Subsurface Anomalies in Semiconductor Device Wiring Levels ....................................... 69
Phil Kaszuba, Frank Alwine, Leon Moszkowicz, and Randy Wells
International Business Machines, Essex Junction, VT, USA
Computed Tomography as Failure Analysis Insurance ...................................................... 75
Gerald M. Martinez, TeleCommunication Systems, Inc., Torrance, CA, USA
Challenges of Small Defect Analysis in Large Analog Power FET Arrays ........................ 86
Eric Cattey, Freescale Semiconductor, Tempe, AZ, USA
Conversion of a D-Mode FET to an E-Mode FET via
Electrostatic Discharge in a GaAs Power Amplifier Duplexer Module .............................. 91
Rose Emergo and Steve Brockett, TriQuint Semiconductor, Hillsboro, OR, USA
Marginal RF Gain Investigation and Root Cause Determination ........................................ 95
Keith Harber and Steve Brockett, TriQuint Semiconductor, Inc., Hillsboro, OR, USA
Anamnesis in Failure Analysis—How a System-Related Approach Can Save
Failure Analysis (FA) Time, Shorten Learning Loops and Reduce Cost ........................... 99
Peter Jacob, Empa Swiss Fed Labs for Materials Testing and Research,
Duebendorf, Switzerland
Failure Analysis for SRAM Logic Type Failures ................................................................ 105
Zhigang Song, Felix Beaudoin, Stephen Lucarini, John Sylvestri, Laura Safran,
Manuel Villallobos, and Richard Oldrey
IBM Systems and Technology, Hopewell Junction, NY, USA
viii
Circuit Edit
Circuit Edit Geometric Trends ............................................................................................ 111
Michael DiBattista, Martin Parley, Don Lyons, Roddy Cruz, Alan Wu, Jamie Langley,
Jonathan Lau, and Ray Stevens
Qualcomm Incorporated, San Diego, CA, USA
Implications of Helium and Neon Ion Beam Chemistry for
Advanced Circuit Editing .....................................................................................................118
H. Wu1, D. Ferranti1, L.A. Stern1, D. Xia1, M.W. Phaneuf2
(1) Carl Zeiss Microscopy LLC, Peabody, MA, USA
(2) Fibics Incorporated, Ottawa, Canada
Silicon and Package Preparation Options for Focused Ion Beam (FIB)
Circuit Editing and General Packaging Failure Analysis .................................................. 123
Steven B. Herschbein, Carmelo F. Scrudato George K. Worth, and Edward S. Hermann
IBM Systems & Technology, Hopewell Junction, NY,USA
Defect Characterization and Metrology
Simulation Studies on Fluorine Spec Limit for Process Monitoring of
Microchip Al Bondpads in Wafer Fabrication .................................................................... 134
Younan Hua, Nistala Ramesh Rao, Yanjing Yang, Siping Zhao, and Redkar Shailesh
GlobalFoundries Singapore Pte. Ltd., Singapore
Surface Microstructure Evolution Upon Silicidation of Ni(Pt) and the
Different Responses to Metal Etch...................................................................................... 138
Wentao Qin1, Dorai Iyer1, Mike Thomason2, Jim Morgan1, Carroll Casteel1,
Robert Watkins1, and Rod Crowder1
(1) ON Semiconductor, Phoenix, AZ, USA
(2) ON Semiconductor, Pocatello, ID, USA
Gate Leakage Characterization and Fail Mode Analysis on
20 nm Technology Parametric Test Structures ................................................................. 144
Satish Kodali1, Wayne Zhao1, Greg M. Johnson2, and Felix Beaudoin2
(1) GlobalFoundries Inc., Hopewell Junction, NY, USA
(2) IBM Hopewell Junction, East Fishkill, NY, USA
STEM EDX Mappings and Tomography for Process Characterization and
Physical Failure Analysis of Advanced Devices ................................................................ 149
Kevin Lepinay1, Frederic Lorut1, Roland Pantel1, and Thierry Epicier2
(1) STMicroelectronics, Crolles, France
(2) MATEIS Lab, INSA de Lyon, Lyon, France
Automatic Registering and Stitching of TEM/STEM Image Mosaics................................ 152
Chung-Ching Lin, Franco Stellari, Lynne Gignac, Peilin Song, and John Bruley
IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
ix
AFM-Based Chemical and Mechanical Property Characterization of
Interconnects and Defects ................................................................................................... 159
Michael Lo1, Eoghan Dillon1, Qichi Hu1, Kevin Kjoller1, Roshan Shetty1,
Craig Prater1, and Sean W. King2
(1) Anasys Instruments Corp., Santa Barbara, CA, USA
(2) Intel Corp., Hillsboro, OR, USA
Evaluation of Digital Holography Microscopy for
Roughness Control Prior Wafer Direct Bonding ............................................................... 162
B. Domengès1, France T. Delaroque2, Ch. Gautier2, K. Danilo2, and E. Le Flao2
(1) LAMIPS, CRISMAT – NXP Semiconductors Caen, France
(2) Presto-Engineering Europe, Caen, France
Emerging Concepts and Techniques
Pump-Probe Imaging of Integrated Circuits....................................................................... 168
David Stoker1, Michael Bruce2, Eric Lavelle1, Erik Matlin1, James Potthast3,
Christopher Sakai1, and Neil Troy1
(1) SRI International, Menlo Park, CA, USA
(2) Independent Consultant
(3) Averna Test Systems
Two-Photon-Absorption-Enhanced Laser-Assisted Device Alteration and
Single-Event Upsets in 28 nm Silicon Integrated Circuits ................................................ 173
K.A. Serrels1, N. Leslie1, T.R. Lundquist1, P. Vedagarbha1, K. Erington2, D. Bodoh2,
C. Farrell3, and D.T. Reid3
(1) DCG Systems Inc. Fremont, CA, USA
(2) Freescale Semiconductor, Austin, TX, USA
(3) Heriot-Watt University, Riccarton, Edinburgh, UK
A Superconducting Nanowire Single-Photon Detector (SnSPD) System for
Ultra Low Voltage Time-Resolved Emission (TRE) Measurements of
VLSI Circuits ......................................................................................................................... 182
Franco Stellari1, Alan J. Weger1, Seongwon Kim1, Dzmitry Maliuk1, Peilin Song1,
Herschel A. Ainspan1, Young Kwark1, Christian W. Baks1, Ulrike Kindereit1,
Vikas Anant2, and Ted Lundquist3
(1) IBM T.J. Watson Research Center, Yorktown Heights, NY , USA
(2) Photon Spot Inc., Monrovia, CA, USA
(3) DCG Systems, Fremont, CA, USA
3D Magnetic Field Imaging for Non-Destructive Fault Isolation ....................................... 189
A. Orozco1, J. Gaudestad1, N.E. Gagliolo1, C. Rowlett1, E. Wong1, A. Jeffers2,
B. Cheng2, F.C. Wellstood2, A.B. Cawthorne3, and F. Infante4
(1) Neocera, LLC, Beltsville, MD, USA
(2) University of Maryland, College Park MD, USA
(3) Trevecca Nazarene University, Nashville, TN, USA
(4) Intraspec Technologies, Toulouse, France
x
Time-Resolved Thermoreflectance Imaging for Thermal Testing and Analysis ............. 194
Kazuaki Yazawa1, Dustin Kendig1, and Ali Shakouri2
(1) Microsanj LLC., Santa Clara, CA, USA
(2) Purdue University, West Lafayette, IN, USA
Nanoprobing and Nanoscale Electrical Failure Analysis
Advantage of AFP Nanoprobing on the 28 nm Technology Failure Analysis ............... 203
C.Q. Chen, G.B. Ang, S.P. Zhao, Q. Alfred, N. Dayanand, K. Dnyan, and B.H. Liu
GlobalFoundries Singapore Pte. Ltd.
Optical Nanoprobe Electrical Microscopy .......................................................................... 208
Stephen Ippolito1, Michael Tenney2, Sweta Pendyala2, Larry Fischer2, John Sylvestri2,
Darrell Miles2, Rich Oldrey2, Manuel Villalobos2, Scott Dinkel2, Terry Kane2,
Bruce Redder2, and Pat McGinnis2
(1) Independent Scientific Inc. Saint Petersburg, FL, USA
(2) IBM Semiconductor Research & Development Center, Hopewell Junction, NY, USA
Device Characterization Using AFP Nanoprobing for the
Localization of New Product Design Weakness ...............................................................213
Ghim Boon Ang, Alfred Quah, Changqing Chen, Si Ping Zhao, Dayanand Nagalingam,
Yan Li, Soh Ping Neo, and Redkar Shailesh
GlobalFoundries Singapore Pte. Ltd.
SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for
Semiconductor Failure Analysis ....................................................................................... 217
Erik Paul, Holger Herzog, Sören Jansen, Christian Hobert, and Eckhard Langer
GlobalFoundries Dresden, Dresden, Germany
The Unique and Completed Characteristics of Device Behaviors in the
Nanoprobing Analysis and Application for Missing LDD ................................................. 222
LiLung Lai, Semiconductor Manufacturing International Corp.
Pudong New Area, Shanghai, China
A Study of Electron Beam Irradiation Influence on Device Contact Junction
Characteristics of Advanced DRAM Using Atomic Force Probing .................................. 228
Wei-Chih Wang and Jian-Shing Luo
Inotera Memories, Inc. Kueishan, Taoyuan, Taiwan, Republic of China
In-situ Characterization of Switching Mechanism in
Phase Change Random Access Memory (PRAM) Using
Transmission Electron Microscopy (TEM) ......................................................................... 236
Sungkyu Son1, Seungjoon Jeon1, Jangwon Oh1, Won Kim1, Hojoung Kim1,
Jonghak Lee1, Seungho Woo1, Sungjoo Hong1, Gapsok Do1, Seungyun Lee1,
Kyungjoon Baek2, and Sangho Oh2
(1) SK Hynix Semiconductor, Ichon-si, Korea
(2) Postech, Pohang, Korea
xi
Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe ...................... 239
Jong Hak Lee, Jong Eun Kim, Chang Su Park, Nam Il Kim, Jang Won Moon,
Jong Chae Kim, Soo Yong Son, Kyung Dong Yoo, and Sung Joo Hong
SK Hynix Inc., Icheon-si, Korea
Physical and Electrical Performance Comparison of
Identical 28 nm Qualcomm Telecommunication Die Produced by
Samsung and TSMC .............................................................................................................243
Anton Riley1, Sean Zumwalt1, Sinjin Dixon-Warren2, and Gary Tomkins2
(1) Multiprobe Inc., CA, USA
(2) Chipworks, Ottawa, Canada
Nanoprobing as an Essential and Fast Methodology in Identification of
Failure’s Root Cause for Advanced Technology ............................................................. 249
Yinzhe Ma, Chong Khiam Oh, Ohnmar Nyi, Chuan Zhang, Donald Nedeau,
Seng Keat Lim, and Ming Chu King
GlobalFoundries, Malta, NY, USA
dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits ............ 255
Sweta Pendyala, Dave Albert, Katherine Hawkins, and Michael Tenney
IBM, Hopewell Junction, NY, USA
Applications of Nanoprobing for Localization of Design for
Manufacturing Issues on Analogue-to-Digital Converter on
Advanced Technology Node ............................................................................................. 260
A.C.T. Quah, C.Q. Chen, G.B. Ang, D. Nagalingam, Y. Li, J. Zhu,
S.P. Neo, and S.P. Zhao
GlobalFoundries Singapore Pte. Ltd.
Packaging and Assembly Analysis — Session 1
Electro Optical Terahertz Pulse Reflectometry—A Fast and
Highly Accurate Non-Destructive Fault Isolation Technique for
3D Flip Chip Packages .......................................................................................................264
Stephane Barbeau1, Jesse Alton2, and Martin Igarashi2
(1) IBM Microelectronics, Bromont, QC, Canada
(2) TeraView Limited, Cambridge, UK
Open Localization in Micro LeadFrame Package Using
Space Domain Reflectometry .............................................................................................. 270
J. Gaudestad1, V. Talanov1, A. Orozco1, and M. Marchetti2
(1) Neocera, LLC, Beltsville, MD, USA
(2) ST Micro Electronics, Rousset Cedex, France
Nondestructive Analysis Solution Using Combination of
Lock-In Thermography (LIT) and 3D Oblique X-Ray CT Technology ............................. 274
Naoki Seimiya1, Takuhei Watanabe2, and Takashi Ichinomiya3
(1) Marubun Corporation, Chuo-ku, Japan
(2) Uni-Hite System Corporation, Yamato City, Kanagaw, Japan
(3) DCG Systems, Yokohama City, Kanagawa, Japan
xii
Sub-Mohms Resistance Characterization of Conductive Interfaces on
Automotive Power MOSFET to Determine the Origin of On-Resistance Drift ................. 277
Yann Weber and Philippe Rousseille
Freescale Semiconducteurs France SAS, Toulouse, France
Analysis of Power MOSFET Active Temperature Cycling Failures ................................. 283
Ian Kearney, Texas Instruments, Bethlehem, PA, USA
Packaging and Assembly Analysis — Session 2
Failure Analysis on Lifted Ball Bond and
Micro Lateral Crack Using Fractography Approach .......................................................... 292
Yong Foo Khong and Michael Raj Marks, Infineon Technologies, Kedah, Malaysia
Planar Analysis of Copper-Aluminium Intermetallics ....................................................... 297
G.M. O’Halloran, Arjan van Ijzerloo, Rene Rongen, and Frank Zachariasse
NXP Semiconductors, Nijmegen, The Netherlands
A Comprehensive Approach to Lifted Bond Balls Package Failure ................................ 301
Dat Nguyen and Sagar Karki, Texas Instruments Corp., Dallas, TX, USA
Photon Based Techniques — Session 1
Laser Voltage Imaging and Its Derivatives—Efficient Techniques to
Address Defect on 28 nm Technology .............................................................................. 306
Thierry Parrassin1, Guillaume Celi1, Sylvain Dudit1, Michel Vallet1, Antoine Reverdy2,
Philippe Perdu3, and Dean Lewis4
(1) STMicroelectronics, Crolles, France
(2) Sector Technologies, Gières, France
(3) CNES Laboratory, Toulouse, France
(4) Université Bordeaux, Talence, France
Advanced Fault Localization through the Use of
Tester Based Diagnostics with LVI, LVP, CPA, and PEM.................................................. 313
Laura Safran, John Sylvestri, Dave Albert, Zhigang Song, and Patrick McGinnis
IBM Systems and Technology Group, Hopewell Junction, NY, USA
Scan-Shift Debug Using LVI Phase Mapping ..................................................................... 322
Yin (Roy) S. Ng1, Howard Marks1, Christopher Nemirov2,
Chun-Cheng Tsao2, and Jim Vickers2
(1) NVIDIA, Santa Clara, CA, USA
(2) DCG Systems, Fremont, CA, USA
Comparison of C.W. Electro Optical Probing and Light Emission Techniques .............. 329
K. Sanchez1, P. Perdu1, K. Melendez1, T. Nakamura2
(1) CNES, DCT/AQ/LE, Toulouse, France
(2) Hamamatsu Photonics Japan, Toulouse, France
xiii
32 nm CMOS SOI Test Site for Emission Tool Evaluation ................................................ 336
Alan J. Weger, Franco Stellari, Seongwon Kim, Herschel A. Ainspan, Young Kwark,
Christian W. Baks, Dzmitry Maliuk, and Peilin Song
IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Tester-Based Methods to Enhance Spatial Resolvability and
Interpretation of Time-Integrated and Time-Resolved Emission Measurements ............ 341
Franco Stellari, Peilin Song, Alan J. Weger, Dzmitry Maliuk, Herschel A. Ainspan,
Seongwon Kim, Young Kwark, and Christian W. Baks
IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Optimization of Soft Defect Localization Technique Scan Time Using
Dummy Subroutine Test Vector Insertion .......................................................................... 350
B.L. Yeoh, S.H. Goh, Y.H. Chan, G.F. You, Y.E. Koh, and Jeffrey Lam
GlobalFoundries, Singapore
Realizing Dynamic Thermal Laser Stimulation by
Lock-in IR-OBIRCH Assisted with a Current Detection Probe Head ................................ 357
Chunlei Wu and Suying Yao, Tianjin University, Tianjin, China
Electrical Modeling of the Effect of Photoelectric Laser Fault Injection on
Bulk CMOS Design ............................................................................................................... 361
Laurent Hériveaux, Jessy Clédière, Stèphanie Anceau, CEA-Leti, Grenoble, France
Comparison of Beam-Based Failure Analysis Techniques for
Microsystems-Enabled Photovoltaics .............................................................................. 369
Benjamin B. Yang, Jose L. Cruz-Campa, Gaddi S. Haase, Edward I. Cole Jr.,
Paiboon Tangyunyong, Murat Okandan, and Gregory N. Nielson
Sandia National Laboratories, Albuquerque, NM, USA
Photon Based Techniques — Session 2
Dynamic Differential Thermal Measurements for
Reliability and Failure Analysis ........................................................................................... 376
R. Aaron Falk, Tram Pham, and Anthony Ruiz
Quantum Focus Instruments Corp, Vista, CA, USA
Thermal Laser Stimulation Technique for AlGaN/GaN HEMT
Technologies Improvement ................................................................................................. 386
Dominique Carisetti1, Nicolas Sarazin1, Nathalie Labat2, Nathalie Malbert2,
Arnaud Curutchet2, Benoit Lambert3, Laurent Brunel3, Karine Rousseau4,
Eddy Romain Latu4, and Thomas Frank4
(1) Thales Research and Technologies, Palaiseau, France
(2) Université Bordeaux Talence, France
(3) United Monolithic Semiconductor, Villebon-sur-Yvette, France
(4) SERMA Technologies, Grenoble, France
xiv
Novel Defect Detection Using Laser-Based Imaging and
TIVA with a Visible Laser ...................................................................................................392
Mary A. Miller, Paiboon Tangyunyong, Edward I. Cole Jr.,
Alejandro Pimentel, and Darlene M. Udoni
Sandia National Laboratories, Albuquerque, NM, USA
Fault Localization of Metal Defects with Si-CCD Camera in
Analog Device Functional Failure ....................................................................................... 398
Stephane Alves, Philippe Rousseille, and Thomas Zirilli
Freescale Semiconducteurs France SAS, Toulouse, France
Posters
A New Approach for Screening Retention Time Failure Bits in DRAM Device ............. 403
Bonggu Sung, Daejung Kim, Yongjik Park, and Joo-Sun Choi
Samsung Electronics Co., Ltd., Hwasung-City, Gyeonggi-Do, Korea
A Reduction of Off-Leakage Current of SWD (Sub-WordLine Driver)
pMOSFET for NWL-Based Mobile DRAM ......................................................................... 407
Sanghyeon Jeon, Taehong Ha, Youngwoo Kim, Hyuckchai Jung, Taewoo Lee,
Kyupil Lee, and Insoo Cho
Samsung Electronics Co., Ltd., Gyeonggi-Do, Korea
A Simple Polishing Technique for Removing the
Entire Metallization Stack for Sub 100 nm Device Technologies ................................... 412
Randal Mulder and Robert Anderson, Silicon Laboratories, Inc., Austin, TX, USA
Adaptive Optics Compensation of Aberrations Introduced by
Sample Thickness Error in aSIL Confocal Scanning Microscopy .................................. 417
Y. Lu, T.G. Bifano, M.S. Ünlü, and B.B. Goldberg, Boston University, Boston, MA, USA
Advanced CMOS Device Fault Isolation Using
Frequency Mapping on Passive Structures ..................................................................... 420
S.H. Goh1, B.L. Yeoh1, G.F. You1, W.H. Hung1, Jeffrey Lam1,
E. Ruttkowski2, R. Kamaludeen2, and Henry Zhang2
(1) GlobalFoundries, Singapore
(2) Lantiq Asia Pacific Pte. Ltd., Singapore
Advanced FIB CE Combined with Static Analysis for
Functional Failure Analysis ................................................................................................. 424
S.K. Loh, C.Q. Chen, K.H. Yip, A.C.T. Quah, X. Tao, P.T. Ng,
G.B. Ang, and S.P. Zhao
Failure Analysis Group, QCE, GlobalFoundries
An Effective SIMS Methodology for GOI Contamination Analysis ................................... 427
Yanhua Huang, Lei Zhu, Kenny Ong, Hanwei Teo, and Younan Hua
GlobalFoundries Singapore Pte. Ltd., Singapore
xv
Application of AFP in Resolving Systematic Issue in Wafer Fabrication ...................... 430
Hui Peng Ng, Ghim Boon Ang, Chang Qing Chen, Alfred Quah, Angela Teo,
Mern Tat Lee, Jony Indahwan, and Si Ping Zhao
GlobalFoundries Singapore Pte. Ltd.
Arsenic Segregation Induced Gate Leakage by TEM Failure Analysis ............................ 434
Binghai Liu, Si Ping Zhao, Eddie Er, Changqing Chen,
Ghim Boon Ang, and Zhiqiang Mo
GlobalFoundries Singapore, Singapore
Data Center Equipment Reliability Concerns—Contamination Issues,
Standards Actions, and Case Studies ............................................................................... 438
Chris Muller1, Chuck Arent1, Henry Yu2
(1) Purafil, Inc., Doraville, Georgia, USA
(2) Purafil, Inc., Guangzhou, China
Die Level Defect Analysis Using Combined Techniques of
AFP with Electron Microscopes ........................................................................................ 445
Lee Lan Yin, Bai Haonan, Chua Kok Keng, Chow Yew Meng, and Grace Tan
Xilinx Asia Pacific Pte. Ltd., Singapore, Singapore
Enabling Scanning Acoustic Microscopy Inspection of
Materials Underneath the Chamfer of the Package ......................................................... 448
Melanie S. Cajita, Marlyn C. Grancapal, and Rudolf A. Sia
Analog Devices Philippines, Inc., Cavite, Philippines
Failure Localization of an Electrical Transient Behavior on a
Mixed-Mode IC by Using Static Emission Microscopy Technique ................................... 452
Magdalena Sienkiewicz, Estelle Huynh, and Alain Vidal
Freescale, Toulouse, France
Gate Bridge to Drain Contact Characteristic in Floating Gate Memory ........................... 456
Pei Wei Chiang, Yu Ting Ling, Bo Chih Chen, and Hsiao Tien Chang
Macronix international Co. Ltd., Hsinchu, Taiwan
Glass Interposer Reliability Improvement by
Transient Thermal Modelling and Physical Analysis ...................................................... 463
A. Benali, A. El Amrani, Y. Bouissa, M. Bouya, M. Faqir, M. Ghogho,
Y. Benlahoucine, and Z. Sbiaa
International University of Rabat-UIR, Sala al Jadida, Morocco
High Resolution C-Mode Scanning Acoustic Microscope Techniques for the
Failure Analysis of Microelectronic Packages ................................................................. 468
Yan Li, Liang Hu, Gang Li, Rajen Dias, and Deepak Goyal
Intel Corporation, Chandler, AZ, USA
How to Interpret the Reflected Laser Probe Signal of
Multiple Elementary Substructures in Very Deep Submicron Technologies ................. 471
M.M. Rebaï1, F. Darracq1, D. Lewis1, P. Perdu2, K. Sanchez2
(1) University of Bordeaux, France
(2) CNES, Toulouse, France
xvi
Localization of a Complex Failure by Combining ATPG and
Customer-Oriented Application Testing ............................................................................ 482
Kai Wang1, Rhys Weaver1, and David Johnson2
(1) CSR plc, Cambridge, UK
(2) Synopsys Inc., Reading, UK
Memory Scramble Verification by Frontside and Backside FIB Modification ............... 486
Chun Ming Tsai, Yi Shiuan Huang, Ya Hui Lu, and Jian Chang
Lin United Microelectronics Corporation, Taiwan, R.O.C
Micro-Abrasive Blasting—A Novel Approach to Local Silicon and
Mold Compound Material Removal ................................................................................... 490
Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri,
Matthew M. Mulholland and Hien Nguyen
Intel Corporation, Santa Clara, CA, USA
Rapid Failure Analysis of Low-Yielding Electrical Test Structures Using
E-beam Physical and Voltage Contrast Inspection ........................................................... 494
Oliver D. Patterson1, Deborah A. Ryan1, Xiaohu Tang2, Shuen Cheng Lei2
(1) IBM, Hopewell Junction, NY, USA
(2) Hermes Microvision Inc., Hopewell Junction, NY, USA
Silicon Junction Profile Delineation by Anodic Etching in
HF/HNO3/CH3COOH Solution............................................................................................... 498
Jeng-Han Lee , Y.M. Chen, C.M. Huang, F.Y. Tseng, C.J. Chen, K.M. Yin,
Y.T. Lin, Y.S. Huan, and David Su
Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Simple and Effective Technique of Backside Deprocessing of
Thin Flip Chip Package ......................................................................................................501
Suk Ho Lee, Chan Hee Park, Seung Joon Cha, Eun Cheol Lee, and
Kyu Shik Hong
Samsung Electronics Co. Ltd., Ki-hung, South Korea
Study of Static Noise Margin and Circuit Analysis on
Advanced Technology Node SRAM Devices by Nanoprobing ....................................... 505
M.K. Dawood, T.H. Ng, P.K. Tan, H. Tan, S. James, P.S. Limin, Y. Huang,
J. Lam and Z.H. Mai
GlobalFoundries Singapore Pte. Ltd., Singapore
Surface Treatment for 20 nm SRAM Devices to
Overcome Tip Curvature Radius Limitation in Conductive AFM Analysis ...................... 511
Tsu Hau Ng, S. James, M.K. Dawood, P.S. Limin, H. Tan, P.K. Tan,
J.C. Lam and Z.H. Mai
GlobalFoundries Singapore Pte. Ltd., Singapore
UV-Raman Microscopy on the Analysis of
Ultra-Low-k Dielectric Materials on Patterned Wafers ...................................................... 517
Maggie Y.M. Huang, Tsu Hau Ng, Hao Tan, Mohammed Khalid Bin Dawood,
Pik Kee Tan, Jeffrey C.K. Lam, and Zhihong Mai
GlobalFoundries, Singapore Pte. Ltd., Singapore
xvii
Validity-Study of Commercial Semiconductor with TO-18 Package for
Space Application by PIND Test ....................................................................................... 523
Yusuke Nakatake, Makoto Okabe, and Shota Sato
Ryoei Technica Corporation, Kanagawa, Japan
Sample Preparation and Device Deprocessing — Session 1
Back-Side Deprocessing for Bulk Silicon Devices .......................................................... 527
M.S. Wei1 and Lauren Blair2
(1) Advanced Micro Devices (Singapore) Pte. Ltd., Singapore
(2) Advanced Micro Devices, Inc., Austin, TX, USA
Advanced FIB Application—Automated,
Precision Deprocessing for Failure Analysis ................................................................... 532
Dandan Wang, Hua Feng, Pik Kee Tan, Guorong Low, Khiam Oh Chong,
Jeffrey Lam, and Zhihong Mai
GlobalFoundries Singapore Pte. Ltd., Singapore
Silicon Fringe Sample Metrology—A Thickness Measurement Technique .................... 536
Mark Kimball, Maxim Integrated, Hillsboro, OR, USA
A New Deprocess Flow of Failure Analysis for MEMS Motion Sensor ............................ 540
Chun-An Huang, Han-Yun Long, King-Ting Chiang, Li Chuang, and Kevin Tsui
Integrated Service Technology Inc., Hsin-chu, Taiwan (R.O.C.)
TEM Sample Fabrication of Sub 22 nm Three-Dimensional Test Structures .................. 544
James J. Demarest, IBM, Albany, NY, USA
A Sample Preparation Methodology for Effective Failure Analysis of
Trench Power MOSFET ...................................................................................................... 549
Yan Li, S.K. Loh, C.Q. Chen, G.B. Ang, A.C.T. Quah, S.P. Neo, C.K. Oh,
Y.J. Yao, and S.P. Zhao
GlobalFoundries Singapore Pte. Ltd.
Backside Sample Preparation Challenges for
Fault Localization Analysis of Flip Chip Package ............................................................ 553
Lihong Cao1, Donna Wallace1, Lynda Tuttle1, and Kirk Martin2
(1) Advanced Micro Devices, Austin, TX, USA
(2) RKD Engineering Corp, Scotts Valley, CA, USA
Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM............................ 560
Max L. Lifson, Carla M. Chapman, D. Philip Pokrinchak, Phyllis J. Campbell,
Greg S. Chrisman, Steven J. Boren, and Renata A. Camillo-Castillo
IBM Microelectronics, Essex Jct, VT, USA
xviii
Sample Preparation and Device Deprocessing — Session 2
Application of Laser Deprocessing Techniques in Physical Failure Analysis ................ 563
H.H. Yap, P.K. Tan, J. Lam, T.H. Ng, G.R. Low, R. He, H. Feng, Y.Z. Zhao,
M.K. Dawood, H. Tan, Y.M. Huang, D.D. Wang, and Z.H. Mai
GlobalFoundries Singapore Pte. Ltd., Singapore
Top-Down Delayering with Planar Slicing Focus Ion Beam (TD-PS-XFIB) .................... 569
G.R. Low, P.K. Tan, T.H. Ng, H.H. Yap, H. Feng, R. He, H. Tan, M.K. Dawood,
Y.M. Huang, D.D. Wang, Y.Z. Zhao, Y. Zhou, J. Lam, and Z.H. Mai
GlobalFoundries Singapore Pte. Ltd., Singapore
Alternative Sample Preparation Technique for
Die Level Parallel Lapping Analysis ................................................................................... 576
Hoon Ye Gwee and Kiong Kay Ng, Infineon Technologies, Melaka, Malaysia
Test and Diagnostics
Early Inline Detection of Systematic Defects Using ATPG and
Commonality Analysis on Product-Like Logic Yield Learning Vehicle ........................... 582
Felix Beaudoin1, Zhigang Song1, Stephen Lucarini1, Thomas F. Mechler1,
Stephen Wu1, Todd L. Cohen1, Mark Lagus1, Dieter Wendel2, Bruno Spruth2,
Kevin Stanley3, and David Bogdan3
(1) IBM Systems and Technology, Hopewell Junction, NY, USA
(2) IBM Systems and Technology, Boeblingen, Germany
(3) IBM Systems and Technology, Essex Junction, VT, USA
Evolution of Wafer Level Tester-Based Diagnostic System—
More Than Just a Dynamic Electrical Fault Isolation Tool .............................................. 587
S.H. Goh1, G.F. You1, B.L. Yeoh1, Y.H. Chan1, C.P. Yap1,
Jeffrey Lam1, and C.M. Chua2
(1) GlobalFoundries, Singapore
(2) SEMICAPS Pte. Ltd.
Improving Failure Analysis for Cell-Internal Defects through
Cell-Aware Technology ......................................................................................................594
F. Hapke1, M. Keim4, T. Herrmann2, T. Heidel2, M. Reese3, J. Schloeffel1, J. Rivers3,
W. Redemund4, A. Over3, A. Glowatz1, A. Fast1, B. Benware4, and J. Rajski4
(1) Mentor Graphics, Hamburg, Germany
(2) GlobalFoundries, Dresden, Germany
(3) AMD, Inc., Austin, TX, USA
(4) Mentor Graphics, Wilsonville, OR, USA
Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping .................. 602
Yan Pan, Atul Chittora, Kannan Sekar, Goh Szu Huat, You Guo Feng,
Avinash Viswanatha, and Jeffrey Lam
GlobalFoundries Inc., Malta, NY , USA
Author Index ........................................................................................................................ 609
xix