Faculty of Engineering
ELECTRICAL AND ELECTRONIC ENGINEERING DEPARTMENT
EENG115/INFE115 Introduction to Logic Design
EENG211/INFE211 Digital Logic Design I
Spring 2009-10
Instructors:
M. K. Uyguroğlu
H. Demirel
Final EXAMINATION
June 08, 2010
Duration : 120 minutes
Number of Problems: 7
Good Luck
STUDENT’S
NUMBER
NAME
SOLUTIONS
SURNAME
GROUP NO
Problem
Achieved
Maximum
1
10
2
10
3
10
4
10
5
20
6
20
7
20
TOTAL
100
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 1 (10 points)
A. Converting (153)10 to base 8 yields which of the following results?
(a)
(b)
(c)
(d)
(e)
107
132
701
231
153
B. Converting (0111011.100)2 to base 16 yields which of the following results?
(a)
(b)
(c)
(d)
(e)
73.8
3C.4
3B.8
73.4
3B.4
C. 10100 is the two's complement representation of:
(a)
(b)
(c)
(d)
(e)
-11
+12
-12
-20
+20
D. Simplification of the Boolean expression AB + ABC + ABCD + ABCDE + ABCDEF
yields which of the following results?
(a)
(b)
(c)
(d)
(e)
ABCDEF
AB
AB + CD + EF
A+B+C+D+E+F
A + B(C+D(E+F))
E. Given that F = (A + B'+ C)(D + E), which of the following represents the only correct
expression for F'?
(a)
(b)
(c)
(d)
(e)
F' = A'BC'+ D'+ E'
F' = AB'C + DE
F' = (A'+ B + C')(D'+ E')
F' = A'BC' + D'E'
F' = (A + B'+ C)(D'+ E')
M. K. Uyguroğlu, H. Demirel
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 2 (10 points):
A. Identify the function which generates the K-map shown
(a)
(b)
(c)
(d)
(e)
F(A,B,C)= Σ(1,3,4,7)
F(A,B,C)= Σ (1,3,5,6)
F(A,B,C)= Σ (3,4,5,6)
F(A,B,C)= Π(1,3,4,7)
F(A,B,C)= Π (1,3,5,6)
AB
C
00
01
11
10
0
0
0
1
0
1
1
1
0
1
B. Identify the most simple expression from the K-map shown.
(a)
(b)
(c)
(d)
(e)
F(A,B,C,D)=B'C + AD + CD
F(A,B,C,D)=BC' + BCD' + AC'D'
F(A,B,C,D)=BC' + BCD' + AB'C'D'
F(A,B,C,D)=AD + BCD' + CD
F(A,B,C,D)=BC' + BD' +AC'D'
AB
CD
01
11
10
00
1
1
1
01
1
1
1
1
00
11
10
M. K. Uyguroğlu, H. Demirel
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
C. Identify the most simple Product of Sums (POS) expression which generates the K-map
shown.
(a)
(b)
(c)
(d)
(e)
AB
F(A,B,C)=(A+C')(A+B+C)
F(A,B,C)=(A+B)(A+C')(B+C')
F(A,B,C)=(A'+B')(A'+C)(B'+C)
F(A,B,C)=(A'+C)(A'+B'+C')
F(A,B,C)=(A+B)(A'+C)(B'+C)
C
00
01
11
10
0
1
0
0
0
1
1
1
0
1
D. The most reduced expression which can be
obtained from the K-map illustrated is:
(a)
(b)
(c)
(d)
(e)
F(A,B,C,D)=A + D
F(A,B,C,D)=C
F(A,B,C,D)=A + B
F(A,B,C,D)=A
F(A,B,C,D)=A + B + D
AB
CD
00
01
11
10
x
1
1
01
x
x
1
1
11
x
x
1
1
x
1
1
10
M. K. Uyguroğlu, H. Demirel
00
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 3 (10 points):
a) Construct a 16 X 1 multiplexer by using 5 4x 1 multiplexers. Use block diagrams.
M. K. Uyguroğlu, H. Demirel
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
b) Construct a 2-to-4-line decoder by using a 1-to-4 Demultiplexer. Use block diagrams.
Question 4 (10 points):
Implement the following Boolean function with a 4 x 1 multiplexer:
F(A, B, C, D) = Σ (0, 1, 3, 4, 8, 9, 15)
Minterm
A
BCD
F
0
0 0 0 0
1
1
0 0 0 1
1
2
0 0 1 0
0
3
0 0 1 1
1
4
0 1 0 0
1
5
0 1 0 1
0
6
0 1 1 0
0
7
0 1 1 1
0
8
1 0 0 0
1
9
1 0 0 1
1
10
1 0 1 0
0
11
1 0 1 1
0
12
1 1 0 0
0
13
1 1 0 1
0
14
1 1 1 0
0
15
1 1 1 1
1
M. K. Uyguroğlu, H. Demirel
I0= C’+D
I1=C’D’
I2= C’
I3= CD
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 5 (20 points):
Design a combinational circuit that converts a 4-bit gray code to a 4-bit binary number. Implement
the circuit using exclusive-OR gates.
Gray Code
Decimal
BINARY
A B C D W X Y Z
0
0000
0 0 0
0
0 0 0 0
1
0001
0 0 0
1
0 0 0 1
2
0011
0 0 1
1
0 0 1 0
3
0010
0 0 1
0
0 0 1 1
4
0110
0 1 1
0
0 1 0 0
5
0111
0 1 1
1
0 1 0 1
6
0101
0 1 0
1
0 1 1 0
7
0100
0 1 0
0
0 1 1 1
8
1100
1 1 0
0
1 0 0 0
9
1101
1 1 0
1
1 0 0 1
10
1111
1 1 1
1
1 0 1 0
11
1110
1 1 1
0
1 0 1 1
12
1010
1 0 1
0
1 1 0 0
13
1011
1 0 1
1
1 1 0 1
14
1001
1 0 0
1
1 1 1 0
15
1000
1 0 0
0
1 1 1 1
M. K. Uyguroğlu, H. Demirel
W= A
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 6 (20 points):
Derive the state table and the state diagram of the sequential circuit shown in Fig. FQ-6.
Z
A
X
J
Q
K
Q'
J
Q
K
Q'
Y
I0
2X1
A'
MUX
I1
S0
B
B'
Figure FQ-6
JA = x
KA= B’x’+Bx
JB= A’
KB=A+x
Y=AB
Z=A’B+x’
Present Input Next
State
State
A B
x
A B
0 0
0
0 1
0 0
1
1 1
0 1
0
0 1
0 1
1
1 0
1 0
0
0 0
1 0
1
1 0
1 1
0
1 0
1 1
1
0 0
Output Flip-flop
Input
Y Z JA KA
0 1 0 1
0 0 1 0
0 1 0 0
0 1 1 1
0 1 0 1
0 0 1 0
1 1 0 0
1 0 1 1
M. K. Uyguroğlu, H. Demirel
JB
1
1
1
1
0
0
0
0
KB
0
1
0
1
1
1
1
1
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 7 (20 points):
Design the sequential circuit specified by the state diagram of Fig. FQ-7 using T flip-flops.
000
1
0
010
0
001
1
1
0
1
0
011
1
100
0
0
1
1
0
101
110
0
1
111
Figure FQ-7
Present
Input Next
State
State
A B C
x
A B
0 0 0
0
0 0
0 0 0
1
0 1
0 0 1
0
0 1
0 0 1
1
0 1
0 1 0
0
0 1
0 1 0
1
1 0
0 1 1
0
1 0
0 1 1
1
1 0
1 0 0
0
1 0
1 0 0
1
1 1
1 0 1
0
1 1
1 0 1
1
1 1
1 1 0
0
1 1
1 1 0
1
0 0
1 1 1
0
0 0
1 1 1
1
0 0
Flip-flop
Inputs
C TA TB
1 0 0
0 0 1
0 0 1
1 0 1
1 0 0
0 1 1
0 1 1
1 1 1
1 0 0
0 0 1
0 0 1
1 0 1
1 0 0
0 1 1
0 1 1
1 1 1
M. K. Uyguroğlu, H. Demirel
TC = x’
TC
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
M. K. Uyguroğlu, H. Demirel
June 08, 2010