Digital Systems
Topic 10: Counters in VHDL
Objectives
• To understand and be able to implement:
– Sequential Circuits and Counters in VHDL
• Flip-flops in VHDL
• Counters in VHDL
– With asynchronous and synchronous reset inputs
– With enable inputs
– Implement the descriptions in Xilinx
– Simulate the descriptions in Modelsim
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Registers
• There 3 methods to explicitly insert registers
(flip-flops) into your design:
– Instantiate a flip-flop in your design
• Using schematic capture tools
• Instantiating a register component in your VHDL
design description
– Use a process that is sensitive to a signal
• Registers may also be inserted implicitly into
a design clock
– Either intentionally or unintentionally
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Registers: Level-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END latch ;
A VHDL Design Description for a gated D latch. Note
that both D and Clk are listed in the sensitivity list,
meaning that a change of state in either of these
signals will activate the process.
ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS ( D, Clk )
BEGIN
IF Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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Registers: Level-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS ( D, Clk )
BEGIN
IF Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
8/18/2010
A VHDL Design Description for a gated D latch. Note
that both D and Clk are listed in the sensitivity list,
meaning that a change of state in either of these
signals will activate the process.
This is also a sample of implicitly inserting a register
into the design (this was done intentionally).
Within the process it is stated that:
If Clk=‘1’ then
Q<=D;
This explicitly states what is to be done if the clock
signal goes high: Q is to be assigned the value of D.
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Registers: Level-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS ( D, Clk )
BEGIN
IF Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
A VHDL Design Description for a gated D latch. Note
that both D and Clk are listed in the sensitivity list,
meaning that a change of state in either of these
signals will activate the process.
This is also a sample of implicitly inserting a register
into the design (this was done intentionally).
Within the process it is stated that:
If Clk=‘1’ then
Q<=D;
This explicitly states what is to be done if the clock
signal goes high: Q is to be assigned the value of D.
Nothing is stated about what is to be done with Q if
the clock signal is low. This (as far as VHDL is
concerned) implies that Q should not change: that it
should remain the same, that Q should remember
and retain its previous state.
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Registers: Level-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS ( D, Clk )
BEGIN
IF Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Note also that the code above describes a leveltriggered D latch.
8/18/2010
A VHDL Design Description for a gated D latch. Note
that both D and Clk are listed in the sensitivity list,
meaning that a change of state in either of these
signals will activate the process.
This is also a sample of implicitly inserting a register
into the design (this was done intentionally).
Within the process it is stated that:
If Clk=‘1’ then
Q<=D;
This explicitly states what is to be done if the clock
signal goes high: Q is to be assigned the value of D.
Nothing is stated about what is to be done with Q if
the clock signal is low. This (as far as VHDL is
concerned) implies that Q should not change: that it
should remain the same, that Q should remember
and retain its previous state.
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Registers: Edge-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
A VHDL Design Description for an edge-triggered D
flip-flop. Note that now, only Clk is in the sensitivity
list, meaning that a change of state of the Clk will
activate the process.
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS (Clk )
BEGIN
IF Clk’EVENT AND Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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Registers: Edge-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS (Clk )
BEGIN
IF Clk’EVENT AND Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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A VHDL Design Description for an edge-triggered D
flip-flop. Note that now, only Clk is in the sensitivity
list, meaning that a change of state of the Clk will
activate the process.
The If statement has also changed: it now has:
If Clk’EVENT AND Clk = ‘1’ then
“ ‘EVENT” is an attribute of the signal “Clk”. In this
case the ‘EVENT attribute refers to any change in
the state of the Clk signal.
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Registers: Edge-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS (Clk )
BEGIN
IF Clk’EVENT AND Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
A VHDL Design Description for an edge-triggered D
flip-flop. Note that now, only Clk is in the sensitivity
list, meaning that a change of state of the Clk will
activate the process.
The If statement has also changed: it now has:
If Clk’EVENT AND Clk = ‘1’ then
“ ‘EVENT” is an attribute of the signal “Clk”. In this
case the ‘EVENT attribute refers to any change in
the state of the Clk signal.
Combining the ‘EVENT condition with the Clk=‘1’
condition means that: “the state of the Clk signal has
just changed (the event) and is now 1.” So, this
statement describes a positive edge-triggered Clk
signal, so that Q will change (if D has changed) on
the positive edge of the Clk.
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Registers: Edge-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS (Clk )
BEGIN
IF Clk’EVENT AND Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Hands-On: Change the description above to describe a
negative edge-triggered D flip-flop.
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A VHDL Design Description for an edge-triggered D
flip-flop. Note that now, only Clk is in the sensitivity
list, meaning that a change of state of the Clk will
activate the process.
The If statement has also changed: it now has:
If Clk’EVENT AND Clk = ‘1’ then
“ ‘EVENT” is an attribute of the signal “Clk”. In this
case the ‘EVENT attribute refers to any change in
the state of the Clk signal.
Combining the ‘EVENT condition with the Clk=‘1’
condition means that: “the state of the Clk signal has
just changed (the event) and is now 1.” So, this
statement describes a positive edge-triggered Clk
signal, so that Q will change (if D has changed) on
the positive edge of the Clk.
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Registers: Edge-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
The only change that must take place is to change
the “Clk’EVENT AND Clk = ‘1’ to when these two
occurrences equal 0.
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS (Clk )
BEGIN
IF Clk’EVENT AND Clk = ‘0' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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Registers: Edge-Triggered D Latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS (Clk )
BEGIN
IF Clk’EVENT AND Clk = ‘0' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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The only change that must take place is to change
the “Clk’EVENT AND Clk = ‘1’ to when these two
occurrences equal 0.
Xilinx synthesized the code above to the circuit
below.
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Registers: Wait Until
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clk’EVENT AND Clk = ‘0' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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The WAIT UNTIL clause can also be used to
describe an edge-triggered flip-flop. When a WAIT
UNTIL clause is used, the sensitivity list is removed
from the process statement because this statement
implies that the clock signal is the only signal that will
trigger the process.
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Registers: Wait Until
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clk’EVENT AND Clk = ‘0' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
8/18/2010
The WAIT UNTIL clause can also be used to
describe an edge-triggered flip-flop. When a WAIT
UNTIL clause is used, the sensitivity list is removed
from the process statement because this statement
implies that the clock signal is the only signal that will
trigger the process.
In some (but not all) CAD synthesis tools the WAIT
UNTIL is redundant with “ ‘EVENT”. It is included
here as good practice and because it is not known
which CAD tool you will use after graduation.
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Registers: Wait Until
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT (D, Clk: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clk’EVENT AND Clk = ‘0' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
The WAIT UNTIL clause can also be used to
describe an edge-triggered flip-flop. When a WAIT
UNTIL clause is used, the sensitivity list is removed
from the process statement because this statement
implies that the clock signal is the only signal that will
trigger the process.
In some (but not all) CAD synthesis tools the WAIT
UNTIL is redundant with “ ‘EVENT”. It is included
here as good practice and because it is not known
which CAD tool you will use after graduation.
So: Why use the WAIT UNTIL instead of the IF?
When the Clk’EVENT AND Clk = ‘x’ statement is used in an IF statement, any signals that are assigned
values within the IF statement are implemented as outputs of a flip-flop.
When the Clk’EVENT AND Clk = ‘x’ statement is used in a WAIT UNTIL statement, any signals that are
assigned values within the entire process statement are implemented as outputs of a flip-flop.
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Registers: D FF with RESET
Many flip-flops (and counters) have a reset input. Some are synchronous, some are asynchronous.
Below is the code for two very similar, D flip-flops. Which has a synchronous reset? Which has an
asynchronous reset?
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT (D, Resetn, Clock: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END flipflop ;
ENTITY flipflop IS
PORT (D, Resetn, Clock: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
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Registers: D FF with RESET
Many flip-flops (and counters) have a reset input. Some are synchronous, some are asynchronous.
Below is the code for two very similar, D flip-flops. Which has a synchronous reset? Which has an
asynchronous reset?
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT (D, Resetn, Clock: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END flipflop ;
ENTITY flipflop IS
PORT (D, Resetn, Clock: IN STD_LOGIC ;
Q: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Asynchronous, the Reset signal is
outside the clock event
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Synchronous, the Reset signal is within
the clock event
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Registers: D FF with RESET
Xilinx synthesized the implementation shown below for the synchronous D flip-flop
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Counters: A 4-bit Up Counter
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
The code for a 4-bit counter with an asynchronous
reset input and an enable input (E).
ENTITY Counter IS
PORT (Clock, Reset, E: IN STD_LOGIC ;
Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ;
END Counter ;
ARCHITECTURE Behavior OF Counter IS
SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (Clock, Reset)
BEGIN
IF Reset = ‘0’ THEN
Count <= ‘0000’;
ELSIF (Clock’EVENT AND Clock = ‘1’) THEN
IF E=‘1’ THEN
Count <= Count +1;
ELSE
COUNT <= Count;
ENDIF;
ENDIF;
END PROCESS ;
Q <= Count;
END Behavior ;
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Counters: A 4-bit Up Counter
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
The code for a 4-bit counter with an asynchronous
reset input and an enable input (E).
ENTITY Counter IS
PORT (Clock, Reset, E: IN STD_LOGIC ;
Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ;
END Counter ;
ARCHITECTURE Behavior OF Counter IS
SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (Clock, Reset)
BEGIN
IF Reset = ‘0’ THEN
Count <= ‘0000’;
ELSIF (Clock’EVENT AND Clock = ‘1’) THEN
IF E=‘1’ THEN
Count <= Count +1;
ELSE
COUNT <= Count;
ENDIF;
ENDIF;
END PROCESS ;
Q <= Count;
END Behavior ;
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Count is an internal 4-bit signal that is equal to Q
Reset is asynchronous because it is outside the
Clock’EVENT AND Clock=‘1’ clause.
E enables the counter: i.e.; the counter will only
count if E=1
Count is specified explicitly (for clarity) if the counter
is not enabled.
Q is assigned the value of Count
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Counters: A 4-bit Up Counter
The code for the 4-bit counter shown in the previous slide should produce one of two circuits, depending on
whether the synthesizer chose T flip flops or ……..
Enable
Clock
T
Q
Q
T
Q
Q
T
Q
Q
T
Q
Q
Clear
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Counters: A 4-bit Up Counter
The code for the 4-bit counter shown in the previous slide should produce one of two circuits, depending on
whether the synthesizer chose T flip flops or D flip flops
Enable
D Q
Q0
Q
D Q
Q
1
Q
D Q
Q2
Q
D Q
Q3
Q
Clock
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Output
carry
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Counters: A 4-bit Up Counter
The code for the 4-bit counter shown in the previous slide should produce one of two circuits, depending on
whether the synthesizer chose T flip flops or D flip flops
Enable
D Q
Q
0
Q
D Q
Q
1
Q
D Q
Q
2
Q
D Q
Q
3
Q
Clock
Output
carry
I decided to try it myself in Xilinx …….
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Counters: A 4-bit Up Counter
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
Although the code to the left is standard VHDL, the
Xilinx ISE produced several errors upon attempting
to synthesize.
ENTITY Counter IS
PORT (Clock, Reset, E: IN STD_LOGIC ;
Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ;
END Counter ;
ARCHITECTURE Behavior OF Counter IS
SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (Clock, Reset)
BEGIN
IF Reset = ‘0’ THEN
Count <= ‘0000’;
ELSIF (Clock’EVENT AND Clock = ‘1’) THEN
IF E=‘1’ THEN
Count <= Count +1;
ELSE
COUNT <= Count;
ENDIF;
ENDIF;
END PROCESS ;
Q <= Count;
END Behavior ;
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Counters: A 4-bit Up Counter
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
Although the code to the left is standard VHDL, the
Xilinx ISE produced several errors upon attempting to
synthesize (because of copy-paste). The file below
synthesized (the only difference is highlighted):
ENTITY Counter IS
PORT (Clock, Reset, E: IN STD_LOGIC ;
Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ; LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
END Counter ;
USE ieee.std_logic_unsigned.all ;
ARCHITECTURE Behavior OF Counter IS
ENTITY Counter IS
SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);
PORT (Clock, Reset, E: IN STD_LOGIC ;
BEGIN
Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) ;
PROCESS (Clock, Reset)
END Counter ;
BEGIN
IF Reset = ‘0’ THEN
ARCHITECTURE Behavior OF Counter IS
Count <= ‘0000’;
SIGNAL Count: STD_LOGIC_VECTOR (3 DOWNTO 0);
ELSEIF (Clock’EVENT AND Clock = ‘1’) THEN
BEGIN
IF E=‘1’ THEN
PROCESS (Clock, Reset)
Count <= Count +1;
BEGIN
ELSE
IF Reset = ‘0’ THEN
COUNT <= Count;
Count <= “0000”;
ENDIF;
ELSIF
(Clock’EVENT AND Clock = ‘1’) THEN
ENDIF;
IF E=‘1’ THEN
END PROCESS ;
Count <= Count +1;
Q <= Count;
ELSE
END Behavior ;
COUNT <= Count;
Xilinx wanted double quotes around the 0s
ENDIF;
ENDIF;
assigned to Count instead of single quotes.
END PROCESS ;
Q <= Count;
END Behavior ;
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Counters: A 4-bit Up Counter
The synthesized circuit is shown below.
Double clicking on this symbol produced…..
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Counters: A 4-bit Up Counter
The logic circuit
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Counters: A 4-bit Up Counter
The logic circuit
These are positive edgetriggered D flip-flops with an
enable (CE), a clock (C), a
reset (clr), and a D input.
The outputs are also fed
back to the input logic (as
should be done with a
counter)
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Counters: A 4-bit Up Counter
The logic circuit
The input logic was different
for each D flip-flop.
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Counters: A 4-bit Up Counter
The logic circuit
The input logic was different
for each D flip-flop.
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Counters: A 4-bit Up Counter
The logic circuit
The input logic was different
for each D flip-flop.
Each also has an
associated KMap and Truth
Table.
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Simulation
The waveform below was added to the project file to see if it operated as it should
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Simulation
The waveform below was added to the project file to see if it operated as it should
E enables the counter when high. Reset should reset the counter when low.
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Simulation
The waveform below was added to the project file to see if it operated as it should
The count should change for each pulse of the clock (on the positive edge).
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Modelsim Results
The counter starts at “0000” because the reset signal was low to start
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Modelsim Results
The counter didn’t change to a “0001” until the count was enabled
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Modelsim Results
The counter didn’t change to a “0001” until the count was enabled, and continued until disabled
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Modelsim Results
Instead of seeing these numbers, some like to see the individual counter waveforms. To see them click
on the [+]
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Modelsim Results
Instead of seeing these numbers, some like to see the individual counter waveforms. To see them click
on the [+] and they can be seen.
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The Counter
• The counter is the fundamental building
block for state machines (our next topic)
• Flip-flops are the fundamental building block
for:
• Static Memory
• Counters
• Registers
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Summary
• In this topic will discussed the building
blocks for state machines
– We discussed and were able to implement:
• Sequential Circuits and Counters in VHDL
– Flip-flops in VHDL
– Counters in VHDL
» With asynchronous and synchronous reset inputs
» With enable inputs
• Implement the descriptions in Xilinx
• Simulate the descriptions in Modelsim
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