Resistivity of Gold Nanowires
Fabricated by Stencil
Lithography on Polymer
Substrates
Master Project
Mahmut Tosun
Microsystems Laboratory, LMIS1
Institute of Microengineering, IMT
School Of Engineering, STI
Ecole Polytechnique Fédérale de Lausanne, EPFL
January 2009
Supervisor: Oscar Vazquez Mena
Professor: Juergen Brugger
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Size Effects in Resistivity of Gold Nanowires Fabricated by Stencil Lithography on Polymer Substrates
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Size Effects in Resistivity of Gold Nanowires Fabricated by Stencil Lithography on Polymer Substrates
CONTENTS
CHAPTER 1. OBJECTIVES AND THEORETICAL BACKGROUND ..............................................7
A.
Motivation .............................................................................................................................7
B.
Objectives ..............................................................................................................................8
C.
Electrical resistivity and Size Effects ....................................................................................8
1.
Surface Scattering: Fuchs-Sondheimer Model (FS) .........................................................9
2.
Grain Boundary Scattering: Mayadas Shatkes Model (MS).......................................... 11
Substrates ............................................................................................................................ 14
D.
1.
Silicon Oxide .................................................................................................................... 14
2.
SU-8.................................................................................................................................. 16
3.
Parylene ........................................................................................................................... 18
4.
Polyimide ......................................................................................................................... 20
CHAPTER 2. EXPERIMENTAL PROCEDURE .............................................................................. 26
Subtrate Preparation........................................................................................................... 26
A.
1.
Silicon Dioxide ................................................................................................................. 26
2.
SU-8: Spin coating ........................................................................................................... 26
3.
Parylene : Vapor Deposition ........................................................................................... 26
4.
Polyimide: Spin coating ................................................................................................... 26
B.
Stencil Fabrication .............................................................................................................. 26
C.
Contact Pads Deposition ..................................................................................................... 29
D.
Alignment between the stencil for nanowires and the substrate ........................................ 29
E.
Nanowire Deposition ........................................................................................................... 30
F.
Characterization of the Nanowires ..................................................................................... 31
G.
Annealing Treatment ....................................................................................................... 32
1.
Current induced annealing.............................................................................................. 32
2.
Rapid Thermal Annealing (RTA) Method ...................................................................... 33
CHAPTER 3. RESULTS .................................................................................................................. 35
A.
Nanowires On Parylene ....................................................................................................... 35
B.
Nanowires on SU-8 .............................................................................................................. 38
C.
Nanowires on Polyimide ...................................................................................................... 41
D.
Annealing Treatment .......................................................................................................... 46
CHAPTER 4. DISCUSSION ........................................................................................................... 51
A.
Grain size and resistivity relation of gold nanowires in different polymer substrates ...... 51
B.
Grain size and resistivity relation of gold nanowires on silicon oxide substrate ............... 54
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CHAPTER 5. CONCLUSION .......................................................................................................... 56
CHAPTER 6. OUTLOOK ................................................................................................................ 57
ACKNOWLEDGEMENT ................................................................................................................ 58
REFERENCES ................................................................................................................................. 59
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List of Figures
Figure 1. Schematic illustration of shadow evaporation through a nanostencil (Brugger, 2000) ...........7
Figure 2. Schematic for Ohm’s law. .....................................................................................................8
Figure 3. Calculated curves for Al which show that grain boundary contributions to film resistivity can
be comparable to the Fuchs size effect if average grain diameter equals thickness (Mayadas, 1969) 12
Figure 4. Structure of Silicon dioxide (www.utas.edu.au) .................................................................. 14
Figure 5. 1,2-epoxy ring .................................................................................................................... 16
Figure 6. SU-8 molecule .................................................................................................................... 16
Figure 7. Adhesion promoters, a) HDMS b) Epoxy based promoter ................................................... 17
Figure 8. Molecular structure for parylene N (left), parylene C (middle), parylene (D) right ............... 19
Figure 9. Process of parylene deposition ........................................................................................... 19
Figure 10. Structure of an imide molecule ......................................................................................... 21
Figure 11. Structure of aromatic heterocyclic polyimide (left), linear polyimide (right) ...................... 21
Figure 12. Structure of an acceptor (left) and donor (right) ............................................................... 21
Figure 13. Charge transfer complex between polymer chains............................................................ 22
Figure 14. Schematic diagram of the apparatus used for vapor phase deposition .............................. 23
Figure 15. Different spin speed curves for cured polyimide ............................................................... 24
Figure 16. The process flow for the fabrication of stencils for the contact pads ................................. 27
Figure 17. SEM images for fabricated stencils used for the contacts depositions ............................... 27
Figure 18. The process flow for the fabrication of stencils for the nanowires..................................... 28
Figure 19. SEM images for the fabricated stencils used for the nanowire depositions. ...................... 29
Figure 20. SEM picture of a contact deposited chip ........................................................................... 29
Figure 21. SEM image of alignment markers on the substrate used to align the stencil for the wires. 30
Figure 22. SEM image of the aperture in the stencil through which the material is deposited onto the
substrate .......................................................................................................................................... 31
Figure 23. SEM images of a broken wire showing change in the morphology just before breaking. ... 32
Figure 24. SEM picture after annealing at 300C˚, grain size enhancement observed starting from the
edges. ............................................................................................................................................... 33
Figure 25. SEM images for the results of RTA treatment at 250C˚ before (left) and after (right)
showing enhancement in grain size................................................................................................... 34
Figure 26. SEM images of broken gold nanowires after annealing treatment at 300C˚ ...................... 34
Figure 27. SEM Pictures of 10µm long 80 nm width gold nanowires with contacts (left), zoom in
image (right) on parylene substrate .................................................................................................. 35
Figure 28. Grain sizes of gold nanowires on parylene extracted from SEM pictures to be 20 nm in
average. ............................................................................................................................................ 35
Figure 29. I-V curve for nanowires width of 110nm, 125nm, 145nm on parylene substrate having
resistances 325Ω, 292Ω, 228Ω respectively. ...................................................................................... 36
Figure 30. Resistance vs 1/Area plot for gold nanowires on parylene ................................................ 37
Figure 31. Left: SEM images of 3µm gold nanowire on including contacts. Right: A zoom in image of
170nm width wire. Both wires are on su8 substrate. ......................................................................... 38
Figure 32. Grain sizes of gold nanowires on su-8 extracted from SEM pictures .................................. 38
Figure 33. Height image (left) and corresponding height profile (right) taken by AFM ....................... 39
Figure 34. I-V curve for gold nanowires on su-8 substrate ................................................................. 39
Figure 35. Resistance vs 1/Area plot for gold nanowires on SU-8....................................................... 40
Figure 36. SEM pictures for gold nanowires on polyimide. ................................................................ 41
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Figure 37. SEM image of gold nanowires on polyimide substrate having an average grain size of
65nm. ............................................................................................................................................... 41
Figure 38. Height image (left) and corresponding height profile (right) taken by AFM. ...................... 42
Figure 39. SEM picture of the wire in figure 38, that doubling effect observed. ................................. 42
Figure 40. Height image (left) and corresponding height profile (right) taken by AFM. ...................... 43
Figure 41. I-V Curve for gold nanowires on Polyimide Substrate ........................................................ 44
Figure 42. Resistance vs 1/Area plot for gold nanowires on polyimide............................................... 44
Figure 43. SEM pictures of gold nanowires a) before 200C° RTA b) same nanowire in (a) after 200C°
RTA c) before 250C° RTA d) same nanowire in (c) after 250C° RTA e) before 300C° RTA f) same
nanowire in (e) after 300C° RTA. All the nanowires were fabricated in the same deposition.............. 46
Figure 44. a) AFM image for a nanowire before 250C° RTA. Height image (left) Corresponding profile
(right) b) AFM image for a nanowire after 250C° RTA. Height image (left) Corresponding profile
(right) ............................................................................................................................................... 48
Figure 45. a) I-V curve for gold nanowires before RTA at 250C° b) I-V curve for gold nanowires after
RTA at 250C° ..................................................................................................................................... 49
Figure 46. Resistance vs 1/Area curve for after and before annealing................................................ 49
Figure 47. A film on a substrate showing surface energy and the interface energy of a grain with the
substrate. ......................................................................................................................................... 52
Figure 48. SEM images of different grain sizes of gold nanowires on different substrates (parylene,
su8 and polyimide) as a result of the different interface energy between the grains and the substrate.
......................................................................................................................................................... 53
Figure 49. Average Grain size vs Resistivity graph for gold nanowires on polymer substrates
respectively from highest grain size: Polyimide, Su-8, Parylene ......................................................... 53
Figure 50. SEM image for nanowires before(left) and after(right) annealing at 250C° ........................ 54
Figure 51. Average Grain Size with respect to resistivity of gold nanowires on different substrates.
Respectively from highest resistivity: Gold nanowires on Parylene, Silicon oxide (before RTA), SU-8,
Silicon oxide (after RTA) and Polyimide. ............................................................................................ 55
Figure 52. AFM tips having a radius smaller than 10nm can be used as probes in a proper setup to
analyze the effect of surface scattering on a single gold grain. .......................................................... 57
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CHAPTER 1. OBJECTIVES AND THEORETICAL
BACKGROUND
A. Motivation
As the electronic systems and devices scales down, the electrical transport properties in
metals change and can not be described with the same equations used for bulk materials. In
the case of nanowires, when their dimensions approach to the range of the mean free path of
the electrons, the resistivity of the nanowires increases as a result of the emerging size effects.
These effects are grain boundary and surface scattering that leads to an increase in resistivity
for confined systems in lateral dimensions.
Besides the scaling down in the size, there is also a new revolution in the materials used for
new devices. Recently, polymer substrates are taking attraction because of their unique
properties of biocompatibility and mechanical properties such as flexibility and elastic
modulus, along with their potential for cost reduction.
Stencil lithography is used in the fabrication of nanowires since this method is an ultra clean
and quick process to fabricate nano-sized structures. The most important feature of stencil
lithography is there is no lift-off or resist processes are involved in this fabrication technique.
This feature enables nanostencil technique to be applied in arbitrary surfaces. (1) This makes
stencil lithography an interesting tool for studying size effects on polymeric substrates. In
Figure 1 the procedure for deposition by stencil lithography is illustrated.
Figure 1. Schematic illustration of shadow evaporation through a nanostencil (Brugger, 2000)
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B. Objectives
The two main objectives of this project are:
1. Study the resistivity of gold nanowires deposited by stencil lithography on polymer
substrates.
2. Modify the grain structure of metallic nanowires by annealing and explore its
effect on its resistivity.
C. Electrical resistivity and Size Effects
Electrical resistances of conducting materials are characterized by the Ohm’s law. Ohm’s law
states that in an electrical device, current flowing through a conductor is directly proportional
to the applied potential and inversely proportional to the resistance between two points. In
Figure 2, a schematic of an electrical circuit is presented to demonstrate the ohm’s law where
the resistance of the conductor is defined by the resistivity (ρ), length of the conductor (L) and
the cross sectional area of the conductor (A).
Figure 2. Schematic for Ohm’s law.
As the systems scales down, the size effects have become more relevant to design and
fabricate new devices. The understanding of such size effects is of great importance for the
development of new devices.
If the dimensions of a metallic conductor are comparable or smaller than the mean free path
of the electrons in this material, the electrical resistivity of the conductor increases compared
to its bulk value as a result of the size effects. The electrical transport properties are
established for diffusive transport regime by the well known relationship
and for
ballistic transport regime Landauer-Büttiker formalism. (2) For the range in between these
two regimes, where the dimensions of the conductors are comparable to the mean free path of
the electrons, the first studies were on size effects were done by Fuchs on the resistivity of
thin films. (3) Afterwards, with Fuchs-Sondheimer model (FS), the theory also explained the
resistivity in thin wires. (4) The model proposed by Fuchs-Sondheimer relates the increase in
the resistivity to the scattering of the electrons at the external surfaces of the films or wires.
Later, Mayadas and Shatzkes developed a model (MS), that included the effects of the
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electron scattering at the grain boundaries and showed that grain boundary effects must make
a major contribution to the measured resistivity of films. (5)
1. Surface Scattering: Fuchs-Sondheimer Model (FS)
For thin films, firstly, to compare the conductivities of thin films to the bulk value, the
simplest assumption is that every free path is terminated by collision at the surface, so that the
scattering is modeled as being entirely diffuse. After calculations the results obtained are as
follows.
Where
a: thickness and l:mean free path of electrons
For thick films,
where к>>1
For thin films,
where к<<1
A more general model is developed without assuming that the scattering at the surface of the
film is entirely diffusive. In this model, it is assumed that a fraction p of the electrons is
scattered elastically at the surface with reversal of the velocity component vz, while the rest
are scattered diffusively losing their drift velocity completely. The fraction of the elastically
scattered electron parameter p, is supposed to be a constant independent of the direction of
motion of the electrons. Also it is assumed that in case of perfectly specular (p=1) reflection
the conductivity is not changed. (4) After the calculations the obtained comparison with the
new introduced fraction parameter p thin and thick films are as follows:
For thick films,
For thin films,
The numerical values for
where к>>1
where к<<1
(4)
for p=0 and ½ are shown in the following Table 1.
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Table 1. The resistivity of thin metallic films divided by the resistivity of the bulk metal (Sondheimer, 1952)
In the case of thin wires, the method is essentially the same. The analyses in the case of wires
are done by MacDonald and Sarginson (1950) by considering a wire of square cross section
and by Dingle (1950) by considering a wire of circular cross section. For very thick and thin
wires, obtained results are
For circular thick wires,
For circular thin wires,
where к>>1
where к<<1
For square thick wires the equation for circular wires is also consistent however for square
thin wires,
(4)
The numerical values for
for a cylindrical wire are shown in Table 2.
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Table 2. The resistivity of thin wires divided by the resistivity of the bulk metal (Sondheimer, 1952)
2. Grain Boundary Scattering: Mayadas Shatkes Model (MS)
MS model was developed in order to estimate the effects due to electron scattering from grain
boundaries. In bulk materials, grain boundary scattering is negligible since the length of
electron mean free path is smaller than the grain diameter. However, this model is related to
fine grain structured materials such as polycrystalline metal films. (5)
In terms of the Fuchs size effect theory, surface scattering is placed over the “intrinsic” or
thickness-independent scattering from the film interior.
Results can be expressed by the relation
ρ: Observed (film) resistivity, p: fraction of electrons specularly reflected at external surfaces,
a:film thickness,
: intrinsic electron mean free path
In the Fuchs relation, by assuming that intrinsic resistivity and intrinsic mean free path are
constant with the film thickness, observed film resistivity and thickness curves generally fitted
with the boundary condition of p≈0 in polycrystalline films and p≈0.5 in single crystal films.
However it was clear that the assumption of intrinsic resistivity being constant with the film
thickness was invalid for polycrystalline Al films. In Mayadas’ studies, it was observed that
intrinsic resistivity is decreased significantly with increasing film thickness. Another study
from Mayadas also showed that Al in films deposited onto quartz substrates at 200C0, the
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average grain diameter D, increases with the film thickness. As the film thickness increased
the intrinsic resistivity decreases and grain diameter increases. Therefore it is possible that
grain boundaries provide a thickness dependent component to the film resistivity. (5)
In MS model, grain boundaries are represented as N parallel partially reflecting planes,
located perpendicular to the electric field E and placed at an average random distance d apart,
identified with scattering potentials height(energy) U and width w. Electron scattering is
predicted as a result of point defects, and phonons and described by a relaxation time . The
resulting equation for the corresponding resistivity is (5) :
Where
: background mean free path, R: reflection coefficient, d: average random distance,
: Total conductivity due to both the grain boundaries and background scattering
: Conductivity from the interior of grains
Figure 3. Calculated curves for Al which show that grain boundary contributions to film resistivity can be comparable to
the Fuchs size effect if average grain diameter equals thickness (Mayadas, 1969)
As seen in Figure 3, an estimation for the strength of grain boundary scattering can be done by
assuming
=75000Å at 4.2K˚ for evaporated Al films. In Figure 3,
vs d was plotted for
=75000Å where in curve A, reflection coefficient R is taken to be 0.2; and for curve C, R is
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taken to be 0.1. For the curves A and C, the fraction of specularly reflected electrons p is
taken to be 1, which means that all the electrons are elastically reflected without contributing
the resistivity. In curve B, resistivity vs thickness is plotted from the Fuchs theory by
assuming the specularity coefficient p to be 0 and
=75000Å. It can be observed from the
graph that the increase in the resistivity due to grain boundary scattering is significant.
Furthermore, its effect is comparable to the surface scattering effect from Fuchs theory which
is represented in curve B. (5)
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D. Substrates
1. Silicon Oxide
Silicon dioxide (SiO2) is one of the most used dielectric in microelectronics and in fabrication
of MEMS. SiO2 is formed by strong covalent bonds as seen in Figure 4.
Figure 4. Structure of Silicon dioxide (www.utas.edu.au)
SiO2 films can be produced by different methods. Most commonly used techniques are
thermal oxidation, low pressure chemical vapor deposition (LPCVD), and plasma enhanced
chemical deposition (PECVD).
Thermal oxidation of silicon requires high temperatures between 600C˚ and 1250C° in the
presence of oxygen (dry) or steam (wet). Even though silicon oxidizes at room temperature,
the thickness can’t exceed 20 Angstroms. The high temperature enables diffusion of oxidant
through the surface oxide layer to the silicon interface to form thicker oxides in a short
amount of time (6). There are two reaction routes for oxidation of silicon:
Si+2H2O →SiO2 + H2 (wet)
Si + O2→SiO2 (dry)
There is a relation between the grown oxide and consumed silicon. The amount of silicon
consumed is 46% of the final oxide thickness (6).
Xs= 0.46 Xox
Xs : Silicon thickness converted
Oxide growth rate is given by:
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Xox : Resulting oxide thickness
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(6)
Ci : Concentration of oxidant at the interface oxide silicon
Ks : Oxidation rate constant
N: Number of molecules of oxidant per unit volume of oxide.
Thermal oxidation is a self limiting process; therefore maximum practical film thickness that
can be obtained with this method is about 2µm however this amount is sufficient for many
applications. (7)
LPCVD is another common method used to produce silicon dioxide wafers and has some
advantages when compared to thermal oxidation.
Mostly, silicon films which are deposited by the LPCVD technique are thick ( >2µm) and
produced at lower temperature than thermal oxidation. These films are called low temperature
oxides (LTO) and they have a higher etch rate in hydrofluoric acid (HF) than thermal oxides.
Therefore low temperature oxides have a faster release time when they are used as sacrificial
layers. (7) Also LPCVD allows producing large numbers of wafers at the same time. One
disadvantage of LPCVD is the low deposition rate. (6)
PECVD is another common used technique to produce silicon oxide. In this process a plasma
is used to dissociate the gaseous precursors. The advantage of PECVD when compared to
LPCVD is that low temperatures are needed to deposit in PECVD technique. (7) PEVCD
enables the deposition of oxides on wafers with small sizes and the ones which are not able to
withstand high temperature treatment techniques such as thermal oxidation and LPCVD.
Silicon oxide is immensely used in MEMS technology. Silicon oxide is easy to dissolve using
etchants therefore it is used as a sacrificial material in various fabrication techniques. Silicon
oxide is also chemically resistant to dry etching processes that enables silicon oxide to be used
as an etch mask for silicon dry etching processes. Silicon oxide films can also be as
passivation layers on the surfaces of environmentally sensitive devices. (7)
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2. SU-8
SU-8 was originally developed as a negative photo resist in the fabrication of advanced
semiconductor devices.
Chemically, SU-8 is based on epoxies. Epoxy refers to an oxygen atom that is bonds with two
other atoms generally carbon as in the Figure 5.
Figure 5. 1,2-epoxy ring
Molecules that have one or more 1,2 epoxy groups, are able to be converted to a thermoset
form or three dimensional network structure. This process is called cross linking. As a result
of the highly cross linked material in the material, SU-8 is thermally stable up to 200C˚ and
chemically stable. The molecular structure of SU-8 molecule is composed of epoxy groups as
in Figure 6.
Figure 6. SU-8 molecule
Here there are some chemical and physical properties of SU-8
Young's modulus E : 4.4 GPa
Poisson's coefficient : 0.22
Viscosity :
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40% SU8-60% solvent : 0.06 Pa.s
60% SU8-40% solvent : 1.5 Pa.s
70% SU8-30% solvent : 15 Pa.s
Coefficient of thermal expansion CTE : 50 ppm/K
Thermal conductivity : 0.2 W/m K
Glass temperature Tg: 200C˚
Degradation Temperature ~380C˚
Relative dielectric constant : 3 at 10 MHz (8)
SU-8 is commonly deposited using spin-coating method. The first step in SU-8 deposition is
the dehydration of the substrate. This step is done under 200C˚ for 1 hour in order to get rid of
the water molecules on the substrate. This step should not be done if the deposition will be
done for a substrate that has an existing SU-8 layer.
Adhesion promoters are used in order to increase the adhesion of SU-8 onto the glass or
silicon wafers. One of the most used adhesion promoters is HDMS (Hexamethyldisilazene)
represented in Figure 7. Another material used in order to promote the adhesion of SU-8 is an
epoxy based promoter. This molecule has on one side methyl groups that stick on glass or
silicon and on the other side it has an epoxy group that reacts with SU-8 as can be seen in
Figure 7.
(a) HMDS
(b) Epoxy based promoter
Figure 7. Adhesion promoters, a) HDMS b) Epoxy based promoter
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Finally a soft baking is done in order to remove all the solvent in the layer. This is done on a
flat and horizontal hot plate and the duration depends on the layer thickness.
SU-8 has unique properties that enable a wide variety of applications in MEMS processing. It
is used as a photoresist in order to pattern other layers. It is also used as a structural material
like micro fluidic devices, inkjet nozzles and AFM probe tips. SU-8 is also used as an
electroplating mold, a wafer bonding material and a packaging coating. In addition it has been
investigated for many other applications, such as a low-cost material for the fabrication of
large micro mirror arrays. The main market for SU-8 is as a photopolymer for devices such as
inkjet heads and optical waveguides.
PMMA is the most commonly used photoresist in x-ray lithography. As an alternative, SU-8
has absorption characteristics very similar to PMMA but SU-8 is more sensitive and requires
shorter exposure time than PMMA. SU-8 can be used in both x-ray LIGA and UV LIGA
applications. The chemical resistance of SU-8 has been exploited to form micro channels,
inkjet components, and micro arrays for bio-analysis. The advantages of SU-8 for inkjet heads
are high precision, good mechanical properties compared to other resists and lower fabrication
costs. Moreover, as a result of its optical properties, SU-8 applications have emerged in a
wide range of sensors and actuators such as AFM cantilevers, integrated strain sensors
elements and as integrated waveguides for bio separation and analysis.
Another emerging application field of SU-8 is in packaging. Since SU-8 has a low cost, easy
to process wafer capability, it is widely used in packaging coating. However a drawback of
SU-8 is it offers a relatively soft protection layer with low mechanical resistance as compared
to silicon and glass. (9)
3. Parylene
There are various derivatives and isomers of parylene. Some of them commercially available
are parylene N, parylene D and parylene C. Their molecular structure can be seen in Figure 8.
Parylene N has the highest dielectric strength of the three versions. Its dielectric constant
value is independent of frequency. It is able to penetrate crevices more effectively than the
other two versions since its level of molecular activity that occurs during deposition is higher.
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Parylene N is generally used in high frequency applications because of its low dissipation
factor and dielectric constant values.
Parylene C differs chemically, having a chlorine atom on the benzene ring which enables a
useful combination of electrical and physical properties including particularly low moisture
and gas permeability. This version deposits on substrates faster than Parylene N, with a
consequent reduction in crevice penetration activity.
Parylene D has two chlorine atoms added to the benzene ring. This gives the resulting film
greater thermal stability than either Parylene N or C. It has reduced ability to penetrate
crevices compared to Parylenes N and C. (10)
Figure 8. Molecular structure for parylene N (left), parylene C (middle), parylene (D) right
Apart from its unique properties of biocompatibility, parylene is also an attractive material in
terms of its fabrication process. Parylene can be deposited at room temperature by CVD.
As can be seen in Figure 9, the process of depositing parylene can be summarized in three
steps which are vaporizing, pyrolizing and deposition.
Figure 9. Process of parylene deposition
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First step is the vaporization of the raw material dimer at 150C˚. Afterwards, the dimer
undergoes pyrolisis process at the two methylene-methylene bonds at about 680C˚ to yield the
stable monomeric diradical, para-xylylene. As a final step, the monomer adsorbs and
polymerizes at the same time, in the room temperature deposition chamber. During the
process the temperature of the substrate does not raise more than few degrees above the
ambient temperature. (11)
Parylene has applications in electronics, medicine and automotive industry. Parylene
conformal coatings provide ultra thin, pinhole free protection in order to promote component
reliability. Since the deposition process is conformal, it enables parylene coatings to be
applied to prefabricated structures. For example, in Si microneedles and low stress silicon
nitride membrane particle filters, parylene coating serves to strengthen the microfabricated
structures.
In medical applications, by the unique properties of biocompability and biostability, parylenes
provide excellent moisture, chemical and dielectric barrier protection. Also, the parylene
coatings have a low friction coefficient for applications in which lubricity is a concern. Some
of the applications of parylene in medicine include stents, cardiac assist devices,
electrosurgical tools, mandrels and molds, catheters and elastomeric seals.
In automotive industry, since the environment for electronics and components is harsh, for the
required parts, parylene is able to provide barrier protection. Parylene also provides thermal
stability up to 450°C and increased UV stability. Some of the applications of parylene in
automative industry are in emission sensors, tire pressure monitoring systems and fuel cells.
(12)
4. Polyimide
Polyimides are a very interesting group of incredibly strong and astoundingly heat and
chemical resistant polymers. Their strength, heat and chemical resistance allow them to
replace glass and metals, such as steel, in many demanding industrial applications. Strong
intermolecular forces between the polymer chains enable these properties to emerge.
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Figure 10. Structure of an imide molecule
If an imide molecule as shown in Figure 10 is polymerized, the product will be a polyimide
molecule as shown below. Polyimides generally have two structures, linear polyimide and
aromatic heterocyclic polyimide as seen in Figure 11.
Figure 11. Structure of aromatic heterocyclic polyimide (left), linear polyimide (right)
A polymer which contains a charge transfer complex consists of two different types of
monomers, a donor and an acceptor as seen in Figure 12. The donor lends some of its electrons
to the acceptor which enables the molecule to tightly stay together.
Figure 12. Structure of an acceptor (left) and donor (right)
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The charge transfer complex works not only between adjacent units in the polymer chain, but
also between chains. The chains will stack together like strips of paper, with donors and
acceptors paired up. This charge transfer complex holds the chains together very tightly as
seen inFigure 13, not allowing them to move around. When things can't move around on the
molecular level, they can't move around in the whole material. This is why polyimides are so
strong. (13)
Figure 13. Charge transfer complex between polymer chains
In the deposition of polyimide to the wafers, various methods used such as vapor phase
deposition and spin coating.
In their article, Atsushi Kobono et al, demonstrated that direct formation of polyimide films
on silicon wafers are possible by vapor deposition polymerization with a machine as can be
seen in Figure 14. In VPD, experimental conditions for example, deposition rate, substrate
temperature and annealing temperature are key parameters in terms of the structure and the
molecular orientation of the deposited films. In terms of the chemical structure of the film is
strongly related to the substrate temperature. In their work, Atsushi Kobono et al, studied the
dependence of chemical structure and molecular orientation of polyimide films on substrate
temperature. They prepared three types of films with different substrate temperature during
deposition, 25C˚, 125C˚ and 175C˚. They observed that at a substrate temperature below
125C˚, polyamic acid films were formed whereas the ones that are deposited above 125C˚ are
transformed into polyimide films. The film prepared at 125C˚, had higher molecular
orientation, perpendicular to the substrate than those prepared at 25C˚. At substrate
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temperatures above 175C˚, the polyimide thin film was directly formed on the substrate with
normal orientation. Another observation was the polyimide film prepared at high substrate
temperature exhibited better thermal stability than the ones prepared at low substrate
temperature.
Figure 14. Schematic diagram of the apparatus used for vapor phase deposition
Polyimides can also be coated onto various substrates such as metals, alloys, semiconductors
and ceramics with the use of adhesion promoters.
Dispensing should be in the centre as close as possible to the substrate. Since polyimide is a
highly viscous solution it may be necessary to have a short delay before starting the spin in
order to allow polyimide to flow as far as possible and relax. The acceleration to final speed
should be as low as possible in order to allow gradual flow of polyimide across the substrate.
Generally one or more intermediate spin speeds are used to allow the polyimide to gradually
cover more than %80 of the substrate before going on to the final speed.
After introducing the polyimide, a bake process is required in order to partially cure the
polyimide before the patterning. In this step both convection oven and hotplate bake methods
can be used.
Then cure heating treatment converts the polyamic acid to the insoluble imide form and dries
the remaining solvent. To achieve the best results, this process requires high temperatures and
well controlled environments. In order to achieve better electrical and mechanical properties,
the solvents should be completely driven off, therefore even at 180C˚ there is enough energy
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to complete imidization, higher temperatures are required. To activate the adhesion promoter,
the cure should be carried out up until 200C˚ in air. The ramp rates should be low in order to
prevent the stress and possible cracks in the polyimide. Different spin speed curves for cured
polyimide can be seen in Figure 15.
Figure 15. Different spin speed curves for cured polyimide
(14), (15)
As a result of their complex structure constituted of strong carbon ring bonds, polyimides do
not melt nor flow as most of the thermosets and thermoplasts. Polyimide films show excellent
thermal stability up to 450C˚, good dielectric properties (ε=3.3 and a resistivity of 1016 ohmcm), higher chemical resistance, toughness, wear resistance, flame retardance, and interesting
mechanical properties as a result of their flexibility.
Jiang et al, capitalized on the strength and flexibility of polyimide to fabricate a flexible
sheer-stress sensor array based on Si sensors. The chemical and temperature stability of
polyimides enables using them as a sacrificial layer for various common used materials such
as evaporated or sputter deposited materials. In the biomedical devices fabricated by
microfabrication techniques, polyimide has a great potential in terms of its biocompatibility
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and mechanical flexibility. Polyimides are being used as passivating and interlayer dielectrics,
planarizing compounds, reactive ion masks, humidity sensitive materials. (6) (7)
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CHAPTER 2. EXPERIMENTAL PROCEDURE
A. Subtrate Preparation
1. Silicon Dioxide
200nm thick wet oxide was thermally grown on silicon wafers.
2. SU-8: Spin coating
SU-8 1040 was spinned on a silicon wafer with the following steps:
Spin speed: 2000 rpm, 40 seconds.
Exposure: 40mJ/cm2
Soft bake
Thickness: 2µm
3. Parylene : Vapor Deposition
Dimmer heated to 150C˚ to convert into vapor phase
Pyrolysis at 670C˚ to produce monomers
Deposition on silicon wafer at room temperature and under a pressure of 5µbar
Thickness: 2µm
4. Polyimide: Spin coating
Spin coating at 1000 rpm.
Soft Bake: 70C˚, 180s
100C˚ 360s
100C˚ 180s
70C˚ 360s
Hard Bake: 300C˚ 6h30m
B. Stencil Fabrication
In this process, we used stencil lithography to define the electrical contacts pads and the
nanowires. The stencils for the definition of the electrical pads contain apertures in the 10µm500µm range. In the case of the stencils used for the deposition of the nanowires the smallest
feature is ~30nm. These sizes determine the thickness of the silicon nitride used to fabricate
the stencils. For the stencils for electrical contacts, a 500 nm thick LS SiN (low stress silicon
nitride) membrane was used, whereas a 100 nm thick LS SiN membrane was used for the
stencils for the nanowires.
The process flow for the fabrication of stencils for the contact pads is illustrated in Figure 16.
A 500 nm thick LS SiN was deposited on conventional 100 mm diameter, 540 µm thick,
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silicon wafers by chemical vapor deposition. Then, using UV lithography ( = 390 nm) and
SiN dry etching the front side of the wafer is patterned with apertures that will later become
the stencil apertures. By the same method, the SiN on the backside of the wafer is patterned to
etch the bulk silicon by KOH and release the silicon nitride membranes on the front side.
Figure 17 shows the fabricated stencils used for the contacts depositions.
Figure 16. The process flow for the fabrication of stencils for the contact pads
Contact
pads
apertures
Contact
pads
apertures
Figure 17. SEM images for fabricated stencils used for the contacts depositions
The process flow for the fabrication of stencils for the definition of nanowires is illustrated in
Figure 18. A 100 nm thick LS SiN was deposited on conventional 100 mm diameter, 540 µm
silicon wafers by chemical vapor deposition. Then, using electron beam lithography (EBL)
and SiN dry etching the front side of the wafer is patterned with apertures that will later
become the stencil apertures (nanoslits). Then, the backside of the wafer is patterned by UV
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lithography to define apertures through which the bulk silicon will be etched to release the
membranes. The bulk silicon is etched in two steps. First, by deep reactive ion etching, 500
µm of silicon are etched using a Bosch (dry) process. Then, the resist is removed by oxygen
plasma. Finally, a KOH bath is used to etch the last 40 µm of silicon to release the silicon
nitride membranes on the front side. Figure 19 shows the fabricated stencils used for the
nanowire depositions.
Figure 18. The process flow for the fabrication of stencils for the nanowires
Aperture
for
nanowire
depositon
Apertures
for contact
depositon
Aperture for nanowire depositon
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50nm width aperture for nanowire depositon
Figure 19. SEM images for the fabricated stencils used for the nanowire depositions.
C. Contact Pads Deposition
In the deposition procedure, we first evaporated the contacts using the stencil for contact
deposition. In Figure 20, an SEM picture of a contact deposited for a seven device chip can be
seen. The stencils are just put on top of a blank substrate (silicon oxide, parylene, SU-8 and
polymide).
Deposited contact pads (Au)
Silicon oxide (Substrate)
Figure 20. SEM picture of a contact deposited chip
For the contact deposition we used the machine LAB600, e-beam evaporator at CMI. The
materials used in the evaporation are, 5nm of titanium and 45 nm of gold. Titanium is used as
an adhesion layer.
D. Alignment between the stencil for nanowires and the substrate
After depositing the contacts, in order to be able to do the electrical characterization, a
micrometric positioning between the contact pads and the nanowires is required. For aligning
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the stencil for nanowires and the substrates we used the machine double side mask aligner and
bond alinger MA&BA6 at CMI. When the contacts are evaporated, in the stencil for the
contacts, there are predefined apertures to define alignment markers along with the contact
pads. SEM image of deposited alignment markers can be seen in Figure 21.
Figure 21. SEM image of alignment markers on the substrate used to align the stencil for the wires.
With the help of the alignment markers on the substrate and alignment apertures on the
stencils for nanowires deposition, we can align the substrate and the stencil. A fixture is used
to hold aligned the stencil and the substrate.
E. Nanowire Deposition
After aligning the stencil and the substrate, the fixture is placed in the LAB600 evaporator.
Using LAB600, the e-beam evaporator, a 45nm thick gold is deposited through stencil. The
deposition rate is 4 Angstroms per second. In Figure 22, a stencil aperture can be seen. It
shows a nanoslit through which the material will pass and form a nanowires on the substrate.
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Nanoslit
Figure 22. SEM image of the aperture in the stencil through which the material is deposited onto the substrate
F. Characterization of the Nanowires
For the characterization of nanowires, SEM, AFM and DC measurements are used in order to
extract the resistivity of the nanowires.
SEM images are taken to extract the width of the nanowires. Zeiss Leo 1550 Scanning
Electron Microscope was used at CMI. Acceleration voltages for the electrons varied from
1kV to 10kV in order to get better resolution for gold nanowires on polymer substrates. For
wires on silicon oxide substrate usually acceleration voltage used was 3kV.
AFM images are taken to extract the thickness of the nanowires. The AFM images were
performed using a Nanoscope III instrument using Tapping Mode imaging.
Two probe measurements are done to obtain the I-V curves and the resistance of the wires.
The manual probe station Karl Süss PM8 at CMI was used. A DC voltage ranging from
10mV to -10mV was used for the I-V measurements with the HP Network Analyzer.
Measured resistances of the wires consist of two components, when the derivative of the
resistances is taken with respect to 1/A, resistivity of the nanowires is extracted.
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A: Area of the cross section of the nanowires
L: Length of the nanowires
Areas of the nanowires are calculated by multiplying the thickness and the width extracted
from AFM and SEM respectively. In order to extract the resistivity of nanowires, the average
data of 14 wires having different cross sectional areas are used. In some of the chips due to
the breaking of the nanowires less than 14 wires are used.
G. Annealing Treatment
In order to study the effect of grain size on the resistivity of nanowires, we tried two different
annealing methods to change the morphology of the nanowires by enhancing the grain size.
One of them is current induced annealing and the other one is thermal annealing by using
rapid thermal annealing method. Annealing treatment was only applied to the oxide substrates
but not for polymer substrates.
1. Current induced annealing
In this approach our motivation was to get the change in the morphology of the nanowires that
we observed in the broken wires before breaking the wire.
Change in morphology
Figure 23. SEM images of a broken wire showing change in the morphology just before breaking.
As can be seen in Figure 23, there is a change in the morphology of the wire in the edges
where the wire detached. From previous experience, we observed that nanowires are breaking
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down at around 500mV. Therefore, a voltage of 400mV applied to the wires for 20 seconds to
5 minutes. (16) However there was no observable change in the morphology of the wires were
obtained. This process is quite difficult to control since there is no fixed current density and
time parameters for the wires. By going to higher voltages, the wires just broke abruptly. This
process did not give satisfactory results for annealing. Most of the wires treated by this
method ended up braking down.
2. Rapid Thermal Annealing (RTA) Method
In RTA method, we cleaved the substrate into twelve chips in order to try different
temperatures and different durations. The nanowires were annealed at, 200C°, 250C° and
300C° for ten minutes. It is observed from SEM images that the annealing of the grains start
from the edges and grains consume each other resulting in the formation of bigger grains as
can be seen in Figure 24.
Grain size
enhancement
starts from the
edges
Figure 24. SEM picture after annealing at 300C˚, grain size enhancement observed starting from the edges.
As can be observed from the SEM images in Figure 25, the enhancement of the grain sizes are
significant. This images are taken before RTA treatment (on the left) and after RTA treatment
(on the right) of 250C° and for ten minutes. It is observed that a temperature of 250C° and
duration of ten minutes were the best parameters to change the morphology. For RTA
treatment at 300C° it is observed from the SEM images taken after that the wires could not
stand an annealing temperature of 300C° and most of the narrow wires were broken as seen in
Figure 26.
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Grains
Grain size enhanced
Figure 25. SEM images for the results of RTA treatment at 250C˚ before (left) and after (right) showing enhancement in
grain size.
Broken
nanowire
Broken
nanowire
Figure 26. SEM images of broken gold nanowires after annealing treatment at 300C˚
The results of RTA treatment enabled us to study the effect of grain sizes in the resistivity of
nanowires. These results are shown and discussed in more detail in the following sections.
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CHAPTER 3. RESULTS
A. Nanowires On Parylene
We studied the resistivity of 10 µm and 20 µm long gold nanowires on parylene substrates.
The width of the nanowires ranged from 80nm to 3µm. In Figure 27, there is a zoom out SEM
picture of the nanowire with the contacts and a zoom in SEM picture of the nanowire 80nm
width.
The
widths
of
10µm long Au nanowire
the
nanowires
are
extracted
from
the
SEM
images.
Contact Pads
80nm width Au nanowire
Figure 27. SEM Pictures of 10µm long 80 nm width gold nanowires with contacts (left), zoom in image (right) on parylene
substrate
High magnification SEM images are taken to measure statistically the diameter of the grains
as can be seen in Figure 28. The grain size of the Au nanowires deposited on parylene was
20±1 nm.
Grains
Au nanowire
Parylene (Substrate)
Figure 28. Grain sizes of gold nanowires on parylene extracted from SEM pictures to be 20 nm in average.
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As discussed in the experimental section, AFM was used to determine the height of the
nanowires. Unfortunately, AFM scanning on parylene was not possible due to some problems
during scanning. Probably the reason was sticking between the scanning tip and the parylene
substrate, but the precise reason was not clear. However, measurement of nanowires deposited
on polyimide, SU-8 and silicon dioxide allows us to infer that the thickness of the nanowires
are similar on different substrates and corresponds to ~37 nm. This is thinner than the
nominal value of 50 nm of Ti/Au indicated by the crystal of the evaporator used to deposit the
nanowires.
For the I-V measurements a voltage from -5mV to 5mV was applied on the nanowires. An
ohmic behavior was observed in the I-V curves of the nanowires can be seen in Figure 29. It
can be seen from the slope of I-V line that as the wire width decreases, the resistance of the
wires increases as expected.
Figure 29. I-V curve for nanowires width of 110nm, 125nm, 145nm on parylene substrate having resistances 325Ω, 292Ω,
228Ω respectively.
By using the thickness and width extracted from the AFM and SEM images respectively,
cross section area of the wires calculated. Using the derivative of the resistance with respect
to 1/Area, the resistivity of the nanowires can be extracted as explained in nanowire
characterization (Experimental Section) part.
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Figure 30 shows the resistance as a function of the cross-section of the nanowires that were
measured. It can also be observed that, as the cross section area of the wires decreases, there
is an increase in the measured resistance observed both in 10µm and 20µm as expected as
well from the expression R=ρL/A.
Figure 30. Resistance vs 1/Area plot for gold nanowires on parylene
The resistivity of gold nanowires calculated was 9,54 µ
times of the bulk value of the gold which is 2,44 µ cm.
37
cm. These values are almost four
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B. Nanowires on SU-8
For Au nanowires on SU-8 substrate, the resistivity is investigated for wire lengths of 20µm
and 10µm which ranged from 145nm to 3µm in width. In the characterization, 14 wires 20µm
long, 10 wires 10µm long were used. SEM pictures of the Au nanowires can be seen in Figure
31. The image on the left shows the nanowires and the predefined contacts. The right image
shows the morphology of a 170nm wide nanowire.
Contact
sss
SU-8 (Substrate)
170nm width nanowire
3µm width nanowire
Figure 31. Left: SEM images of 3µm gold nanowire on including contacts. Right: A zoom in image of 170nm width wire.
Both wires are on su8 substrate.
SEM pictures were used to measure the width and estimate grain sizes of the nanowires as
seen in Figure 32. For gold nanowires on su-8, the grain size was extracted to be around
32±2nm.
SU-8 (Substrate)
Grains
170 nm width Au nanowire
Figure 32. Grain sizes of gold nanowires on su-8 extracted from SEM pictures
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AFM measurements are done to extract the thickness of the wires. As seen in other substrates,
the thickness was around 37 nm. Height image and the corresponding height profile of the
nanowires on su-8 substrates can be seen in Figure 33.
Figure 33. Height image (left) and corresponding height profile (right) taken by AFM
I-V measurements were done under an applied electric bias of -5mV to 5mV and measuring
the induced electrical current. Nanowires having different width are measured in order to
extract the resistivity. As expected, as the width decreases, the electrical resistance increases.
I-V curves for the nanowires on SU-8 substrate are shown in Figure 34.
Figure 34. I-V curve for gold nanowires on su-8 substrate
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In the Figure 35, it is also clear that as the cross sectional area decreases the resistance of the
wires increase both in 10µm and 20µm length wires.
Figure 35. Resistance vs 1/Area plot for gold nanowires on SU-8
The procedure to extract the resistivity is explained in the experiental part. The resistivity for
the gold nanowires found was 8,21µ cm The calculated resistivities are around three times of
the bulk resistivity of gold which is 2,44µ cm.
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C. Nanowires on Polyimide
Resistivity of gold nanowires on polyimide substrates were studied for 20µm and 10µm long
wires. The width of the nanowires ranged from 3µm down to 70nm. In Figure 36, SEM
pictures of gold nanowires on polyimide substrate can be seen. The image on the left shows
the nanowires with the contacts, the image on the right reveals the grain structure of
nanowires on polyimide substrate. In the left image it is also possible to observe the charging
effects during SEM.
Contacts
70nm width nanowire
Polyimide(Substrate)
Figure 36. SEM pictures for gold nanowires on polyimide.
SEM images are taken to extract the width and determine the average grain size. Average
grain sizes of the gold nanowires on polyimide substrates calculated to be 65nm. In Figure 37,
morphology of gold nanowires on polyimide substrate is shown.
Polyimide(Substrate)
Grains having an average
diameter of 65 nm
Au nanowire
Figure 37. SEM image of gold nanowires on polyimide substrate having an average grain size of 65nm.
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AFM pictures are taken to extract the thickness of the nanowires. In the AFM measurements
we realized that for 10µm long wires there was an unexpected doubling of the nanowires as
seen in Figure 38. The corresponding SEM image of the wire can be seen in figure Figure 39.
Doubled wire
Figure 38. Height image (left) and corresponding height profile (right) taken by AFM.
Doubled wire
Figure 39. SEM picture of the wire in figure 38, that doubling effect observed.
It is not obvious in the SEM image to observe the doubling effect; however it is clear from the
AFM image that there are actually two wires connected to each other.
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The doubling effect was not observed in other zones of the wafer. In Figure 40, there is an
AFM image from the zone right under the zone of the place that the doubling effect occurred.
From the AFM images, the thickness of the wire extracted to be around 37nm as in the other
substrates.
Figure 40. Height image (left) and corresponding height profile (right) taken by AFM.
I-V measurements were done under an applied electric bias of -5mV to 5mV. From the
gathered I-V data, resistance of the wires having different width extracted to determine to
resistivity. In Figure 41, I-V curve for the nanowires on polyimide having different width can
be seen. To obtain the resistivity only nanowires not showing the doubling effect were used.
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Figure 41. I-V Curve for gold nanowires on Polyimide Substrate
In Figure 42, the plot of resistance with respect to reverse of the area shows that resistance
increases as the cross sectional area decreases. The slope of this curve is calculated with the
procedure explained in the experimental part and resistivity of the nanowires extracted.
Figure 42. Resistance vs 1/Area plot for gold nanowires on polyimide
The resistivity of the gold nanowires are calculated to be 4,18µΩcm. The calculated
resistivity for 20µm long wires is 4,18µΩcm that is smaller than the other resistivities
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calculated for gold nanowires on other substrates. This difference could possibly be resulting
from the grain size will be discussed in the next chapter.
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D. Annealing Treatment
In order to investigate the grain size effect on the resistivity of the nanowires, gold nanowires
were deposited on silicon oxide substrate by stencil lithography. The gold nanowires from the
same deposition were annealed at three different temperatures 200C°, 250C° and 300C° with
rapid thermal annealing (RTA) method for ten minutes. A change in the morphology is
observed in all of the three treatments. Grain sizes are enhanced in the RTA treatment
significantly. SEM pictures of gold nanowires before and after annealing at three different
temperatures can be seen in Figure 43.
a
b
d
c
f
e
Figure 43. SEM pictures of gold nanowires a) before 200C° RTA b) same nanowire in (a) after 200C° RTA c) before 250C°
RTA d) same nanowire in (c) after 250C° RTA e) before 300C° RTA f) same nanowire in (e) after 300C° RTA. All the
nanowires were fabricated in the same deposition.
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An increase in the grain size observed after annealing at the three different temperatures.
Besides the change in grain size, it is also observed that the cross section trough the long axis
of the nanowire loses uniformity. The nanowire becomes rather like a series of grains of
different size, affecting the width and cross section of the wire. Only the wires it was possible
to extract the resistivity for the nanowires annealed at 250C°. The nanowires that were
annealed at 300C° could not stand the temperature and most of the narrow wires were broken
as seen in Figure 26. For the nanowires annealed at 200C°, I-V measurements show opencircuit behavior although they seem to be connected in SEM images. Therefore it was not
possible to make a comparison for the resistivity of nanowires which are annealed at 200C°
and 300C°.
Resistivities of gold nanowires before and after annealing are calculated with the same
approach as in the characterization part. SEM and AFM images are taken to extract the
dimensions. AFM images before and after annealing at 250C° can be seen in Figure 44.
a.
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b.
Figure 44. a) AFM image for a nanowire before 250C° RTA. Height image (left) Corresponding profile (right) b) AFM
image for a nanowire after 250C° RTA. Height image (left) Corresponding profile (right)
It is observed from the AFM images that annealing did not changed the thickness of the
nanowires critically. Before and after annealing the thickness was around 37 nm.
I-V measurements are done for the wires annealed at 250C˚ in order to obtain the resistance.
As can be seen in Figure 45, obtained results show an ohmic behavior both before and after
annealing.
a.
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b.
Figure 45. a) I-V curve for gold nanowires before RTA at 250C° b) I-V curve for gold nanowires after RTA at 250C°
In order to extract the resistivity of gold nanowires before and after annealing treatment, the
same procedure explained in the characterization part was done. Derivative of resistances are
taken with respect to 1/Area to extract the resistivity. The slope of the resistance vs 1/Area
curves in Figure 46, equals to resistivity multiplied by the length of the nanowires.
Figure 46. Resistance vs 1/Area curve for after and before annealing
It is observed from Figure 46 that the slope of the curve decreases after annealing. This
behavior indicates that the resistivity of the nanowires decreases after annealing. Calculations
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revealed that resistivity of gold nanowires was 8,92µ cm before annealing. After annealing
the resistivity of the nanowires found to be 6,61µ cm. The decrease in the resistivity could
possibly be related to the enhancement of the grain size as seen in the SEM pictures in Figure
43. However, the change in the cross section are of the nanowire can also induce a change in
the resistance through the change in width in some sections of the wires and also changes in
the resistivity due to size effects. This effect will be fully discussed in the next chapter.
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CHAPTER 4. DISCUSSION
A. Grain size and resistivity relation of gold nanowires in different polymer
substrates
As stated in the results chapter, different resistivities were measured for gold nanowires on
different polymer substrates. This difference could be originated from the different grain sizes
on different substrates. Resistivities calculated for gold nanowires and corresponding average
grain sizes can be seen in Table 3.
Substrate
Resistivity (µΩcm)
Average Grain Size in Diameter (nm)
Parylene
9,54
21±1
SU-8
8,21
32±2
Polyimide
4,18
65±8
Table 3. Resistivity of gold nanowires on different substrates and corresponding average grain sizes
As Carl V. Thomspson stated in an article from 1990, it is known that grain growth can
profoundly affect the mechanical, electrical and chemical properties of thin films (17). In our
work, we observed that nanowires of the same material but with a different grain size show
different electrical properties, namely the electrical resistivity of nanowires.
In his work, Thompson argues that the real thin films are not two-dimensional because they
have surfaces. Since the energy of the surface of a crystal depends on its orientation,
anisotropy of the surface free energy plays a very important role in grain growth in thin films.
(17) A theory for the grain growth in thin films that includes the effect of surface energy
anisotropy using both macroscopic energetic arguments and coarsening theory has been
developed giving the rate of growth of an individual grain of radius r on a substrate is as
follows:
: The radius of the secondary grain
The average grain radius for the normal grains
h: The film thickness,
: The grain boundary energy
: Surface free energy of the grain being considered,
51
: The average surface energy
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:The energy of the interface between the grain and the substrate,
: The average energy
between the grain and the substrate
As can be seen from the equation, the rate of growth of a grain in a thin film is a function
dependent on the surface energy of the grain and the energy of the interface between the grain
and the substrate as illustrated in Figure 47. The change in the grain size of the gold nanowires
on different substrates, as shown in Figure 48 could be due to the different interface energies
between the grain and the substrate.
Figure 47. A film on a substrate showing surface energy and the interface energy of a grain with the substrate.
Au nanowire
SU-8 (Substrate)
Grains having average
diamater of 32nm
Grains having average
diamater of 21nm
Au nanowire
Parylene (Substrate)
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Polyimide(Substrate)
Grains having an average
diameter of 65 nm
Au nanowire
Figure 48. SEM images of different grain sizes of gold nanowires on different substrates (parylene, su8 and polyimide) as
a result of the different interface energy between the grains and the substrate.
Having different grain sizes in gold nanowires resulted in different resistivities on different
substrates as shown in Table 3. This situation is probably explained by the grain boundary
scattering theory of Mayadas. As explained in chapter 1.C, electron scattering at the grain
boundaries contributes to the resistivity of the thin films. If the grain sizes of the gold
nanowires are higher this means the density of the grain boundaries are smaller, therefore a
relatively less number of scattering occurs at the grain boundaries resulting in a smaller
resistivity. The only way in which the electrical resistivity can remain unaffected by grain size
would be if the reflection of electron at grain boundaries would be zero (R=0), which has not
been reported in previous literature reports on Au nanowires. Grain sizes vs. resistivity graph
for polymer substrates plotted in Figure 49.
Figure 49. Average Grain size vs Resistivity graph for gold nanowires on polymer substrates respectively from highest
grain size: Polyimide, Su-8, Parylene
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B. Grain size and resistivity relation of gold nanowires on silicon oxide substrate
Our measurements show that before annealing the average grain size for the gold nanowires
was 26nm. Average grain size after annealing found to be 56 nm. After annealing the
nanowires at 250C°, a significant increase in the grain size as seen in the SEM pictures in
Figure 50. The electrical measurements also show a decrease in the resistivity of nanowires
after annealing. This is probably due to increase in the grain size and decrease in grain
boundary density leading to less scattering from the grain boundaries. The resistivity of the
nanowires decreased from 8,92µ cm to 6,61µ cm and the average grain size of the wires
increased from 26nm to 56nm. Along with the increase in the grain size after annealing at
250C˚, a decrease in the wire width observed, however, the decrease was smaller than %5 in
most of the cases.
Grains having
average diameter of
56nm
Grains having
average diameter of
26nm
Figure 50. SEM image for nanowires before(left) and after(right) annealing at 250C°
Figure 51 summarizes the results of this project, showing the resistivity for different grain sizes
obtained on different substrates and from annealing process.
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Figure 51. Average Grain Size with respect to resistivity of gold nanowires on different substrates. Respectively from
highest resistivity: Gold nanowires on Parylene, Silicon oxide (before RTA), SU-8, Silicon oxide (after RTA) and Polyimide.
The plot in Figure 51 reveals the contribution of grain boundary scattering on resistivity. The
resistivity decreases as a result of the increase in the grain size from 9,54µ cm on a parylene
substrate down to 4,18µ cm on a polyimide substrate. This change in the resistivity of
nanowires are enabled by changing the morphology of the nanowires using different polymer
substrates or annealing nanowires. Resistivity of gold in bulk is 2,44 µ cm. In nanowires it is
found to be higher than its bulk value as a result of the emerging size effects, grain boundary
scattering and surface scattering. By having different Au nanowires of similar dimensions but
having different grain size, we show the important role of grain scattering in the resistivity of
metallic nanowires and allows us to separate the grain size effect from surface scattering on
the electrical resistivity.
As shown in previous reports (5), we also show that by changing the grain sizes of the
nanowires, grain boundary density in the nanowires changes modifying as well the resistivity
of the nanowires.
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CHAPTER 5. CONCLUSION
We have demonstrated that stencil lithography is a reliable technique for the fabrication of
metallic nanowires on polymer and conventional silicon oxide substrates. This offers an
alternative route for nanopatterning without resist-based processing.
By using different substrates and annealing methods, we have fabricated Au nanowires having
different grain sizes. In the case of polymer substrates, the extracted resistivities are
9,54µΩcm, 8,21µΩcm, and 4,18µΩcm respectively for parylene, SU-8 and polyimide. The
different grain sizes 21nm, 32nm, 65nm respectively Au nanowires on parylene, SU-8 and
polyimide. In the case of annealing method on silicon oxide, the resistivity decreased from
8,92µΩcm to 6,61µΩcm with a corresponding increase in the grain size of the nanowires
from 26nm to 56nm.
Collected data and results indicate that there is a strong relation between the resistivity and the
grain size of the nanowires. As the grain size increases, the resistivity decreases. The increase
in the grain sizes results in a smaller grain boundary density and less grain scattering.
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CHAPTER 6. OUTLOOK
The next step in the analysis of grain scattering in resistivity would be a quantitative analysis
using Mayadas theory. This would also involve the estimation of the reflectivity and
specularity parameters R and p from grain and surface scattering respectively.
In order to further investigate the effect of using different polymer substrates on morphology
of the nanowires, the nanowires can be deposited at the same time to have the same deposition
conditions and only vary the substrate. This would give more data concerning the relation
between grain size and substrate. Also to further investigate the effect of enhancing grain
sizes on resistivity, annealing treatment can be applied to the polymer substrates; however
polymer substrates impose restriction on the highest temperatures that can be applied.
Moreover, in order to discern the effects of grain boundary scattering and the surface
scattering, I-V measurements can be done on a single or few gold grains with using
cantilevers for 4-probe measurements like the ones proposed by Keller et al, the proper
conductive AFM tips. (18) A gold nanodot having a diameter of 100nm can be annealed to get
a single grain then AFM tips having a radius smaller than 10nm as seen Figure 52, can be
aligned with a nanometric precision to do the I-V measurements and extract the resistivity.
Since in this case there will not be any contribution of grain boundary scattering to the
resistivity of the nanowires, only the effect of surface scattering can be examined and
compared to the bulk resistivity.
Figure 52. AFM tips having a radius smaller than 10nm can be used as probes in a proper setup to analyze the effect of
surface scattering on a single gold grain.
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ACKNOWLEDGEMENT
I would very much like to thank Oscar Vazquez Mena for his endless helpful and motivating
attitude to me during the project. I learned so much from his great experience and knowledge
in micro fabrication as well as from his personality.
I would like to thank Dr. Scott Harada for providing access to the clean room in Ceramics
Laboratory (LC), helping me with the annealing treatment and for his beneficial discussions.
I would like to thank staff of CMI for giving formations for the equipment in the clean room. I
thank Guy Francois Clerc for LAB600 e-beam evaporator formation, Kevin Lister for SEM
formation, Boris Lunardi and George Andre Racine for MA6 Mask Aligner formation, Jean
Baptiste Bureau for Manual Probe Station formation.
I would also like to thank Professor Juergen Brugger and all the members of LMIS1 for their
productive discussions. In particular I would like to thank to Cristina Martin for the
preparation of SU-8 wafers and Guillermo Villanueva for his help in clean room.
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