Vol. 34, No. 3
Journal of Semiconductors
March 2013
A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO
in 130 nm CMOS technology
He Siyuan(何思远)1; Ž , Zhang Changhong(张常红)1 , Tao Liang(陶亮)1 , Zhang Weifeng(张伟锋)1 ,
Zeng Longyue(曾隆月)1 , Lü Wei(吕伟)1 , and Wu Haijun(武海军)1; 2
1 Guangzhou
2 School
Runxin Information Technology Co. Ltd, Guangzhou 510663, China
of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China
Abstract: A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter
is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature
passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order
Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and
analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity.
An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 m CMOS
process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), –11 dBm
IIP3, and > C65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector
magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip
supply.
Key words: RF CMOS; passive mixer; 25% duty-cycle; saw-less; noise figure; Chebyshev filter; LTE
DOI: 10.1088/1674-4926/34/3/035002
EEACC: 2570
1. Introduction
LTE (3GPP long-term evolution) is the latest standard to
provide mobile broadband service for fourth-generation wireless communications. LTE supports both frequency-division
duplex (FDD) and time-division duplex (TDD), as well as a
wide range of system bandwidths in order to operate in a large
number of different frequency bands allocated from 0.7 to
2.7 GHz. In addition, the LTE standard supports a large number
of channel bandwidths that vary from 1.4 to 20 MHzŒ1 . Therefore, a receiver designed to cover all-band LTE application is
tested in software-defined radio (SDR) and/or multi-standard
multi-band from the point of view of the high requirements in
out-of-band interference rejection.
In an LTE FDD radio, due to the simultaneous operation
of the receiver and transmitter, and the limited isolation of the
duplexer, the receiver must tolerate its own transmitter leakage
while receiving extremely weak input signals. For that reason,
a SAW filter is typically placed in the RX path to suppress
out-of-band TX leakage blocker signals that reduce sensitivity, and prior to that an external LNA is needed to overcome
the passband loss of the filter. Although very challenging, the
increasing interest in lower cost and smaller form-factor solutions mandates the elimination of bulky and expensive off-chip
components, which poses stringent IIP2 and cross-modulation
IIP3 requirements. Architectural and system improvement is
one way to reduce cost. Due to their simplicity and better
integration, direct conversion receivers (DCRs) have gained
wide attention for modern communication standard receivers
as compared to the heterodyne architectureŒ2 .
In this paper, a saw-less LTE direct convert receiver with
a 25% duty-cycle LO fabricated in a standard digital 0.13-m
CMOS process is presented. High out-of-band linearity performance is achieved by reducing the RF circuitry and filtering the out-of-band blockers after direct conversion. The 25%
duty-cycle LO results in higher signal conversion efficiency
and lower noise sensitivity relative to a 50% duty-cycle implementation. Wide dynamic gain range is achieved in both the
RF and analog parts.
2. Architecture
Figure 1 shows the proposed receiver architecture without
the interstage SAW filter. All the RF and signal paths are implemented in a fully differential style in order to enhance commonmode noise rejection. The variable gain low noise amplifier
acts as a transconductance amplifier (TCA) stage feeding the
current to the I/Q down-converters. The down-converters are
comprised of a current-commutating mixer in cascade with the
trans-impedance amplifier (TIA). The LO path consists of a
VCO locked at 2LO frequency. The 25% divider halves the
VCO output frequency signal and generates four 25% dutycycle square wave signals, which drive the I/Q mixers through
the LO buffers. After frequency down conversion in the RF
front-end, the received signals are processed by programmable
gain amplifiers (PGA) and low pass filters (LPF). 4 stages of
RC active filters and 4 stages of PGAs alternately in chains are
used to achieve a small ripple in band, improved linearity for
out-of-band interference, and wide dynamic gain range. This
results in about 60 dB in 1 dB steps. Together with the 36 dB
* Project supported by the National High Technology R&D Program of China (No. 2009AA01Z260) and the Guangdong & Hong Kong
Cooperation Key Area 2010 Program (No. 2010A090601001).
† Corresponding author. Email: [email protected]
Received 21 August 2012, revised manuscript received 10 October 2012
© 2013 Chinese Institute of Electronics
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He Siyuan et al.
Fig. 1. Architecture of Rx.
Fig. 2. Simplified schematic of the transconductance amplifier (TCA)
with large gain control range.
gain range in the TCA, the receiver chain achieves 96 dB dynamic gain range in 1 dB steps in total.
Fig. 3. Schematic of a passive mixer with 25% LO.
3. Design of key blocks
This section describes each building block of the receiver:
TCA, mixer, and LPF&PGAs. All circuits described here operate under 1.2-V power from an LDO supply on chip.
3.1. Variable gain TCA
The simplified schematic of the TCA used in the receiver is
shown in Fig. 2. It consists of a differential low noise common
source NMOS gm -stage with source degeneration to introduce
a real part to the input impedance without adding significant
noise. A differential input to the TCA is used to minimize RF,
LO and noise coupling and to achieve high impedance with optimal noise matching for more passive gain. In order to implement fine gain control, the transconductor is divided into five
binary-weighted sections (16 : 8 : 4 : 2 : 1 : 1) with digitallycontrolled current steering via cascoded devices. By digitally
steering the current in the cascoded devices to the load or to
the dummy bus, 36 dB in total in 6 dB steps gain control range
can be achieved, while keeping input impedance unaffected.
3.2. Passive mixer with a 25% duty-cycle LO and a TIA
A passive current commuting mixer is implemented in order to tackle a stringent 1/f noise problem and a high linearity
requirement. As shown in Fig. 3, the RF signal through a low
noise TCA feeds into an I/Q mixer, while an AC coupling capacitor prevents DC-current flow through mixing switches to
reduce low 1/f noise, and it can also help to suppress the 2ndorder distortion from RF part entering into the baseband region;
thus improving IIP2 performance.
Without an RF SAW filter, the mixer is required to work
under large signal interference. It is necessary for frequency
down converted signal amplification with out-of-band rejection. The TIA, constructed from an opamp and feedback resistors and capacitors, terminates the switching pair in low
impedance driving to high linearity TIA operation. The IF signals achieve high gain after the low-pass filter formed by feedback resistors and capacitors. The opamp for the TIA is a conventional two-stage amplifier with high output swing.
The full RF current passes through each double-balanced
mixer separately, as opposed to being split between the I and
Q mixers as in conventional direct conversion receivers with
50% duty-cycle LO signal. In a 50% duty-cycle LO system, at
any given time, there exists a low impedance path between the
in-phase and quadrature-phase TIAs through the mixer which
results in NF deterioration. This problem can be addressed by
adopting a 25% duty-cycle LO, where I and Q mixer switches
are never open simultaneouslyŒ3; 4 . The 25% duty-cycle LO
also provides 3 dB higher gain and consequently 3 dB lower
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He Siyuan et al.
Fig. 4. Analog signal processing circuitry. (a) Second-order RC active low pass filter. (b) First-order RC active low pass filter. (c) PGA cell with
DC-offset-cancellation circuitry.
NF for a passive mixer. Let the transconductance of the LNA
be Gm . In a receiver with a double-balanced mixer driven by a
50% duty-cycle LO, the LNA output current divides between
the two down-converters. Hence, the voltage gain of the receiver can be expressed as,
G50%LO D Gm D
1 4
RTIA
2 2
Gm RTIA ;
(1)
where 4/ is the gain of a double balanced mixer and RTIA is
the TIA feedback resistance. The Fourier series expansion of
a 25% duty-cycle switching waveform with frequency !LO is
given byŒ7 ,
p 2 2
1
f25%LO .t / D
sin !LO t
sin 3!LO t
3
1
1
sin 5!LO t C sin 7!LO t C : (2)
5
7
Hence, a double balanced
mixer driven by a 25% dutyp
cycle LO has a gain of 2 2=. As only one down converter is
active at a time, the entire LNA output current feeds it. Thus
p
2 2
G25%LO D Gm RTIA
p
2 2
Gm RTIA :
(3)
D
As compared with Eq. (1), a 3 dB improvement in gain by
using 25% duty-cycle will be achieved.
The complex IIP2 of the receiver is one of the most critical
specifications to meet for SAW-less operation. To compensate
for the mismatch between the quadrature switches, an on chip
IIP2 calibration technique is realized. The IIP2 calibration is
done with a closed loop routine by injecting calibration signals
at the receiver input, setting the DAC offset at the mixer gates
based on an algorithm which is implemented in firmware, detecting the IMD2 components in the baseband, and repeating
to minimize the second-order distortion component. With IIP2
calibration, the IMD2 products arising from the modulated TX
blocker are reduced to an acceptable amount, and then the interstage SAW filter can be eliminated in the LTE receiverŒ8 .
3.3. LPF & PGAs
In order to support 1.4–20 MHz channel bandwidth, high
adjacent-channel rejection, wide dynamic ranges, low ripple in
band and other stringent specifications which LTE demand, 4
stages of LPF and PGAs place alternatively in chains to process down-converted signal which are shown in Fig. 4. Three
stages of second-order RC active filters based on Tow-Thomas
biquadŒ10 topology and one stage of a first-order RC active
filter is adopted as a 7th order Chebyshev filter.
By varying the RC value and especially the ratio from
Eq. (7), the filter characteristic can be freely achieved. The first,
the third and the fourth stage filters share the same configurations except for different Q settings. Considering the trade-offs
between NF and linearity, a moderate-Q filter is placed at the
front to reject the following blocks’ noise considerations, while
a high-Q filter is put at the end to get high linearity. Of course,
in order to achieve a high GBW of opamp, a large current has
to be consumed.
The RC tune circuitry can keep the RC time-constant defined characteristic unchanged regardless of process variation.
All 4 stages of PGAs share the same configuration except
for the gain range. 60 dB gain range in 1 dB steps is achieved. In
each cell, DC offset cancellation circuitry is also employed to
prevent large dc signal blocking from the previous LPF output.
The biquad topology filter transfer functions are as follows:
035002-3
TLPF .s/ D
H !02
;
!0
s2 C
s C !02
Q
H D
!0 D
C
R4
;
R1
p
1
;
R3 R4
(4)
(5)
(6)
J. Semicond. 2013, 34(3)
He Siyuan et al.
Fig. 5. Die microphotograph of the receiver as part of LTE transceiver.
Fig. 7. Measured Rx chain DSB NF and voltage gain versus LO frequency.
Fig. 6. Measured Rx chain voltage gain versus control word.
QD p
R2
:
R3 R4
(7)
Fig. 8. Measured double side band NF versus IF at 2.4 GHz LO.
4. Measurement results
The receiver is fabricated in a 0.13 m 1p6m CMOS process as a part of the LTE transceiver. Figure 5 shows the die
microphotograph of receiver with a frequency synthesizer, including the PADs and ESD protection. The area is about 3.2
mm by 1.0 mm. Two inductors are used, one in LNA and another in VCO. As shown in Fig. 6, the receiver chain voltage
gain versus control word is plotted and 96 dB in 1 dB steps
gain dynamic range is achieved. Maximum voltage gain and
the corresponding DSB NF from the antenna port with LO frequency are illustrated in Fig. 7, where the maximum gain is
about 107 dB. The DSB noise figure from the antenna port is
from 3.8 to 4.3 dB, considering external balun and cable loss,
1.1 dB lower about 2.7 to 3.2 dB from PAD port. As shown in
Fig. 8, the flicker noise corner is lower than 20 kHzŒ9 .
The input reflection coefficient S11 is better than –12 dB.
LO leakage to the RX input port is less than –80 dBm.
Two tone test out-of-band IIP3 versus with Vgain is presented in Fig. 9. When the receiver is set to maximum gain,
IIP3 > –11 dBm.
IIP2 Measurement is conducted in LTE band 7 FDD mode,
the Tx leakage to Rx is a strong interference power at the offset
frequency of 120 MHz. Figure 10 shows that the calibrated IIP2
> C65 dBm when interference power D 38 dBm.
Fig. 9. Measured out-of-band IIP3 versus gain.
The final output IF frequency response at maximum bandwidth (20 MHz) setting is shown in Figs. 11–13. Over 60 dB
stop band rejection, less than 1.3 dB ripple in band and a less
than 2% EVM is achieved.
The TCA consumed 8 mA, the LO divider and buffer consumed 15 mA, the TIA consumed 10 mA, while the PGA and
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He Siyuan et al.
Fig. 13. EVM versus input power at 2.65 GHz.
Fig. 10. Measured IIP2 (un)calibrate versus interference power.
Table 1. Performance comparison with recent publications.
Parameter
This work
Ref. [5]
Ref. [6]
Process
0.13 m
0.18 m
0.13 m
CMOS
CMOS
CMOS
Frequency (GHz)
2.3–2.7
2.11–2.17
1.93–1.99
Voltage gain (dB)
105
102
50
Gain range (dB)
96
84
89
DSB NF (dB)
2.7
2.8
8
IIP3 (dBm)
–11
–2
–6
IIP2 (dBm)
C65
65
C30
EVM (%)
2
5
8
Supply voltage (V)
1.2
2.9–5
2.7–3
Current supply (mA)
89
35
35
5. Conclusion
Fig. 11. Measured receiver output frequency response at max bw setting (20 MHz).
A direct conversion saw-less LTE receiver in 130 nm
CMOS technology was presented. A low noise transconductance amplifier, together with PGAs, provides a large
control range, meeting the demands of modern communication systems. A current commutating passive mixer with a
25% duty-cycle LO has significant advantages in noise, intermodulation distortion and large signal handling capability and
is a key enabler for saw-less operation. 7th order Chebyshev
LPF suppresses the interferer out-of-band, and improves ripple
in band performance and is an important factor for large bandwidth requirements. The whole receiver, as measured, achieves
2.7 dB DSB NF (from pad port), 96 dB dynamic gain range
with 107 dB maximum gain, better than –11 dBm IIP3 and +65
dBm IIP2, 1.3 dB ripple in band at maximum bandwidth setting (20 MHz), less than 2% EVM from 1.2 V LDO on chip
supply. The total receiver consumes 89 mA.
References
Fig. 12. Measured receiver output frequency response in band at max
bw. setting (20 MHz).
filter (total I and Q) consumed 16 mA and 40 mA, respectively.
All the above blocks draw from a 1.2 V LDO on chip supply.
The key specifications are enumerated and compared with prior
published results in Table 1.
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