Ideal Tx-Line Reflection
吳瑞北
Rm. 340, Department of Electrical Engineering
E-mail: [email protected]
google: rbwu
S. H. Hall et al., High-Speed Digital Design, Chap.3
N. N. Rao, Elements of Engineering Electromagnetics, Chap. 6
1
What will you learn?
• How to solve circuits with ideal lossless tx-line?
• Is there easier “analytic” equ. circuit model.
• How to solve “analytically” tx-line circuits with R,
L, and C loading/discontinuities?
• How does reflection come from? How to deal with
multiple reflection phenomenon?
• How to measure? Operation principle of TDR.
• How to extract tx-line parameters & discontinuities
from TDR measurement?
• How to mitigate reflection?
R. B. Wu
2
Contents
•
•
•
•
•
Analytic Tx-Line Analysis
Reflections from Resistive Loads
Reflection from Reactive Loads
Time Domain Reflectometry
Termination Designs
R. B. Wu
3
Analytic Tx-Line Analysis
4
Distributed Element
Tx-line is also called
a distributed element
vS(t)
vA(t)
iA(t)
i(z,t)
+
v(z,t)
vB(t)
iB(t)
_
i(z,t)
• vs. lumped elements ZS, ZL.
• Note the reference of V(z,t).
GROUND
• Where is the ground of tx-line?
• I(z,t) must accompany the return-path current.
• How to interpret a negative I(z,t)?
• How to solve circuits with a distributed circuit element?
R. B. Wu
5
Eq. Circuit Model for SPICE Simulation
Rule of Thumb:

1. Decide # of segments  10
tr  v p

2. Choose R, L, C, G segment  R, L, C, G *
#
Note: TDsegment
t
 r
10
#

max freq.
10
R. B. Wu
Equivalent Circuit Seen from Both Ends



V ( z, t )  V  t  vzp  V  t  vzp
I ( z, t ) 
VA (t )  V (0, t )  V t   V t 




     V (t )  V (, t )  V
1 
V t  vzp  V  t  vzp
Z0

B
I B (t )  I (, t ) 
1 
I A (t )  I (0, t ) 
V t   V  t 
Z0

t  T   V  t  T 


1 
V t  T   V  t  T 
Z0
VB (t )  Z 0 I B (t )
VA (t )  Z 0 I A (t )

 2V  ( z  , t )

 2V  ( z  0, t  T )
 2V ( z  0, t )
 2V ( z  , t  T )
V   VB  V  ;
V   VA  V 
R. B.
Wu
Ref.: F. H. Branin, Jr., “Transient analysis of lossless transmission lines,” Proc.
IEEE,
vol. 55,7 pp.
2012-2013, Nov. 1967.
Circuit Modeling
A
B
Z0 ; T
VA
Z0
Z0
EA
VB
EB
Equivalent circuit
 Time delay
 Impedance
* voltage controlled voltage source
E A ( t )  2v B ( t  T )  E B ( t  T )
Rem: Only 4 lumped
elements, even for very
long tx-line.
E B ( t )  2v A ( t  T )  E A ( t  T )
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8
Time Marching
At source end
Zs
t
T
2T
3T
Z0
Z0
VA (t)
Vs (t)
VS (t ) VA(t)
x
x
x
x
x
x
x
x
x
At load end
x
x
x
x
x
x
x
x
x
EA (t)
E A(t)
0
0
0
0
0
0
x
x
x
V  ( 0,t)
x
x
x
x
x
x
x
x
x
VB (t)
EB (t)
V  ( ,t)
0
0
0
x
x
x
x
x
x
EB (t)
0
0
0
x
x
x
x
x
x
ZL
VB (t)
0
0
0
x
x
x
x
x
x
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9
Reflections from Resistive Loads
10
Time-Domain Sol. w/o Simulator
1. Determine launch voltage & final “DC” or “t =0”
voltage
2. Calculate load reflection coefficient and voltage
delivered to the load
3. Calculate source reflection coefficient and
resultant source voltage
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11
Determine Launch Voltage
TD
I+
Rg
Vs
B
Zo
Vs
0
V
Rs A
Rt
+
V0
(initial voltage)
t=0, V=Vi
Z=0
I+
Rg
Z0
V0
V+
Vi = VS
Z0
Z0 + RS
Vf = VS
Rt
Rt + RS
Z=0
Step 1: determine launch voltage
– Simply a voltage divider!
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12
Voltage Delivered to Load
TD
Vs
Rs A
Vs
0
B
Zo
VB
Z0
Rt
RL
2Ei
(initial voltage)
t=0, V=Vi
rB  Rt  Zo
Rt  Zo
(signal is reflected) for t   d
RL
t=TD, V=Vi +rB (Vi )

Vreflected = rB (Vincident)
VB = Vincident + Vreflected
VB  2V
Z 0  RL
V   VB  V 
I   V  Z 0
Step 2: determine VB at t = TD
−
−
−
−
Tx-line delays the arrival of launched voltage until t = TD.
VB for 0 < t < TD is at quiescent voltage (0 in this case)
Voltage wavefront will be reflected at tx-line end
R. B. Wu
VB = Vincident + Vreflected at t = TD
13
;
Voltage Reflected back to Source
Vs
0
Rs A
Vs
rA
B
Zo
rB
Rt
TD
IA
(initial voltage)
VA
Z0
t=0, V=Vi
Rg
2Er
V0
Z=0
t=2TD,
V=Vi + rB (Vi) + rAr B )(Vi )
(signal is reflected)
t=TD, V=Vi + rB (Vi )
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14
Voltage Reflected Back to Source
rA
 Zo
Rs

Rs  Zo
Vreflected = rA (Vincident)
VA = Vlaunch + Vincident + Vreflected
Step 3: Determine VA at t = 2TD
−
−
−
−
Tx-line delays the arrival of voltage reflected from load
until t = 2TD.
VA at time 0 < t < 2TD is at launch voltage
Voltage wavefront will be reflected at source
VA = Vlaunch + Vincident + Vreflected at t = 2TD
In steady state, sol. converges to VB = VS [Rt/(Rt + Rs)]
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Lattice (Bounce) Diagram
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16
1st Reflection vs. 1st Incident Switching
Open-circuited line  Γ R  1 (VB  2V  )
Termination by Z 0  Γ R  0 (VB  V  )
• Applications
First reflection switching
First incident switching
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17
Over Driven Tx-Line (Under Damped)
V(source)
2v
V(load)
Zs
TD = 250 ps
Vs
rsource  0. 3333
Time V(source)
0
500 ps 1.33v
Assume Zs=25 ohms
Zo =50ohms
Vs=0-2 volts
Vinitial Vs
rload 1
1.33v
 50 
Zo
 (2) 
÷ 1.3333
Zs  Zo
 25 50 


rsource  Zs Zo  25 50  0.33333
V(load)
Zs  Zo
25  50

 50
rload  Zl Zo 
1
0v
Zl  Zo
  50
1.33v
Response from lattice diagram
1000 ps
2.66v
-0.443v
3
2.5
1500 ps 2.22v
-0.443v
2000 ps
Volts
0
Zo
1.77v
2
1.5
Source
1
0.5
0.148v
Load
0
0
2500 ps 1.92
0.148v
250
500
750 1000 1250 1500 1750 2000 2250
Time, ps
2.07
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18
Under Driven Tx-Line (Over Damped)
2v
0
Vs
Zo
V(source)
Zs
TD = 250 ps
r source  0 . 2
r load  1
V(load)
Time V(source)
0
Assume Zs=75 ohms
Zo=50ohms
Vs=0-2 volts
V(load)
0.8v
Vinitial  Vs
r source 
0v
500 ps
rload 
0.8v
0.8v
1000 ps
Zo
 50 
 (2)
  0.8
Zs  Zo
 75  50 
Zs  Zo 75  50

 0.2
Zs  Zo 75  50
Zl  Zo   50

1
Zl  Zo   50
1.6v
Response fr om lattice diagram
0.16v
2.5
1500 ps 1.76v
2
2000 ps
2500 ps
1.92v
0.032v
V olt s
0.16v
1.5
Sour ce
1
Load
0.5
0
0
2 50
500
750
Tim e , ps
1000
1250
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Effects of Rise Time – overdriven case
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Effects of Rise Time – underdriven case
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21
Reflection and Transmission
Incident
r
1r
Transmitted
Reflected
Reflection Coefficient
Zt  Z0
r
Zt  Z0
Transmission Coefficient
 =1+r    1 
2Zt

Zt  Z0
Zt  Z0
Zt  Z0
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22
Multiple line impedance
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23
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24
Multi Receivers Topology
l2
Rs=Zs
l1
Z0
Receiver 1
Z 0  Rs  50
Z0
l1  l3  250 ps;
l3 > l2
l2  125 ps;
Receiver 2
0-2V
Z0
2 
Z0 2  Z0
  13
Z0 2  Z0
T2  1   2 
2
3
 3   13 ; T3 
2
3
 4  1; 5  1
Eig 3-35
v 
4
3
v 
8
9
v 
52
27
vA 
4
3
vB 
20
9
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25
Effects of Non-symmetry
l2
Rs=Zs
l1
Z0
Receiver 1
Z0
l3 > l2
Receiver 2
0-2V
Z0
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26
Ringing Noise on Address Lines of DDR
v p  3 108 / 2.5; Rs  3.27 104   s  m1
tanD  0.02; TD3  L3 / v p  100ps
Tt  Lt / v p  214ps; t  l / v p
Short End
L1=(Lt-Δl)/2
Z0
L3
0-1.5V
Tr=200ps Z0, vp, Rs, tanD
L2=(Lt+Δl)/2
Long End
Ringing Effect
2
2
1.5
1.5
l/Lt=0
1
Voltage(V)
Voltage(V)
Ringing Effect
l/Lt=0.2, Short End
l/Lt=0.2, Long End
0.5
l/Lt=0.6, Short End
0.5
l/Lt=0.8, Short End
l/Lt=0.6, Long End
l/Lt=0.8, Long End
l/Lt=0.4, Short End
0
-0.5
0
1
0
l/Lt=0.4, Long End
0.5
1
1.5
time(ns)
2
2.5
3
-0.5
0
0.5
1
R.
1.5B. Wu
2
time(ns)
27
2.5
3
RLC Resonance Model of Ringing Noise
•
The total response can be divided into the balanced response and the ringing
noise response.
The ringing noise response can be fitted as a RLC resonance response
•
Tt
 l 
sin 2 

b
 2 Lt    v

0 p
2
Tt
 l 
sin 

 2 Lt 
A
 l 
sin 2 
   0 Lt
 2 Lt 
          j   
Step Response, l/Lt=0.12
2
0   0   0.884m1
1.5
v0
Z0
Z0, L3
Z0/2
0-1.5V
Tr=200ps
L
vstep(t-TD)
0-1.5V
Tr=200ps
TD=L3/vp
v0
veq
vn
Avn
veq  v0  vn
Equivalent Balanced Ringing noise
response
response response
Voltage(V)
0 

Balanced
Precise, short end
Model, short end
Precise, long end
Model, long end
Ringing
1
0.5
0
-0.5
0
0.5
1
1.5
time(ns)
2
2.5
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28
3
Eye Height – Bit rate Influence
• Worst case occurs at UI/Tt is odd.
UI/Tt=4, Δl/Lt=0.12
Eye Height/Vh
7
6
0.6
0.6
0.6
0.6
1
0
00.4.2
0.4
0.2
0.4
0.6
0
0.1
0.6
0.6
2
0.4 0.2
0
0.4
0
UI/Tt
0.6
4
3
0%
0.8
0.6
5
UI/Tt=3, Δl/Lt=0.12
0.8
0.8
65%
0.8
0.4
0.2
0.2
0.3
l/Lt
0.4
0 0.2
0.4
0.6
0.6
0.5
R. B. Wu
0.6
29
Eye Height – Leg Difference Influence
Eye Height/Vh
• Worst case occurs
at where the max 7
of A occurs.
0.8
l 2

 0 Lt  0.12
L 
0.6
0.6
0.6
4
0.6
0.6
1
UI/Tt=3, Δl/Lt=0.12 0
00.4.2
0.4
0.2
0.4
0.6
0
0.1
0.6
0.6
2
0.4 0.2
0
0.4
0
UI/Tt
0.8
0.6
5
3
0%
0.8
0.8
6
0.4
0.2
0.2
0.3
l/Lt
0.4
0 0.2
0.4
0.6
0.5
Ref: K.-Y. Yang, et al., “Modeling and
fast eye- diagram estimation of ringing
effects on branch line structures,” IEEE
T-CPMT, Apr. 2014.
0.6
0.6
UI/Tt=3, Δl/Lt=0.6
62%
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30
Effect of a Long Stub
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31
Reflections from Reactive Loads
32
Inductive Termination
t=0
for t  T  l u
R0
LL 
V0 / 2
LL
R0
diL
 R0  iL  2v   V0
dt
 iL (t )  VR0 1  e  ( t T )R0 LL
0

 ( t T )R0 LL
vL (t )  v(l , t )  V0e

V0
z=0
z=l
z = z1
iL(t)

v  (l , t )  v(l , t )  V0 2
v  (0, t )  V0 2
R0
for t  0
v(l,t)
v(l,t)
2v+(0, t-T)
v(l,t)
for 2T  t  T
LL
z1  l  u   t  T 
V0
V0
V0 / 2
T
LL
R0
t
z = z1
z=l
z
R. B. Wu
Capacitive Termination
t=0
for t  T
v  (l , t )  v(l , t )  V0 2
R0
R0
CL
z=0
V0
z=l
z = z1
z1  l  u  t1  T 
v(z,t1)
V0
iL(t)
V0 / 2
v  (0, t )  V0 2
for t  0
R0
v(l,t)
2v+(0, t-T)
v(l,t)
V0
CL
v(z1,t)
z = z1
z=l
z
V0
V0 / 2
0
T
t
T
t1
t
R. B. Wu
Time Domain Reflectometry
36
Time-Domain Reflectometry
• Key advantages over frequency measurement
– Ability to extract electrical data relevant to digital systems
– Can extract impedance, velocity, tx-line parameters, and model
parameters of discontinuities.
• Basic theory
1 r
Z DUT  Z o
;
1 r
Vreflected Z DUT  Z o
r

Vincident Z DUT  Z o
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37
at node A
Impedance & Velocity
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38
Peeling Idea for Reflections
• Multiple reflections.
• Need minimize reflections prior to DUT & TDR
– Use a controlled-impedance, low-loss cable btw TDR & probe
– Use a low-loop-inductance, controlled-impedance probe
J. M. Jong and V. K.
Tripathi, IEEE T-CHMT,
pp. 497-504, Aug .
1992
J. M. Jong, B. Janko
and V. K. Tripathi,
IEEE T-CHMT, pp.
119-126, Feb. 1993
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41
Inductive Load in Middle of a Line
r max
2Z t
 0r 
L 
L

1  e

2tr Z 0 

vs
vs L
Aind 
;
4Z0
vs: excitation voltage
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42
Capacitive Load in Middle of a Line
CD
VB-Ei
Vr
Tw,50
Acap
vs Z 0C

;
4
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43
Discontinuity Loading
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44
Equally Spaced Capacitive Loads
Z 0  49.7
 d  0.573ns
C L  2 pF
t r  0.35ns
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45
FLY-BY Topology in DIM and Modeling
A
B
C
Simulation Model
f= 800 MHz
Tr=125 ps
Voltage = 1.5v
+
A thick trace (10mil)
R1= 40 ohm
_Microstrip (10 mil) Stripline (10 mil)
thin trace (trace width: 4mil)
Package
+
B
_
stripline (4 mil)
R
R
R
R
R
R
R
R
L
L
L
L
L
L
L
L
C
C
C
C
C
C
C
+
C
_
R2= 40 ohm
C
TDR at A and TDT at B will be considered under DDR3 to discuss
effects of FLY-BY trace design (width 10mil vs. 4mil).
R. B. Wu
46
Simulation
Results
A
R1= 40 ohm
trace width
Microstrip (10 mil) Stripline (10 mil)
stripline (4 mil)
f= 800 MHz
+
B
_
Tr=125 ps
R
R
L
L
C
R2= 40 ohm
C
1
1
VA
TDR
0.8
Voltage (V)
0.8
Voltage (V)
VB
TDT
0.6
0.4
0.6
0.4
0.2
0.2
Trace W idth = 4 m il
Trace Width = 10 mil
Trace W idth = 4 m il
Trace Width = 10 mil
0
0
0
1
2
3
Time (nSec)
4
5
6
0
1
2
3
4
5
6
Time (nSec)
Suitable trace width (thin trace) improves impedance match.
H.-H. Chuang, et al., “Signal/power integrity modeling of high-speed memory
modules using chip-package-board co-analysis,” IEEE T-EMC, May 2010.
R. B. Wu
47
Inductance Measurement by TDR
Z0
L
Z0
Voc


0
vs ,DUT (t )  vs ,ref (t ) dt
Rem.:
different formula
if matched at
right end
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48
Capacitance Measurement by TDR
Z0
1
C
Z 0Voc


0
vo,ref (t )  vo,DUT (t ) dt
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49
Termination Design
50
Termination Schemes to minimize reflection noise
• Decrease system frequency
• Shorten PCB traces
• Termination with matched impedance
– Source termination
• On-die source termination
• Series source termination
– Parallel termination (Load termination)
• Load termination with a resistive load
• AC load termination
• Active termination
Ref.: H. Johnson & M. Graham, High-Speed Digital Design, Sec.6.1-4
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51
Source Termination
• On-die source termination
Difficult to guarantee matched buffer impedance!
• Series source termination
Add cost to board, and consumes board area!
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52
SI is about Finding & Fixing Problems
3 inch long PCB Trace
3 inch long PCB Trace
Series termination (~40 Ohms)
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53
Source Termination
suggested :
Rs  Rop  Z 0
 overshoot
T10-90  2.2 RC  2.2Z 0C
2
 VDD  1
E  2 f 

2

 R
Power 
2
(Pulse Freq.)  f VDD
2R
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54
Load Termination
• Load termination with a resistive load
Power delivery and thermal problems!
• AC load termination
Capacitor value need be optimized for specific design
R. B. Wu
Capacitive loading increases signal delay!
55
Load Termination
Eq. ckt
CD
Tterm.  2.2 RC
 2.2  C  ( RL // Z 0 )  1.1Z 0C
2
net risetime : Tterm
 tr2
Too much power consumption!
R. B. Wu
56
Split Termination
match  R1 // R2  Z 0
Pload 
(VHI VEE ) 2  (VLO VEE ) 2
2 R2

(VCC VHI ) 2  (VCC VLO ) 2
2 R1

( V ) 2
2Z 0
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57
Load Termination for Multiple Lines
• Bifurcated line
with matched
trace impedance
• Daisy-chain configuration
Cap. of each
short stub adds
to cap. load of
receiver
End termination
R. B. Wu
58
AC Load Termination
R1C  clock time
• Power saving (in DC-balanced circuit)
PR1 
( V / 2 ) 2
Z0

( V ) 2
4Z0
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59
Match by Series/Parallel Termination
Parallel
termination
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60
Active Termination
V
25 Ω
L
H
V
1
25 Ω
H
L
2/3
TTL / CMOS
50 Ω
Clamp to -1V on HIGHto-LOW (limit signal
undershoot)
L
R0
L
L
L
L
Suitable for any Z0
Power saving
L
Voo
ECL
0.1 μF
Vbb
R. B. Wu
61
Comparisons
• Rise time of an end-terminated circuit, when capacitively
loaded, is half of a series-terminated line driving same load.
• Most TTL or CMOS gates can’t source enough current to
drive end terminators. Split termination or capacitive
termination can be a remedy.
• One can daisy-chain receivers on an end-terminated line.
• At low-pulse repetition rates, source terminations dissipates
little power.
2
 V  1
• Peak drive power for source-terminated line is  2  R
same as end-terminated line (biased at halfway point)
R. B. Wu
62
Did you learn?
• What’s diff. of “distributed” from “lumped” circuits?
• How to solve “analytically” tx-line circuits with R,
L, and C loading/discontinuities?
• Load & source reflection coeff. & bounce diagram.
• Operation principle of time domain reflectometry.
• How to extract tx-line parameters & discontinuities
from TDR measurement?
• How to mitigate reflection?
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63
References & Further Reading
• F. H. Breanin, Jr., “Transient analysis of lossless transmission lines,”
IEEE Proc. Lett., pp.2012-2013, 1967.
• J. M. Jong, B. Janko, and V. K. Tripathi, “Equivalent circuit modeling of
interconnects from time-domain measurements,” IEEE T-CHMT, vol. 16,
pp. 119-126, Feb. 1993.
• M.-H. Wang and R.-B. Wu, “Measuring method for equivalent
circuitry,” USA Patent 6,137,293, Oct. 2000.
• H.-H. Chuang, et al., “Signal/power integrity modeling of high-speed
memory modules using chip-package-board coanalysis,” IEEE T-EMC,
vol. 52, pp. 381-391, May 2010.
• K.-Y. Yang, et al., “Modeling and fast eye-diagram estimation of ringing
effects on branch line structures,” IEEE T-CPMT, Apr. 2014.
• A. Boutar, et al., "An efficient analytical method for electromagnetic
field to transmission line coupling into a rectangular enclosure excited by
an internal source", IEEE T-EMC, pp. 1-9, 2015.
R. B. Wu 64
References & Further Reading
• A. Beygi and A. Dounavis, "Analysis of excited multi-conductor
transmission lines based on the passive method of characteristics
macro-model," IEEE T-EMC, vol. 54, pp. 1281 - 1288 , Dec. 2012.
• F. Capolino, et al., "Equivalent transmission line model with a lumped
X-circuit for a meta-layer made of pairs of planar conductors,” IEEE
T-AP, vol. 61, pp. 852-861, Feb. 2013.
• G. Lugrin, et al., "High-frequency electromagnetic coupling to multiconductor transmission lines of finite length,” IEEE T-EMC, vol. 57,
pp. 1714-1723, Dec. 2015.
• M. Chernobryvko, D. De Zutter, and D. Vande Ginste, "Nonuniform
multi-conductor transmission line analysis by a two-step perturbation
technique", IEEE T-CPMT, vol. 4, pp. 1838-1846, Nov. 2014.
• G. Antonini, et al., "Review of Clayton R. Paul studies on multiconductor transmission lines", IEEE T-EMC, vol. 55, pp. 639-647,
Aug. 2013.
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