Advanced Market Series
Applying Moore’s Law to Printed Circuit Boards
Averatek’s Additive Metallization Process
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Table of Contents
Advanced Market Series
Introduction ................................................................................................................................................ 3
Needs Driven Applications .......................................................................................................................... 3
Chip scale integration ............................................................................................................................. 3
High density circuits ................................................................................................................................ 4
Embedded active components ............................................................................................................... 4
Micro-vias ............................................................................................................................................... 5
Environmental improvement.................................................................................................................. 5
One Application Example Driving Higher Density: Intravascular Instruments ........................................... 5
Averatek Technology .................................................................................................................................. 6
The History .............................................................................................................................................. 6
The Innovation ........................................................................................................................................ 6
Additive Process...................................................................................................................................... 7
High conductivity metal .......................................................................................................................... 7
Fine Line and Spaces ............................................................................................................................... 8
Thin copper ............................................................................................................................................. 9
Scalability and Business Model ............................................................................................................... 9
Metalizing Via Surfaces ......................................................................................................................... 11
A Semi-Additive Process Version .............................................................................................................. 12
Benefits ..................................................................................................................................................... 12
Process simplification ........................................................................................................................... 13
Cost reduction....................................................................................................................................... 13
High Density Design Facilitation ........................................................................................................... 13
Summary ................................................................................................................................................... 14
List of Figures
Figure 1: Embedded Active Components on Multi-Layer Boards.............................................................. 4
Figure 2: Example of Non-Planar 3D Printed Circuit Application ............................................................... 6
Figure 3: The Additive Averatek Process ................................................................................................... 7
Figure 4: Cross Section of a Conductor Made with the Averatek Process ................................................ 8
Figure 5: Fine Line Samples ........................................................................................................................ 8
Figure 6: Scalability of the Averatek Process ............................................................................................. 9
Figure 7: 35 micron diameter via in 25 micron thick polyimide .............................................................. 11
Figure 8: Comparison of Print-and-Plate of Pre-Drilled Vias for Subtractive Etch Processes ................. 13
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Advanced Market Series
Introduction
The needs of the large printed circuit board markets ($30-plus billion for rigid boards, $10 billion-plus
for semi-rigid and flexible printed circuits) are driven by new electronics applications that require
higher performance with lower costs for the consumer, medical, military, and automation industries.
These needs translate into higher conductor and component density, higher speed, broader
bandwidth, finer lines, and thinner conductors and layers. Loosely defined, one could call this the
Moore’s law effect for flexible and rigid circuit boards.
Up until just recently, designing and manufacturing printed circuit boards using subtractive etch
processes have supported the trending needs of greater density at lower cost. However, the tendency
of etchant chemistries to undercut metal patterns is creating a barrier of how fine a line or thinness of
copper can be practically or cost effectively achieved. For all practical purposes, subtractive etch
processes become more costly (to the point of being cost prohibitive) below 25 m line widths and 15
µm copper thickness. Overcoming this barrier requires metallization processes that are predominantly
additive.
Averatek Corporation, a high tech company based in Santa Clara, CA provides patterned flexible circuit
board materials manufactured through the use of a patented innovative and additive metal “print and
plate” process. The Averatek technology is a cost effective process for creating metal lines/spacing for
widths below 10 microns and for depositing copper to a thickness level from 0.1 micron up to 10
microns or more. The additive feature of this technology allows the direct deposition of copper on a
flexible or rigid substrate in the pattern specified by the circuit design artwork without tie coat,
adhesive, etching, or waste of copper.
Needs Driven Applications
There is a variety of applications that are requiring denser packaging at affordable costs. These
include:
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Mobile devices (higher frequency and higher bandwidths for smart phones, tablets, etc.)
Touch screens (using metalized grids to permit new functionality in thinner packages)
Interposers (interfacing high pin-out components to printed circuit board conductors)
Rigid PCBs (efficient metallization of micro-vias and fine line geometry, supporting high-pin out
embedded components)
Medical devices (permitting lower cost and higher density for diagnostic and therapeutic
instruments)
Chip scale integration (reducing packaging costs and assembly complexity)
HD Displays (chip scale integration, higher density displays)
ITO replacement (using widely spaced fine line metal grids to replace slightly conductive
transparent oxide coatings)
These applications are driven by several design, cost, and process needs. A brief examination of the
more important needs is presented in the following.
Chip scale integration
Dale Wesselmann of MFLEX stated in a recent article (PC Design Magazine, March 29, 2013, p15) that
there was the potential to reduce the cost of the active devices on a flexible printed circuit board by a
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Advanced Market Series
significant amount with chip scale integration since up to 50% of the current cost is packaging, test,
and design. He also estimated that the weight and thickness of a finished flex circuit could be reduced
significantly since the dies are such a small part of the mass of a packaged chip.
This significant cost reduction is available only if the pin-out circuitry in the chip package and the
interposer board that is often used to provide further pin-out spacing can be replaced by a flexible
substrate that has metal conductors with widths down to single digits of µm. Having one printed circuit
substrate that can support both fine line and conventional conductor geometries is the key to the
elimination of the intermediate packaging and interconnect devices that stand as present obstacles to
chip scale integration. The Averatek process provides this benefit because it employs imaging
technology used by the semiconductor industry and is additive in its metallization approach.
High density circuits
Conventional subtractive etch printed circuit processes are approaching the limits of the durability,
speed, and bandwidth of the conventional subtractive etch processes used today to make flex circuits.
Product designers want to pack more electronics in smaller spaces which means greater circuit density
is required. Circuit density usually means more circuit complexity and more layers. Also since flex
circuit manufacturing and warranty costs tend to be proportional to the square of the number of
layers, the cost of new product designs using existing manufacturing methods are increasing
exponentially. Solving this “three dimensional” problem requires narrower and more closely spaced
conductors, thinner layers of conductor metal, elimination of tie coat materials, and lower cost
manufacturing. And ideally, the solution should also use greener manufacturing processes. Averatek’s
innovative print and plate technology provides all these benefits.
Embedded active components
Increasing circuit density and reducing the size and weight of electronic assemblies has been aided by
the continuing shrinking of the semiconductor devices (Moore’s Law first application) used in these
assemblies. A parallel trend has been the integration of passive components (capacitors, resistors,
inductors) into the assembly, i.e. the placement of passive components in the printed circuit board
rather than on the board. For example in Figure 1, a comparison of a typical PCB assembly is made to
one with imbedded passive components.
Figure 1: Embedded Active Components on Multi-Layer Boards
Conventional 2D PCB Packaging
Embedded Technology for 3D PCB Packaging
Transferring components from the surface to inside the multiple layers of a PCB assembly frees up 30%
to 50% of the outer surface area of the assembly for more important active (processor, memory,
special purpose chips) components. However, with the advent of new thinking about chip scale
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Advanced Market Series
integration, embedding active components in the assembly is becoming an attractive, albeit new,
design alternative. Of course, as with the chip scale integration issue, there is a need for fine line metal
conductors and micro-vias on each layer to support such embedding.
Micro-vias
A via is an electrical connection between one or more layers in a PCB assembly. It consists of two pads
in corresponding positions on different layers of the board assembly that are electrically connected by
a hole through the layers. The hole is made conductive by electroplating the interior walls of the via
and ultimately by filling the via with metal. High-density multi-layer PCBs usually have micro-vias that
have diameters of less than 50 µm. They are either (1) blind vias that are exposed only on one side of
the board, (2) buried vias that connect internal layers without being exposed on either outer surface,
or (3) thru vias that connect both outer surfaces. Vias can carry either electrical signals or thermal
energy to move heat away from power devices. Conventional plating technologies often have
problems that reduce yield and performance. These problems include inadequate coverage of interior
walls of high aspect ratio blind vias and damage to previously processed metallized areas. Averatek’s
technology thoroughly coats the interior of blind as well as open vias thus improving yields and
producing high quality metallization of the interior micro-vias, both of which reduce the cost of the
finished assembly and give designers more flexibility in laying out the assembly.
Environmental improvement
Another growing need is for more ecologically friendly processes and materials. For flex circuits this
means minimization of the waste of materials and minimization of the use of environmentally toxic or
unfriendly materials. Subtractive etch processes use a variety of etchant solutions to remove between
50% to 75% of the original metal from the flex circuit material. Semi-additive vacuum sputtered metal
processes typically use a seed layer of chromium which is a heavy metal that is being removed from
the market by new environmental regulations in the North American and European markets and which
also requires an etchant process. Either way, expensive materials are wasted, environmentally toxic
etchants are required, or both. With the Averatek technology, little or no metal is wasted, nor is
etching required to define the desired circuit.
One Application Example Driving Higher Density: Intravascular Instruments
Advances in arthroscopic and endoscopic surgery tools has also lead to a variety of other intravascular
instruments and devices which provide for minimally invasive diagnostic, therapeutic, and surgical
procedures. The desire to reap increasing performance and benefits by embedding more intelligence,
sensors, and communications into such intravascular tools is driving the need for greater densities and
more 3D configurations in the applied electronics assemblies. This is driving the need for higher
density circuits, chip-scale integration, micro-vias, and 3D circuit design. The Averatek additive process
is ideally suited to support and enable all of these required process features. The state of the art in
integrating electronic assemblies onto intravascular instruments is for flex circuit assemblies to be
glued to a wire or catheter that provides the transport mechanism and the delivery of the surgical or
therapeutic tool to the in vivo site. Averatek is providing benefits to this type of application now. In
the future, the Averatek technology can provide integration of the electrical conductor circuits directly
on the wire or catheter, thus eliminating interposer layers, electrical wires, and other electronic
assembly packaging. Figure 2 below illustrates the non-planar 3D electronic assembly made possible
with Averatek technology.
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Advanced Market Series
Figure 2: Example of Non-Planar 3D Printed Circuit Application
Averatek Technology
The History
Averatek Corporation was founded by SRI International, a global contract research and development
institution, and a team of successful Silicon Valley entrepreneurs who have a long history in specialty
metal plating businesses and products for companies in the computer, storage, and automation
industries. SRI International was part of Stanford University as the Stanford Research Institute from
1946 until 1970 when it became an independent non-profit contract research firm. SRI has been
developing and commercializing advanced technology products and processes for over 60 years.
Scientists at SRI invented and patented the technology that is at the heart of the Averatek process.
Averatek has established its first production facility in Santa Clara, CA. The first production line is
composed of custom designed equipment that has an initial capacity of more several million circuit
units of output per year.
The Innovation
The key breakthrough innovation has been the development of a special catalytic precursor “ink” that
can be imaged to create the patterns or areas where conducting metal is to be deposited. This ink
controls the horizontal dimensions of line width and spacing. The vertical dimension of metal thickness
is controlled by using a proven additive plating process that deposits metal only on the patterns
defined by the precursor ink. An additional benefit is that the interior of vias can be plated with metal
using the same process and at the same time that the surface conductors are also coated with the
Averatek precursor ink. The precursor ink promotes good bonding between the thin metal patterns
and the substrate, which improves lifetime and eliminates the need for adhesives and other tie-coat
bonding methods. This “print and plate” process is patented and has been taken to commercial scale
by Averatek Corporation.
There are actually a variety of innovations that have been developed as part of the commercialization
of this print and plate technology. These innovations include: (1) design of a catalytic ink which serves
as a delivery mechanism for a special catalytic compound. This delivery mechanism is advantageous
because in addition to eliminating the need for adhesive materials and layers and expensive toxic tie
coats, it also the pattern of where the metal is to be deposited. The ink solution can then be deposited
as either a coating or in a pattern using a printing technique; (2) “tuning” of the precursor ink to a
variety of coating/printing techniques to deposit the precursor ink; (3) a curing process which converts
the catalytic compound molecules left behind from the dried ink into active catalysts for the metal for
which the compound has been matched and selected. When the catalytic molecules have been
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Advanced Market Series
activated, each molecule becomes a bonding agent between the substrate and the metal molecules in
an electroless plating bath; (4) application to a variety of substrates for which the precursor ink was
designed. The substrates include a wide range of films made of filled and unfilled polyimides,
polyesters, polycarbonates, and rigid three dimensional parts such as FR4 boards, plates, molded parts,
and drawn fibers. This variety of substrate types and shapes creates the opportunity for metalizing for
both electrical applications as well as decorative applications; (5) application using a variety of metals
that can be deposited by this technique; and (6) metallization of the inside walls of vias that have been
created in the substrates at very early process stages, avoiding the need and additional process steps
required to coat the vias later in the process.
Additive Process
The most advanced application of the Averatek technology is for additive processes as illustrated in
Figure 3. First the Averatek precursor ink is imaged and cured on a substrate (ideally with vias already
in place) resulting in an invisible pattern of active material that is only a few angstroms thin. Second,
copper is deposited on the invisible pattern left by the imaged ink using one or more steps of
electroless (E-less) or electrolytic (E-lytic) plating baths. The final result is a substrate with metallized
patterns and metallized vias.
Figure 3: The Additive Averatek Process
High conductivity metal
Unlike conductive inks which tend to be highly resistive composites of metal flakes, polymers, and
other fillers, the copper deposited on the Averatek imaged patterns takes the form of fine grain,
densely packed, ductile, smooth, annealed, and highly conductive material which has electrical
properties similar to that of high quality copper wire or rolled copper foil. Since many of the
applications requiring fine line geometries have to support high speed and therefore high frequency
signals, the smoothness and quality of the conducting metal is critical. The process developed by
Averatek produces conductor whose cross sections are rounded and whose surfaces are smooth. Both
qualities are ideal for high frequency circuitry to minimize cross talk, shorts, and energy losses. An
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Advanced Market Series
example of a typical cross section of a conductor created using the Averatek process is shown in Figure
4.
Figure 4: Cross Section of a Conductor Made with the Averatek Process
Fine Line and Spaces
The two dimensions of length and width of metallized patterns are created with the Averatek imaging
technology. The imaging technology used today by Averatek for its commercial offerings is based on
high resolution photolithographic equipment used today for semiconductor and high density circuit
applications. Averatek can deliver fine lines down to 5 µm in width and spacing on the same substrate
with geometric features that can be measured in hundreds of µm. A sample of copper lines created on
commercially available polyimide is shown in Figure 5.
Figure 5: Fine Line Samples
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Advanced Market Series
Thin copper
The third dimension of height or thickness of the metallized patterns is created using conventional but
finely tuned electroless and/or electrolytic plating processes. By using this additive plating approach,
the thickness of the copper in the metallized patterns can be custom selected or “dialed in”.
The typical conventional processes in the rigid and flex circuit board industries today start with sheets
of copper foils (available only a few thicknesses) that are laminated to a substrate. If the required
thickness is different than the foil thicknesses available, then the copper has to be etched down or
plated up to the necessary thickness. However, the trend of higher density and finer line circuits is
accompanied by a trend to thinner copper.
An alternative to the laminated copper foil substrates that has been used for many years is sputtered
or vacuum deposited copper. This type of process often requires that a thin tie coat of chromium,
nickel, or steel be vacuum deposited on the substrate before the copper is vacuum deposited. These
processes have provided a non-adhesive approach to achieve thin copper, but the additional expense
of the vacuum sputtered processes and a loss of some key qualities in the mechanical performance of
the deposited copper. The Averatek additive process is also non-adhesive, but is lower in cost,
eliminates the need of the sputtered heavy metal tie coats, and provides excellent mechanical
properties.
Scalability and Business Model
Of course one of the key questions for any innovative new production process is whether it is scalable
to the volumes required for the markets that it will serve. The list of applications shown above
indicates that the range of production volumes goes from low volume medical devices to high volume
consumer electronics products. The Averatek process has been designed to support the full range of
applications volumes and the various types of customers for each. The diagram in Figure 6 helps
illustrate how Averatek’s business model has evolved to support the customers across the range of
volumes.
Figure 6: Scalability of the Averatek Process
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Advanced Market Series
The full Averatek process consists of 6 basis steps as follows:
1. Preparation of the substrate material for processing. In most cases this is a simple cleaning and
mounting of the material in the appropriate material handling system (either roll-to-roll or
panels)
2. Drill vias in the substrate using either mechanical or laser drills (this step is optional if the
customer’s process includes creating vias after the Averatek process has been completed or
does not include vias)
3. The substrate is coated with the special Averatek precursor catalytic ink and cured resulting in a
subnano-layer (<1nm thick) of catalytic material.
4. The subnano-layer of cured ink is imaged using photolithographic techniques to create the
patterns where copper will be deposited. At this stage the patterns are virtually invisible but
ready for copper deposition. The geometry of lines and spaces that can be produced at this
point is anything above 3 µm.
5. Electroless copper is deposited only on the patterns designated by the ink from the previous
step. The thickness of copper for this step ranges from 0.1 µm to 1.0 µm.
6. If thicker copper is needed, then the sixth step is electrolytic plating.
Averatek has demonstrated that each of the process steps can be scaled up to volume production
using roll-to-roll technology as well as panel processing.
Customers may require further processes such as nickel or gold flash plating or overlays, but for the
purpose of this discussion, only the steps for depositing the conducting copper patterns are discussed.
Averatek’s business strategy from its inception has been to provide patterned electronic materials to
printed circuit fabricators (small and large) and final component manufacturers. Conventional
providers of electronic materials sell a dielectric substrate that has one or both surfaces totally covered
with a layer of copper (laminated copper foil or sputtered field coated) which the fabricator or
manufacturer then has use subtractive etching processes to produce the patterns and plate the vias in
an iterative sequence of wet chemistry steps. Averatek’s patterned electronic materials eliminates
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Advanced Market Series
most of these etchant pattern-making steps thus reducing cost, improving yields, and providing fine
line capabilities not easily available from the conventional processes.
Thus for many of the higher value, lower volume applications such as medical devices, the full benefit
of Averatek’s six steps are required because it provides fabricators and manufacturers with high value
quick to implement advanced design options.
However some manufacturers who have high volume needs and who have invested in high volume
electrolytic plating technology may only need the Averatek patterned electronic materials that have
just the thinnest of copper from Step 5.
Similarly manufacturers who have high volume needs and who have also invested in electroless plating
production lines may only need the Averatek patterned electronic materials that have only the nanolayer of patterned cured ink on the substrate from Step 4.
If a manufacturer also has the appropriate lithographic imaging technology, the Averatek coated
electronic materials from Step 3 may be useful to a high volume manufacturer.
If a manufacturer has not yet made the investment in the technology require to complete Steps 3
through 6 but wishes to integrate the Averatek technology with their existing manufacturing
operations, then under mutually beneficial business arrangements, Averatek will license the rights to
use the technology, provide technology transfer consulting to assist the licensee in setting up an
integrated process line, and then sell the consumable items required by the installed line.
Metalizing Via Surfaces
Metalizing via surfaces at the very earliest stages of a production process is an innovation that offers
the elimination of several process steps that are currently embedded in the conventional
manufacturing of flexible circuit boards that use subtractive and semi-additive processes. Typically vias
are plated and filled at later stages in the flex circuit board layer manufacturing process because of the
manufacturing processes associated with flex circuit materials that are either adhesive-based or
vacuum sputtering on metal tie coats. Using the precursor ink technology described above, copper can
be deposited on the inner surfaces of vias at the very earliest stages of a flex circuit production
process.
The demonstration of using the print and plate method for vias is shown in Figure 7. In Figure 7(a), a
microscopic picture of a via that is 35 microns in diameter and which is laser drilled in commercially
available film of polyimide that is 25 microns thick is shown.
Figure 7: 35 micron diameter via in 25 micron thick polyimide
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Advanced Market Series
Fig 7(a) Via in Polyimide
Fig 7(b) Copper Plated Via
Fig 7(c) Cross Section
In Figure 7(b), a via of the same size is shown with a layer of copper that is approximately 1 micron
thick that has been deposited using the Print and Plate process described above. In Figure 7(c), a cross
section of the via in Figure 7(b) is shown to highlight the degree of uniformity of the copper thickness
from the surface of the polyimide to the inner walls of the via.
A Semi-Additive Process Version
Despite the many advantages of using a fully additive metallization process for making printed circuits,
there are some circuits where design and copper thickness requirements make a fully additive
approach difficult. The fully additive approach described in Steps 4 through 6 above requires that
there be electrical contact in Step 6 to the metallized pattern created in Step 5 to allow the electrolytic
plating process to be completed. This can be achieved in a variety of ways which usually involves
adding in easily removed or inconsequential conductors on the pattern itself or with custom designed
anodes. If neither of these options is attractive, then a semi-additive approach can be taken using the
Averatek process. Many legacy designs require this approach, but once the design team understands
the possibilities of the Averatek approach, subsequent designs often don’t require semi-additive steps
Typically a semi-additive approach involves the creation of a large area pattern (possibly the entire
surface) of copper in Step 4 which then produces a micro-layer of copper ( < 0.1 µm) in Step 5. This
thin copper layer then can act as a ground plane for the electrolytic process in Step 6. This approach
requires a modification to Step 6 to include a photolithographic step to image the pattern of copper to
be built up on the ground plane from Step 5 and a flash etch step to remove the seed layer of copper
not patterned after the electrolytic process is completed. All of the benefits for fine line geometry from
the additive process are preserved as well as the cost savings by avoiding the need for sputtered
vacuum deposition. However, there is some additional processing required when compared to the
fully additive process.
Benefits
The benefits that the Averatek fully additive process has over the conventional subtractive etch and
semi-additive sputtered processes fall into in three major categories: (1) process simplification, (2)
cost reduction, and (3) high density design facilitation.
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Advanced Market Series
Process simplification
In the illustration in Figure 8, the advantages of the Averatek additive print-and-plate process over the
conventional subtractive etch methods are clear: an entire iteration of imaging and etching is
eliminated. These advantages are available to Averatek customers whether they are getting products
from Steps 4, 5, or 6 of the Averatek process. By eliminating the extra activities associated with the
extra imaging and etching, there is less time needed in the end-to-end process, there are fewer
opportunities for mistakes, less consumable material required, higher yields, and less waste and
recycling necessary.
Figure 8: Comparison of Print-and-Plate of Pre-Drilled Vias for Subtractive Etch Processes
Cost reduction
All of the benefits from process simplification directly translate into cost savings. A cost model of the
subtractive etch process indicates that savings in the direct costs of goods sold for the finished part can
be in the range of 10% to 30% and up to 25% in reduction of cycle time depending on the degree of
complexity or density of the circuit. If the circuit design to be manufactured is pushing the boundary of
density, thinness, and chip-scale integration, the cost saving and cycle time reduction of the finished
product compared to that from using conventional processes will likely be even higher and could be in
the range of 40% to 70%.
High Density Design Facilitation
Due to the precursor ink and additive nature of the Averatek process, there are opportunities to
implement high density metallization of circuits that would be difficult if impractical using conventional
methods. Applications that would benefit from chip-on-flex integration, embedded actives on rigid
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Advanced Market Series
PCBs, copper conductors on molded or extruded parts also are now possible using the Averatek
process.
High Density PCBs
Rigid PCBs also benefit from the step reduction, blind via plating and through-hole capabilities of the
Averatek process. Averatek processes can provide high yielding blind and through hole via plating,
along with ultra fine trace and space capability. Conventional subtractive barriers are shattered with
the additive or semi-additive process, providing high density circuits with reduced manufacturing
complexity at the same time. These capabilities can be mixed and matched with conventional board
manufacturing techniques, with little or no modification to existing lines.
Summary
The Averatek technology is a cost effective process for creating metal lines/spacing for widths below
10 microns and for depositing copper to a thickness level from 0.1 micron up to 10 microns or more.
The additive feature of this technology allows the direct deposition of copper on a flexible or rigid
substrate in the pattern specified by the circuit design artwork without tie coat, adhesive, etching, or
waste of copper. The key advantages of Averatek’s innovative copper deposition process for flexible
circuit materials described above include (1) elimination of the need for multiple plating steps to plate
vias after they have been formed into circuitized materials, (2) the ability to deposit copper on the
surfaces of bare base material and in the interior of vias that are pre-formed in the base material, (3)
elimination of multiple expensive process steps normally associated with conventional copper coating
techniques, and (4) the achievement of excellent adhesion without the need for a tie coat of chromium
or nickel. This process has been implemented with a combination of a roll-to-roll/panel process and
can be scaled up to full roll-to-roll process.
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