A 1.9 μW 4.4 fJ/Conversion-Step 10 b
1 MS/s Charge-Redistribution ADC
Michiel van Elzakker, Ed van Tuijl, Paul Geraedts,
Daniel Schinkel, Eric Klumperink, Bram Nauta
IC Design group
University of Twente, Enschede, The Netherlands
http://icd.ewi.utwente.nl
Outline
• Introduction
• Key building blocks
– Charge-redistribution DAC
– Two-stage comparator
– Delay-line based controller
•
•
•
•
Simulation results
Measurement results
Benchmark
Conclusions
2
Introduction
• Features of this SAR ADC:
– Very low energy consumption
– 10 bit resolution
– No dissipation when not used
• Example application: wireless sensor nodes
3
Charge-redistribution
in
1
out
reset
2
out
reset
Vout (t 0 ) = ?
in
0
4
Charge-redistribution
in
1
out
reset
2
out
reset
Vout (t 0 ) = ?
Vout (t1 ) = Vreset
in
0
1
5
Charge-redistribution
in
1
out
reset
2
out
reset
Vout (t 0 ) = ?
Vout (t1 ) = Vreset
in
0
1
2
C1
C1
Vout (t 2 ) = Vreset +
⋅ ∆Vin = Vreset +
⋅ ∆Vin
C1 + C2
C total
6
Charge-redistribution
in
1
out
reset
2
out
reset
Vout (t 0 ) = ?
Vout (t1 ) = Vreset
in
0
1
2
C1
C1
Vout (t 2 ) = Vreset +
⋅ ∆Vin = Vreset +
⋅ ∆Vin
C1 + C2
C total
No energy dissipation in capacitors!
(capacitors store and deliver energy)
7
Switched charge-redistribution
C1 ⋅ C2
Ceq =
C1 + C2
Energy dissipated in switches:
E diss
1
= ⋅ Ceq ⋅ Vb2
2
8
Multiple step charging
Dissipation for total change of Vb:
2
E diss
1
1
⎛ Vb ⎞
= n ⋅ ⋅ Ceq ⋅ ⎜ ⎟ =
⋅ Ceq ⋅ Vb2
2
n⋅2
⎝ n ⎠
9
Multiple step implementation
• Big capacitors for intermediate voltages
– Voltages converge towards appropriate levels
– Comparable energy saving
• Theory: more steps ⇒ less dissipation
• Practice: dissipation in control logic
10
Switch implementation
11
Charge-redistribution DAC
• CR-DAC uses one accurate voltage and array of
matched capacitors
12
Charge-redistribution DAC
• CR-DAC uses one accurate voltage and array of
matched capacitors
VDAC (t1 ) = Vreset
VDAC (t 2 ) = Vreset +
CMSB
⋅ Vb
C total
13
Charge-redistribution DAC in SAR ADC
MSB
in
MSB
DAC
half
voltage
MSB
Vhalf
VDAC
Vin
time
14
Differential ADC
• Test chip is a 10 bit differential ADC
• Three most significant bits use multiple step charging
15
Two-stage comparator
16
Two-stage comparator
high gain ⇒
relatively low regeneration noise ⇒ energy efficient
17
Delay-line based controller
SAR accuracy requires sufficient delay rather than
accurate delay
18
Energy simulation
2.0
conversion energy
(pJ/conversion)
Total
1.5
1.0
Controller
0.5
Comparator
DAC + Register
0
T/H
0
100
time (ns)
500
19
Die micrograph
65 nm CMOS; dimensions in μm2
20
1.9 μW @ 1MS/s
6
4
2
0
1.3 1.2
1.1 1.0
0.1
supply voltage (V)
measured
max. sample
rate (MS/s)
measured supply
current (μA)
Measured sample rate / supply current
2.0
1.5
1.0
0.5 sample
rate (MS/s)
5
4
3
1.00
1.05
1.10 1.15
1.20 1.25
supply voltage (V)
1.30
21
DNL / INL measurement
Vsupply = 1V; fsample = 1 MS/s; fin= 499968.75Hz
DNL
LSB
0.75
-0.75
INL
LSB
2.5
-2.5
1
1024
(Fitted) INL increases near edges of range
22
FFT of measured ADC output
Half input range used; normalized to first harmonic
0
fin= 499968.75Hz
-50
P (dB)
-100
-150
0
0
500
f
f5 3
-50
-100
-150 0
3
497
500
f (kHz)
23
Summary of measured performance
SNR (dB)
THD (dB)
DNL (LSB)
INL (LSB)
SNDR (dB)
ENOB (bit)
Econversion (pJ/conversion)
Figure Of Merit
(fJ / conversion-step)
FOM =
Average
55.6
-61.1
0.49
2.24
54.4
8.75
1.9
Standard deviation
0.58
1.95
0.06
0.18
0.47
0.08
4.42
0.24
P
2 ⋅ BWeff ⋅ 2ENOB
=
ECONVERSION
2ENOB
24
FOM (fJ / conversion-step)
Benchmark
1000
Comparison with state-of-the-art ADCs
100
10
This work
1
13.5 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8
ISSCC 2007
ISSCC 2008
25
Conclusions
• Multiple step charge-redistribution DAC can
have a very low energy dissipation
• New topology for energy efficient comparator
• Record low FOM of 4.4 fJ/conversion-step
• Suitable for low power applications like wireless
sensor nodes
26
27