Abstract #858, 223rd ECS Meeting, © 2013 The Electrochemical Society
2
Hole mobility (cm /Vs)
Coulomb scattering
600
GeOx=1.2 nm
EOT=1.09 nm
400
GeOx=0.27 nm
EOT=0.98 nm
200
GeOx=1.4 nm
EOT=1.18 nm
<110>/(001) Ge pMOSFETs
0.1
1
12
10
-2
Ns (10 cm )
Fig. 1 Mobility of Ge pMOSFETs with the Al2O3/GeOx/Ge gate
stacks having different GeOx ILs thicknesses.
3
11
@Ns=5x10 cm
-2
2
S factor
(mV/dec)
factor(mV/dec)
S.S.
2
1
200
1.2 nm GeOx
150
100
50
0
T
. 120
S.S.(120K)
0
100
200
300
Temperature (T)
0
1
2
3
12
4
2
5
Dit (10 cm /eV)
Fig. 2 The mobility of Ge pMOSFETs with Al2O3/GeOx/Ge
gate stacks (@NS=5×1011 cm-2) as a function of Dit evaluated
from the S. S. factors measured at 120 K. Inset t shows the
temperature dependence of S factor.
4000
w/ buffer (2/5/3 nm)
3000
2
Mobility [cm /Vs]
(body thickness)
w/o buffer
(10 nm)
2000
1000
x 1.6
x 4.2
Si MOSFETs
15
N =4x10 cm
-3
A
0
12
12
2x10
13
6x10
1x10
-2
N [cm ]
S
Fig. 3 eff characteristics of In0.7Ga0.3As-OI MOSFETs with and
without MOS interface buffer.
7000
(a)
In Ga As w/ buffer
0.7
4000
T
eff [cm2/Vs]
MOSFETs using III-V/Ge channels with high mobility
and low effective mass have been regarded as strongly
important for obtaining high current drive and low supply
voltage CMOS under sub 10 nm regime [1, 2]. Thus, the
development of the device technologies for III-V/Ge
MOSFETs has been strongly accelerated. However,
fundamental device physics on electrical properties of IIIV/Ge MOSFETs has not been fully clarified yet. Among a
variety of the electrical properties, understanding of
limiting factors of the III-V/Ge MOS channel mobility is
of paramount importance, because the purpose of
introducing these devices consists in the high current
drive. In this paper, thus, we address key issues for
enhancing channel mobility in InGaAs/Ge MOSFETs.
It is well known that superior MOS interface properties
can provide higher channel mobility, because of reduction
in Coulomb scattering and surface roughness scattering.
We have confirmed in Ge p-MOSFETs with ultrathin
GeOx interfacial layers formed by plasma post oxidation
[3], as shown in Fig. 1, that the GeOx thickness can
control the peak mobility in a low Ns region [4]. This fact
is attributed to lower Dit near Ev, estimated from the S
factor, in thicker GeOx, as shown in Fig. 2. On the other
hand, we have recently found [5] that the hole mobility in
Ge p-MOSFETs in a high Ns region is significantly
degraded by both trapping of free holes and severe
surface roughness scattering. Thus, further reductions in
MOS interface defect concentration and interface
roughness are expected to provide higher mobility.
We have reported through Hall measurements [6] that
the trapping of free electrons into interface states or slow
states within the conduction band also significantly
lowers electron mobility in InGaAs MOSFETs. In
addition, another critical factor for the electron mobility
reduction is the influence of the ultrathin body channels,
which are mandatory for short channel MOSFETs. It has
been reported that ultrathin Si channels severely reduce
the channel mobility, because of increased body thickness
fluctuation scattering [7]. This thickness fluctuation
scattering becomes worse for III-V MOSFETs with lower
effective mass and wider inversion-layer thickness. Thus,
we have proposed MOS interface buffer channel structure,
where InGaAs buffer layers sandwich InGaAs channels
with higher In content [8]. This structure is expected to
allow us to mitigate the influences of MOS interface
defects and the channel thickness fluctuation. Actually,
we have observed the significant mobility enhancement in
the In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As-OI structure over
single In0.7Ga0.3As-OI structures. The mobility was
evaluated with changing the thickness of the channel and
the buffer (Fig. 4). It is found that thickness fluctuation
scattering and surface roughness scattering dominate the
mobility in low and high Ns region, respectively.
This work was partly supported by a Grant-in-Aid for
Scientific Research (No. 23246058) from MEXT, and
Innovation Research Project on Nano electronics
Materials and Structures, and Research and Development
1000
800
-3
S. Takagi1, S.-H. Kim1, R. Zhang1, N. Taoka1, 2,
M. Yokoyama1, and M. Takenaka1
1
The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku,
Tokyo 113-8656 JAPAN
2
Nagoya University, Furo-cho, Chikusa-ku,
Nagoya 464-8603 JAPAN
e-mail: [email protected]
Program for Innovative Energy Efficiency Technology
from NEDO. The authors would like to thank Drs. T.
Yasuda, T. Maeda, W. Jevasuwan, N. Miyata, Y. Urabe
and H. Takagi in AIST, Drs. M. Hata, T. Osada, O.
Ichikawa, and N. Fukuhara in Sumitomo Chemical, and
Dr. H. Yokoyama in NTT for their collaborations.
1/ (10 Vs/cm )
Limiting factors of channel mobility
in III-V/Ge MOSFETs
body
T
body
0.3
-1.1
= 2/3/3 nm
N
1000
700
400
NS
= 2/5/3 nm
-0.8
S
T
body
= 2/1/3 nm
NS
-0.5
at 150 K
12
1x10
12
4x10
N [cm-2]
12
7x10
S
Fig. 4 eff characteristics of In0.7Ga0.3As-OI MOSFETs with a
MOS interface buffer layer as a parameter of the Tbody at 150 K
References [1] S. Takagi et al., Solid-State Electron. 51
(2007) 526 [2] S. Takagi et al., IEEE Trans. Electron Device
55 (2008) 21 [3] R. Zhang et al., Appl. Phys. Lett. 98 (2011)
112902 [4] R. Zhang et al., IEEE Trans. Electron Device 59
(2012) 335 [5] R. Zhang et al., presented in Tech. Dig. IEDM
(2012) [6] N. Taoka et al., Tech. Dig. IEDM (2011) 610 [7] K.
Uchida et al., Appl. Phys. Lett. 82 (2003) 2916 [8] S.-H. Kim
et al., Appl. Phys. Exp. 5 (2012) 014201