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CHAPTER 6
DESIGN OF SEQUENTIAL LOGIC CIRCUITS IN QCA
6.1
INTRODUCTION
The logic circuits whose outputs at any instant of time depend not
only on the present inputs but also on the past outputs are known as sequential
circuits. In sequential circuit, outputs are fed back to the input side. Thus an
output signal is a function of the present input signals and a sequence of
the past input signals. The block diagram of sequential circuit is shown in
Figure 6.1. It consists of a combinational circuit to which memory elements
are connected to form a feedback path. The storage elements are devices
capable of storing binary information. The binary information stored in these
elements at any given time defines the state of the sequential circuit at the
time.
Figure 6.1 Block Diagram of sequential circuit
The sequential circuit can be classified into two types depending on
the timing of their signals. They are
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1) Synchronous or clocked sequential circuits
2) Asynchronous or unclocked sequential circuits.
In the synchronous sequential circuit, synchronization is achieved
by a timing device called a master clock generator which generates a periodic
train of clock pulses. In practice, it may be achieved by applying clock pulses
to various AND gates through which external inputs enter the sequential
circuit. This ensures the gates to transmit input signals only which coincide
with the arrival of the clock pulses.
In an asynchronous sequential circuit, events can occur after one
event is completed and there is no need to wait for a clock pulse. Therefore, in
general, asynchronous circuits are considerably faster than the synchronous
sequential circuits. However, in an asynchronous circuit, events are allowed
to occur without any synchronization.
In this thesis, design of sequential circuits such as Flip Flops (FF),
Shift Registers (SR) and Counters are proposed. The different sequential
circuits are designed by using majority gate. Then the designed circuits are
implemented with QCA cells and simulated using QCADesigner. These
structures are popular designs in the transistor technology. The circuit designs
in QCA follow the conventional design approaches, but due to the technology
differences, they are modified and optimized for the best performance in
QCA.
6.2
DESIGN OF FLIP FLOPS (FF) USING MG
The memory elements in a sequential circuit are called flip-flops. A
circuit has two outputs, one for the normal value and one for the complement
value of the stored bit. Binary information can enter a flip-flop in a variety of
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ways and gives rise to different types of flip-flops. The most common types of
flip flops are
1. SR (Set-Reset) Flip Flop
2. D (Data or Delay) Flip Flop
3. T (Toggle) Flip Flop
4. JK Flip Flop
The flip flops are synchronous sequential circuits. Hence the
circuits change their states only when clock pulses are present. The basic
operation of these flip flops has been explained by Morris Mano (1995).
This section describes the architectures for the four flip-flops. By
replacing AND/OR logic with majority logic it is possible to significantly
minimize the total number of cells in the design. Since there is no static
memory equivalent in QCA, hence to create loops, which keep memory in
motion. The proposed architectures of the flip-flops have been shown below.
As a means for generating the QCA architecture an obvious first
step is to translate existing CMOS designs directly into QCA majority gate
logic. However, while such a translation is possible, the nature of QCA
devices will require an architecture that is radically different from
conventional CMOS. Hence first the sequential circuits are designed by using
conventional gates. Then it can be translated into QCA majority gate.
6.2.1
Design of SR Flip Flop
The clocked SR flip-flop shown in Figure 6.2 consists of a basic
NOR flip-flop and two AND gates. The outputs of the two AND gates remain
at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input
values. When the clock pulse goes to 1, information from the S and R inputs
passes through to the basic flip-flop. With both S=1 and R=1, the occurrence
of a clock pulse causes both outputs to momentarily go to 0. When the pulse
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is removed, the state of the flip-flop is indeterminate, i.e., either state may
result, depending on whether the set or reset input of the flip-flop remains a 1
longer than the transition to 0 at the end of the pulse.
(a) Logic diagram
(b) Graphic symbol
Figure 6.2 SR flip flop
Table 6.1 Characteristic table of SR flip flop
Q
S
R
Q(t+1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
Intermediate
1
0
1
Intermediate
Figure 6.3 Characteristic equation
Q (t+1) = S+R'Q
(6.1)
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The characteristics table of the flip flop is shown in Table 6.1. This
table shows the operation of the flip flop in a tabular form. The Q is an
abbreviation of Q (t) and stands for the binary state of the flip flop before the
application of a clock pulse, referred to as the present state. The S and R
columns give the possible values of the inputs, and Q (t+1) is the state of the
flip flop after the application of a single pulse, referred to as the next state.
The table must be interpreted as follows: Given the present state Q and the
inputs S and R, the application of a single pulse in the CP input causes the flip
flop to go to the next state Q (t+1).
The characteristic equation of the flip flop is derived by using the
map of Figure 6.3. This Equation (6.1) specifies the value of the next state as
a function of the present state and the inputs. The characteristic equation is an
algebraic expression for the binary information of the characteristic Table
6.1. The two intermediate states are marked with don’t-care X’s in the map,
since they may result in either 1 or 0. However, the relation SR = 0 must be
included as part of the characteristic equation to specify the both S and R
cannot equal to 1 simultaneously.
Next the SR flip flop is designed using majority gates with the help
of the characteristics equation. It is constructed by using 5 majority gates and
1 inverter as shown in Figure 6.4. The circuit have two inputs S and R along
with one control input Clock. The last two majority gates M4 and M5 form a
loop. The output of the flip flop is fed back to M4 and combined with the
input R'of majority gate M4 to produce R'Q. Here the gate M4 act as an AND
gate. The gate M5 is designed to perform OR operation which combine the
output of Majority gate M1 and M4.Hence the output of the gate M5 produce
the desired characteristic Equation (6.1).
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Figure 6.4 Design of SR flip flop using majority gate
Computation with QCA is accomplished by designing QCA
layouts, which exhibit the desired interaction of states. The designed SR flip
flop using majority gate is next implemented by using QCA cells. The flip
flop is implemented by 57 cells, with an area of 72,000 nm2. The cell
minimization techniques are used to minimize the number of cells from 78 to
57. The corresponding QCA implementation of SR flip flop is shown in
Figure 6.5.
Figure 6.5 Layout of SR flip flop
6.2.2
Design of D Flip Flop
One way to eliminate the undesirable condition of the
indeterminate state in the RS flip flop is to ensure that inputs S and R are
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never equal to 1 at the same time. This is done in the D flip flop as shown in
Figure 6.6 (a). The D flip flop is a modification of the clocked SR flip-flop. It
has only two inputs: D and CP. The D input goes directly into the S input and
the complement of the D input goes to the R input. The D input is sampled
during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to
the set state (unless it was already set). If it is 0, the flip-flop switches to the
clear state.
(a) Logic diagram
(b) Graphic symbol
Figure 6.6 D flip flop
Table 6.2 Characteristic table of D flip flop
Q
D
Q (t+1)
0
0
1
1
0
1
0
1
0
1
0
1
Figure 6.7 Characteristic equation
Q (t+1) = D
(6.2)
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The binary information present at the data input of the D flip flop is
transferred to the Q output when the CP input is enabled. The output follows
the data input as long as the pulse remains in its 1 state. When the pulse goes
to 0, the binary information that was present at the data input at the time the
pulse transition occurred is retained at the Q output until the pulse input is
enabled again.
The characteristics table of the D flip flop is shown in Table 6.2. It
shows that the next state of the D flip flop is independent of the present state
since Q (t+1) is equal to the input D whether Q is equal to 0 or 1. This means
that an input pulse will transfer the value of input D into the output of the flip
flop independent of the value of the output before the pulse was applied. The
characteristics equation shows clearly that Q (t+1) = D.
Next the D flip flop is designed with the help of the characteristic
equation. The flip flop is designed by two ways. First method is using
majority gates and the second method is using a QCA binary wire. In the first
method the flip flop is constructed by using 3 majority gates and 1 inverter as
shown in Figure 6.8. The circuit have one input D and along with one control
input Clock. The output Q of the flip flop is fed back to the majority gate M3
and combined with the input D to produce the output Q. Here the gate M1 act
as an AND gate and M2 act as an OR gate. The gate M3 is designed to
perform OR operation which combine the output of Majority gate M1 and
M2.Hence the output of the gate M3 produce the desired characteristic
Equation (6.2).
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Figure 6.8 Design of D flip flop using majority gate
The QCA implementation of the D flip flop is shown in Figure 6.9.
The QCA implementation requires 69 cells, with an area of 93,686 nm2 and
this also required less number of cells than previous implementations. This is
achieved by using cell minimization techniques.
Figure 6.9 Layout of D flip flop
Latching is effectively accomplished through timing by using a
four-phase clocking arrangement. Therefore, a D-type FF can be constructed
by a QCA binary wire with four clocking zones as shown in Figure 6.10. In
this case, the input signal is delivered to the output after at least one complete
clock cycle delay and control is accomplished by timing. The relative
simplicity of a D-FF seems to suggest that sequential design in QCA could be
achieved at ease within the Cartesian layout and have been proposed by
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Huang et al (2007). However, timing and signal delay must be carefully
considered.
Figure 6.10 Layout of D flip flop using binary wire
The wire which is clocked from left to right with increasing
clocking zones will carry information in the same direction. The clock signals
act to pump information in the circuit as a result of the successive latching
and unlatching in cells connected to different clock phases. Figure 6.10 shows
a wire connected to different clock zones. Each group of cells connected to a
particular clocking zone. The clocked QCA wire is used to carry the
information which is constructed by regular QCA cells. Hence in the QCA
wire input and outputs are equal and it act as a D flips flop. The D flip flop is
implemented by only 16 cells.
6.2.3
Design of JK Flip Flop
A JK flip-flop is a refinement of the SR flip-flop in that the
indeterminate state of the SR type is defined in the JK type. Inputs J and K
behave like inputs S and R to set and clear the flip-flop (note that in a JK flipflop, the letter J is for set and the letter K is for clear). When logic 1 inputs are
applied to both J and K simultaneously, the flip-flop switches to its
complement state, i.e., if Q=1, it switches to Q=0 and vice versa.
The Output Q is ANDed with K and CP inputs so that the flip-flop
is cleared during a clock pulse only if Q was previously 1. Similarly, output
Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock
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pulse only if Q' was previously 1. The behavior of the JK flip flop is
demonstrated in the characteristics table. A clocked JK flip-flop is shown in
Figure 6.11.
It is very important to realize that because of feedback connection
in the JK flip-flop, a CP signal which remains 1 while both J and K are equal
to 1 will cause the output to complement again and repeat complementing
until the pulse goes back to zero. To avoid this, the clock pulses must have
time duration less than the propagation delay through the flip-flop. The
restriction on the pulse width can be eliminated with a master-slave or edgetriggered construction.
(a) Logic diagram
(b) Graphic symbol
Figure 6.11 JK flip flop
Table 6.3 Characteristic table of JK flip flop
Q
J
K
Q(t+1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
0
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Figure 6.12 Characteristic Equation
Q (t+1) = JQ'+K'Q
(6.3)
Next the JK flip flop is designed by using the characteristic
equation. The flip flop is constructed by using 4 majority gates and 2 inverters
as shown in Figure 6.13. The circuit has two inputs J and K along with one
control input clock. The output Q of the flip flop is fed back to the input
majority gate M1 and the complement of the output is fed back to the majority
gate M3. The output of M1 and M3 are combined with the clock input by M2.
Here the gate M2 act as an OR gate to produce JQ’+K’Q. The gate M4 is used
to form a loop and to produce the desired characteristic Equation (6.3).
Figure 6.13 Design of JK flip flop using majority gate
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The QCA implementation of the JK flip flop is shown in Figure
6.14. The QCA implementation requires 46 cells, with an area of 36,000 nm2.
In the proposed QCA implementation, the required number of cells is 50%
reduced from the previous implementations. This is achieved by using cell
minimization techniques. Anoop Vetteth et al (2003) have proposed QCA
architecture for the JK flip-flop. It consists of 7 majority gates and takes 2 1/
4 clock cycles to complete the output, while our new QCA architecture
requires only one clock cycle.
Figure 6.14 Layout of JK flip flop
6.2.4
Design of T Flip Flop
The T flip-flop is a single input version of the JK flip-flop. As
shown in Figure 6.15, the T flip-flop is obtained from the JK type if both
inputs are tied together. The output of the T flip-flop "toggles" with each
clock pulse. The designation T comes from the ability of the flip flop to
toggle or complement, its state. Regardless of the present state, the flip flop
complements
its
output
when
clock
pulse
occurs
while
input
T =1.
The characteristics table and the characteristic equation show that
when T = 0, Q (t+1) = Q, that is, the next state is the same as the present state
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and no change occurs. When T = 1, Q (t+1) = Q', the state of the flip flop is
complemented.
(a) Logic diagram
(b) Graphic symbol
Figure 6.15 T flip flop
Table 6.4 Characteristic table of T flip flop
Q
T
Q (t+1)
0
0
1
1
0
1
0
1
0
1
1
0
Figure 6.16 Characteristic equation
Q (t+1) = TQ'+T'Q
(6.4)
Next the T flip flop is designed by using the characteristic equation.
The flip flop is constructed by using 4 majority gates and 2 inverters as shown
in Figure 6.17. The circuit has one input T and along with one control input
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Clock. The output Q of the flip flop is fed back to the input majority gate M2
and the complement of the output is fed back to the majority gate M1. The
output of M1 and M2 are combined with the Clock input by M3. Here the
gate M3 act as an OR gate to produce TQ'+T'Q. The gate M4 is used to form
a loop and to produce the desired characteristic Equation (6.4).
Figure 6.17 Design of T flip flop using majority gate
The QCA implementation of the T flip flop is shown in Figure
6.18. The QCA implementation requires 59 cells, with an area of 60,000 nm2.
In this implementation, the required number of cells is 50% reduced from the
previous implementations. This is achieved by using cell minimization
techniques.
Figure 6.18 Layout of T flip flop
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The performance analysis proposed SR, D, JK and T flop flops are
given in Table 6.5. The performance analyses of those circuits are compared
according to the complexity, area, and number of clock cycles and the
proposed designs are compared with existing majority gate method.
Table 6.5 Comparison of Flip flops
Previous structures
ComplexFlip
ity (No. of
Flops
QCA cells)
Area
Proposed structures
Delay Comple(No. of xity (No.
clock of QCA
cells)
cycles)
Area
Delay
(No. of
clock
cycles)
SR
7 8cells
300nm x 360nm
2
57 cells 240nm x 300nm
1
D
71 cells
360nm x 278nm
2
69 cells 337nm x 278nm
1
JK
92 cells
320nm x 360nm
2
46 cells 120nm x 300nm
1
T
97 cells
325nm x 380nm
2
59 cells 200nm x 300nm
1
6.3
DESIGN OF SHIFT REGISTERS IN QCA
A register is a group of flip flops suitable for storing binary
information. Each flip flop is a binary cell capable of storing one bit of
information. An n-bit register has a group of n flip flops and is capable of
storing any binary information containing n bits. The register is mainly used
for storing and shifting binary data entered into it from an external source. It
is a type of sequential circuit and an important building block used in digital
systems like multipliers, dividers, memories, microprocessors, etc.
A register capable of shifting binary information either to the right
or to the left is called a shift register. The shift register permits the stored data
to move from a particular location to some other location within the register.
In a shift register, the FFs are connected in such a way that the bits of a binary
number are entered into the shift register, shifted from one position to another
and finally shifted out.
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There are two methods of shifting the data. They are 1) Serial
shifting and 2) Parallel shifting. The serial shifting shifts one bit at a time for
each clock pulse in a serial fashion, beginning with either MSB (Most
Significant Bit ) or LSB (Least Significant Bit)For example, a 4-bit register
requires four clock pulses to shift a bit from the input to the output. In parallel
shifting operation, all the data get shifted simultaneously during a single clock
pulse. Hence it is faster than the serial shifting method. These two methods
can be used to shift data into a register and out of the register.
Shift registers are classified into the following four types based on
how binary information is entered or shifted out. They are
1. Serial in Serial out (SISO), 2.Serial in Parallel out (SIPO)
3. Parallel in Serial out (PISO) and 4.Parallel in Parallel out (PIPO)
The block diagrams of the four basic register types are shown in
Figure 6.19. The registers can be designed using flip flops (Morris Mano
1995). An n-bit shift register consists of n-flip flops and the required gates to
control the shift operation.
Figure 6.19 Shift register types
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Shift registers are used in digital systems for temporary storage of
information, data manipulation and transferring. In addition, they are used in
counting circuits, such as simple counters, variable modulo counters and
increment counters.
In this thesis, the Serial-in Serial-Out (SISO) and Serial-in ParallelOut (SIPO) 3-bit shift registers are designed using D and JK flip flops which
allow shifting in both directions: Left to Right or Right to Left. The results are
verified according to the truth table. The performance analyses of those
circuits are compared according to the complexity, area, and number of clock
cycles.
6.3.1
Serial in Serial Out Shift Register
This type of shift register accepts data serially, i.e. 1 bit at a time on
a single input line. It produces the stored information on its single output also
in serial form. Delay data by one clock time for each stage. It will store a bit
of data for each register. Data may be shifted left using shift left register or
shifted right using shift right register.
6.3.1.1
Shift right register
A shift right register can be built using JK flip flops or D flip flops
as shown in Figure 6.20 and Figure 6.21 respectively. A JK flip flop based
shift register requires connection of both J and K inputs. Input data are
connected to the J and K inputs of the rightmost (lowest order) flip flop. To
input a 1, i.e., J = 1 and K = 0; to input a 0, a 0 at J input, i.e., J = 0 and K = 1,
should be applied. When a clock pulse is applied, the data will be shifted bit
by bit to the right.
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Figure 6.20 SISO Shift right register using JK flip flop
Figure 6.21 SISO Shift right register using D flip flop
In the shift register using D flip flops; D input of the leftmost flip
flop is used as a serial input line. To input data 1, one should apply a 1 at D
input and to input data 0, a 0 at the D input should be applied.
Figure 6.22 Data shift in SISO Shift register
For example, consider that all stages are reset and a steady logical 1
is applied at the serial input line connected to stage A. A 1 is applied at the
serial input line i.e., at D input of the first flip flop (right most). When the first
clock pulse is applied, flip flop A is SET, thus storing the 1. Next a 1 is
applied to the serial input, making D=1 for flip flop A and D=1 for flip flop B
because D input of B is connected to the QA output.
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When second clock pulse occurs, the 1 on the data input is shifted
to flip flop A and 1 in flip flop A is shifted to flip flop B. The next 1 in the
binary number is now applied at the serial line and a clock pulse is applied.
This 1 is entered into flip flop A and the 1stored in flip flop A is shifted to flip
flop B and the 1stored in flip flop B is shifted to flip flop C. This completes
the serial entry of the 3-bit binary number into the shift register. The data in
each stage after each of the three shift pulses is shown in Table 6.6. The
logical-1 input enters into stage A and then shifts right to stage C after 3clock
pulses. This is graphically explained in Figure 6.22.
For a JK FF, the data bit to be shifted into the flip flop must be
present at the J and K inputs when the clock transition from low to high
occurs. Since the data bit is either a 1 or a 0, there are two cases:1. To shift a 0
into the FF, J=0 and K=1and 2. To shift a 1 into the FF, J=1 and K=0.
Table 6.6 Truth table of SISO shift right register
6.3.1.2
QCA implementation of Shift right register
The shift right register is constructed by using 3 flip flops (JK flip
flops or D flip flops).The flip flops are designed by using majority gates as
explained in previous section. The shift register is implemented by QCA cells
using flip flops implementation in section 6.2. It is a 3 bit shift register hence
3 flip flops are used in the design.
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In the JK flip flop design as shown in Figure 6.23, the shift register
is constructed by using 218 cells, with an area of 267,480 nm2 . The design of
each flip flop involves 4 clocking zones i.e, one clock cycle. Hence inputoutput delay for the shift register design required 3 clock cycles. In the shift
register using D flip flop as shown Figure6.24, design involves only 31 cells
and delay of 3 clock cycles. The area required for this QCA design is 31,640
nm2
.
Figure 6.23 Layout SISO Shift right register using JK flip flop
Figure 6.24 Layout SISO Shift right register using D flip flop
6.3.2
Shift left register
A shift left register can be built using JK flip flops and D flip flops
as shown in Figure 6.25 and Figure 6.26 respectively. The clock pulse is
applied to all the flip flops simultaneously. When the shift or clock pulse
occurs, each flip flop is set or reset according to the data at the respective flip
flop input. Thus, the input data bit at serial input line is entered into stage A
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by the first clock pulse. At the same time, the data of stage A is shifted into
stage B and so on for the following stages. For each shift pulse, data stored in
the register stage shifts to the left by one stage. New data is entered in to stage
A, whereas the data present in stage C are shifted out (to the left) for use by
some other shift register or other building block of digital system.
Figure 6.25 Schematic of SISO Shift left register using D flip flop
Figure 6.26 Schematic of SISO Shift left register using JK flip flop
For example, consider that all stages are reset and a steady logical 1
is applied at the serial input line connected to stage A. The data in each stage
after each of the three shift pulses is shown in Table 6.7. The logical 1 input
enters into stage A and then shifts left to stage C after 3clock pulses.
Table 6.7 Truth table of SISO shift left register
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6.3.2 .1
QCA implementation of Shift Left register
The shift left register can be implemented by QCA cells using JK
flip flops or D flip flops as shown in Figure 6.27 and Figure 6.28 respectively.
This QCA design is similar to the QCA implementation of shift right register
except the direction of data shifting. Hence there is no change in the number
of cells required, area and clock cycles.
Figure 6.27 Layout SISO Shift left register using JK flip flop
Figure 6.28 Layout SISO Shift left register using D flip flop
6.3.3
Serial in Parallel out Shift Register
A 3-bit serial in parallel out shift registers are shown on Figure 29
and Figure 30. It is constructed by using JK flip flops and D flip flops. It
consists of one serial input and outputs are taken from all the flip flops
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parallel. In this register, data is shifted in serially but shifted in parallel, it is
necessary to have all the data available at the outputs at the same time. Once
the data is stored, each bit appears on its respective output line and all the bits
are available simultaneously, rather than on a bit-by bit basis as with the serial
output.
Figure 6.29 Schematic of SISO Shift right register using D flip flop
Figure 6.30 Schematic of SIPO Shift right register using JK flip flop
6.3.3.1
QCA implementation of Serial in Parallel out Shift registers
The shift register can be built by QCA cells using JK flip flops and
D flip flops are shown in Figure 6.31 to Figure 6.34.The SIPO shift registers
are implemented by QCA cells in both directions of data shifting. It consists
of one serial input S through which the data is entered in to the register
serially. The outputs A, B and C are taken from the flip flops in parallel. It is a
3 bit shift register hence 3 flip flops are used in the design.
140
In the JK flip flop design, the shift register is constructed by using
218 cells, with an area of 267,480 nm2. This QCA design is similar to the
QCA implementation of serial in serial out shift register. Hence there is no
change in the number of cells required, area and clock cycles. In the shift
register using D flip flop design involves 37 cells and delay of 3 clock cycles.
The area required for this QCA design is 31,640 nm2.
Figure 6.31 Layout of SIPO Shift right register using JK flip flop
Figure 6.32 Layout of SIPO Shift left register using JK flip flop
Figure 6.33 Layout of SIPO Shift right register using D flip flop
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Figure 6.34 Layout of SIPO Shift left register using D flip flop
The performance analyses of the proposed shift registers are shown
in Table 6.8. The performance analyses of those circuits are compared
according to the complexity, area, and number of clock cycles.
Table 6.8 Comparison of Shift Registers
Shift Register
Complexity
Area
Delay
(clock cycles)
SISO (D FF)
31 cells
565nm x 56nm
3
SIPO(D FF)
37 cells
565nm x 56nm
3
SISO/SIPO (JK FF)
218 cells
743nm x 360nm
3
6.4
DESIGN OF COUNTERS IN QCA
A counter is a sequential circuit consisting of set of flip flops
connected in a suitable manner to count the sequence of the input pulses. The
counters can be broadly classified into 3 types as follows:
1. Asynchronous and Synchronous counters
2. Single and multimode counters
3. Modulus counters
An asynchronous or ripple counter can be constructed using
minimum hardware. In an asynchronous counter, each flip-flop is triggered by
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the output from the previous flip-flop which limits its speed of operation. The
settling time in asynchronous counters, is the cumulative sum of the
individual settling times of flip-flops. It is also called a serial counter. In
synchronous counters, the speed limitation of ripple counter is overcome by
applying clock pulses simultaneously to all the flip flops which leads to the
settling time of the counter being equal to the propagation delay of a single
flip-flop. Hence synchronous counters also are also called parallel counters.
Single mode counters operate in single mode, i.e., it counts either in the Up
mode or in the DOWN mode, whereas multimode counters operate in both
UP and DOWN modes. Modulus counters are defined based on the number of
states they are capable of counting. For example, a MOD 10 counter has 10
states.
Counters are fundamental components of digital systems. Digital
counters find wide application like pulse counting, frequency division, time
measurement and control and timing operations.
In this thesis, the 4-bit ring and Johnson counters are designed
using D flip flops. The 3-bit up counter is designed using JK flip flops which
counts upward from 0 to 7. The performance analyses of those circuits are
compared according to the complexity, area, and number of clock cycles.
6.4.1
Design of Ring Counter
Ring counters are implemented using shift registers. It is essentially
a circulating shift register connected so that the last flip-flop shifts its value
into the first flip-flop. There is usually only a single 1 circulating in the
register, as long as clock pulses are applied.
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Figure 6.35 Ring counter using D flip flop
Table 6.9 Truth table of Ring counter
In the diagram as shown in Figure 6.35, assuming a starting state of
Q0 = 1 and Q1= Q2 = Q3 = 0. At the first pulse, the 1 shift from Q0 to Q1 and
the counter is in the 0100 state. The next pulse produces the 0010 state and
the third, 0001. At the fourth pulse, the 1 at Q3 is transferred back to Q0,
resulting in the 1000 state, which is the initial state. Subsequent pulses will
cause the sequence to repeat, hence the name ring counter. This operation is
shown in Table 6.9.
The ring counter above functions as a MOD-4 counter since it has
four distinct states and each flip-flop output waveform has a frequency equal
to one-fourth of the clock frequency. A ring counter can be constructed for
any MOD number. A MOD-N ring counter will require N flip-flops
connected in the arrangement as the diagram above.
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A ring counter requires more flip-flops than a binary counter for the
same MOD number. For example, a MOD-8 ring counter requires 8 flip-flops
while a MOD-8 binary counter only requires 3 (23 = 8). So if a ring counter is
less efficient in the use of flip-flops than a binary counter, why do we still
need ring counters? One main reason is because ring counters are much easier
to decode. In fact, ring counters can be decoded without the use of logic gates.
The decoding signal is obtained at the output of its corresponding flip-flop.
Mehdi Askari et al (2008) have designed ring counter using QCA cells.
For the ring counter to operate properly, it must start with only one
flip-flop in the 1 state and all the others at 0. Since it is not possible to expect
the counter to come up to this state when power is first applied to the circuit,
it is necessary to preset the counter to the required starting state before the
clock pulses are applied. One way to do this is to apply a pulse to the
PRESET input of one of the flip-flops and the CLEAR inputs of all the others.
This will place a single 1 in the ring counter.
6.4.2
QCA Implementation of Ring Counter
The flip flop is a significant part of the counters. In fact, a D-type
flip flop can be constructed by a QCA binary wire with four clocking zones.
An optimal design can be attained with attaching four optimal D flip flops as
well as using an appropriate feedback being able to transmit output signal to
input at every clock cycle.
Figure 6.36 Layout of Ring counter using D flip flop
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The 4-bit QCA ring counter design is shown in Figure 6.36. Every
different subsequent four clock zones is repeated alternatively and operates as
a D-FF, i.e., the clocked binary wire operates as a D FF. It is necessary that
D-FF3 output shift to D-FF0 after every clock cycle. So, feedback path only
includes a complete clock cycle.
There is a majority gate at the circuit input. Since one of its inputs
has logic “1”, majority gate is operated as a logic OR function. The “set”
input, for the purpose of the initial turn on the circuit has been connected to
the first flip-flop. The total number of cells required to implement a ring
counter is 82, with an area of 84000 nm2. This is achieved by using cell
minimization techniques.
6.4.3
Johnson Counter using DFF
The Johnson counter, also known as the twisted-ring counter, is
exactly the same as the ring counter except that the inverted output of the last
flip-flop is connected to the input of the first flip-flop.
This counter circulates a stream of ones followed by zeros around
the ring. For example, a four bit shift counter with initial value of the counter
of 0000 is followed by the repeating pattern 0000, 1000, 1100, 1110, 1111,
0111, 0011, 0001, 0000.
Figure 6.37 Johnson counter using D flip flop
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Table 6.10 Truth table of Johnson counter
Shift Pulse Q0
Q1
Q2
Q3
0
0
0
0
0
1
1
0
0
0
2
1
1
0
0
3
1
1
1
0
4
1
1
1
1
The Johnson counter works in the following way: Take the initial
state of the counter to be 0000. On the first clock pulse, the inverse of the last
flip-flop will be fed into the first flip-flop, producing the state 1000. On the
second clock pulse, since the last flip-flop is still at level 0, another 1 will be
fed into the first flip-flop, giving the state 1100. On the third clock pulse, the
state 1110 is produced and on the fourth clock pulse, the state 1111 is
produced. On the fifth clock pulse, the inverse of the last flip-flop, now a 0,
will be shifted to the first flip-flop, giving the state 0111. On the sixth and
seventh clock pulse, using the same reasoning, we will get the state’s 0011
and 0001. On the ninth clock pulse, we will get the states 0000, which is the
initial state again. Hence, this Johnson counter has sixth distinct states: 0000,
1000, 1100, 1110, 1111,0111, 0011 and 0001, and the sequence is repeated so
long as there is input pulse. Thus this is a MOD-8 Johnson counter.
The MOD number of a Johnson counter is twice the number of flipflops. In the example above, four flip-flops were used to create the MOD-8
Johnson counter. So for a given MOD number, a Johnson counter requires
only half the number of flip-flops needed for a ring counter. However, a
Johnson counter requires decoding gates whereas a ring counter doesn't. As
with the binary counter, one logic gate (AND gate) is required to decode each
state, but with the Johnson counter, each gate requires only two inputs,
regardless of the number of flip-flops in the counter. Note that we are
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comparing with the binary counter using the speed up technique discussed
above. The reason for this is that for each state, two of the N flip-flops used
will be in a unique combination of states.
Recirculating a single one, a ring counter divides the input clock by
a factor equal to its number of stages whereas a Johnson counter divides by a
factor equal to twice the number of stages. For example, a four stage Johnson
counter divides by eight while a four stage Ring counter divides by four.
Latching is done by using four clocking arrangement. Input is delivered to the
output after one complete clock cycle delay. The four bit shift counter and the
clocking of D flip flop is shown in Figure 6.37. The truth table of Shift or
Johnson Counter is shown given by Table 6.10.
A Johnson counters represent a middle ground between ring
counters and binary counters. A Johnson counter requires fewer flip-flops
than a ring counter but generally more than a binary counter; it has more
decoding circuitry than a ring counter but less than a binary counter. Thus, it
sometimes represents a logical choice for certain applications. Chakrabarty et
al (2011) have proposed QCA design of Johnson counter.
6.4.4
QCA implementation of Johnson Counter
The 4-bit QCA implementation of Johnson counter design is shown
in Figure 6.38. It is constructed from Ring counter as Figure 6.36. In this
counter the inverted output of last flip flop is connected to the input of first
flip flop. This is achieved by using QCA inverter which is indicated by a
circle in the QCA layout as shown below.
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Figure 6.38 Layout of Johnson counter using D flip flop
Majority gate is used at the input for OR function for logic 1 to
initial turn on the circuit with the set input which is connected to the first flip
flop. Once the set input is activated the circuit operates and the outputs are
generated accordingly. In this work 93 cells are used, each of size 20nm x
20nm and area 984 nm2 while the dot size is 5 nm, and effective area is
96,000 nm2.
6.4.5
Design of Up Counter in QCA
A synchronous binary counter counts from 0 to 2N-1, where N is
the number of bits/flip-flops in the counter. Each flip-flop is used to represent
one bit. The flip-flop in the lowest-order position is complemented/toggled
with every clock pulse and a flip-flop in any other position is complemented
on the next clock pulse provided all the bits in the lower-order positions are
equal to 1.
Take for example A4 A3 A2 A1 = 0011. On the next count, A4 A3 A2 A1
= 0100. A1, the lowest-order bit, is always complemented. A2 is
complemented because all the lower-order positions (A1 only in this case)
are 1's. A3 is also complemented because all the lower-order positions, A2
and A1 are 1's. But A4 is not complemented the lower-order positions,
A3 A2 A1 = 011, do not give an all 1 condition.
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To implement a synchronous counter, we need a flip-flop for every
bit and an AND gate for every bit except the first and the last bit. The diagram
below shows the implementation of a 3-bit synchronous up-counter.
Figure 6.39 Up counter using JK flip flops
Table 6.11 Truth table of up counter
6.4.6
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
QCA implementation of Up Counter in QCA
In conventional sequential circuits, any sequential circuit can be
modelled as a single finite state machine (FSM) consisting of combinational
logic and flip-flops. This model can also be used for QCA implementations of
sequential logic. However, there exists an essential difference between
150
conventional and QCA sequential circuits. In a conventional sequential
circuit, the clock signal controls only flip-flops. In a QCA sequential circuit,
the clock signal controls not only flip-flops, but also the combinational logic.
This difference brings many difficulties in QCA counter designs. Huang et al
(2007) have worked on the design of QCA counters.
In this counter, the clock inputs of all the flip flops are connected
together so that the input clock signal is applied simultaneously to each flip
flop. Only the J and K inputs of FF1 is permanently connected to +1 while the
J and K inputs of the other flip flops are driven by some combination of flip
flop outputs. The J and K inputs of FF2 is connected with (A ) output of
FF1; the J and K inputs of FF3 is connected with AND operated output of A
and B.
Figure 6.40 Layout of Up counter using JK flip flops
The 3-bit QCA up counter design is shown in Figure 6.40. It is
constructed by using JK flip flop. It is a 3 bit counter hence it consists of 3 JK
flip flops. Here the Majority gate is designed to perform AND operation of
the output of flip flop 1 and flip flop 2. This design uses 218 QCA cells and
span over 12 clocking zones from input to output. The input-output delay of
the circuit is therefore 3 clock cycles. The area required for this QCA design
is 267,480 nm2.
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The performance analyses of proposed counters are shown in
Table 6.12. The performance analyses of those circuits are compared
according to the complexity, area, and number of clock cycles. The proposed
designs are compared with existing majority gate method.
Table 6.12 Comparison of counters
Previous Structures
Circuit
Name
Proposed structures
Delay
(clock
cycles)
Complexity
Area
Complexity
Area
Ring
Counter
86 cells
750nm x
120nm
82 cells
700nm x
120nm
5
Johnson
Counter
99 cells
860nm x
120nm
93 cells
800nm x
120nm
5
Up
Counter
221 cells
800nm x
340nm
218 cells
743nm x
340nm
4
The length of the structure increases as the number of cells
increases. But the width of the structure remains the same. Therefore the
difference in the number of cells is not proportional to the area.
6.5
RESULTS AND DISCUSSION
The design of QCA sequential circuits is quite different from the
design of traditional CMOS sequential circuits because of their different
clocking schemes. The four types of flip flops have implemented and
simulated here. The simulated results of all these flip flops are shown from
Figure 6.41to Figure 6.44. The simulation results obtained with QCADesigner
ver.2.0.3 verifies the functionality of the proposed flip flops. The delay for the
each flip flop is 1 clock cycle. Therefore, each circuit has four clocking zones.
Initially clock 0 is used to get the inputs. Clock 1 is used to route inputs for
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majority gate logic, clock 2 is used for finding majority logic and clock 3 is
used to compute output. The output is available at clock 0 again.
Figure 6.41 Simulation Result of SR flip flop
Figure 6.42 Simulation Result of D flip flop
Figure 6.43 Simulation Result of JK flip flop
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Figure 6.44 Simulation Result of T flip flop
The simulated results of 3 bit serial in serial out and serial in
parallel out shift registers are shown in Figure 6.45 and Figure 6.46. The shift
registers are constructed by 3 flip flops. Hence 3clock cycles or 12 clock
zones are required to transmit the data from input to the output. In SISO shift
register, at each clock cycle single bit is shifted to next flip flop either right or
left direction as shown in Figure 6.45. But the SIPO shift register, all the bits
are available simultaneously as shown in Figure 6.46.
Figure 6.45 Simulation Result of SISO shift register
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Figure 6.46 Simulation Result of SIPO shift register
The simulated result of 4-bit QCA ring counter is shown in
Figure 6.47. The counter is constructed by D flip flops. The D flip flop is
designed by a QCA binary wire as shown in Figure 6.33. It is 4 bit counter
hence it consists of 4 D flip flops. Therefore, 4 clock cycles are needed for the
design of 4 flip flops and 1 clock cycle is used for feedback path. Hence 5
clock cycles are required for the proper operation of the circuit. The “set”
input, is used to turn on the circuit initially which is connected to the first flip
flop. The “Set” input waveform and circuit outputs are shown in Figure 6.47.
In this figure, the rotation of bit “1” is indicated properly. With QCADesigner
ver.2.0.3, the circuit functionality is verified and this design has 82 cells and
an area of approximately 84000 nm2.
Figure 6.47 Simulation Result of Ring counter
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The simulated result of 4-bit QCA Johnson counter is shown in
Figure 6.48. Similar to ring counter it is also constructed by D flip flops. The
D flip flop is designed by a QCA binary wire as shown in Figure 6.33. The
delay for the circuit is 5 clock cycles which is required to produce the output.
Once the set input is activated the circuit operates and the outputs are
generated accordingly.
Figure 6.48 Simulation Result of Johnson counter
The proposed QCA up counter has been designed and simulated
using the QCADesigner tool. This tool allows users to do a custom layout and
then verify QCA circuit functionality by simulations. The simulated result of
3-bit QCA up counter is shown in Figure 6.49. This counter is constructed by
JK flip flops as shown in Figure 6.14. The delay for the circuit is 4 clock
cycles which is required to produce the output. Here the 3 clock cycles are
used to design the 3 JK flip flops and 1 clock cycle is used for combinational
logic (MG) design.
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Figure 6.49 Simulation Result of Up counter
6.5
CONCLUSION
In this chapter the different flip flops have been designed using
majority gates. The layouts and functionality checks were done using
QCADesigner and the designs are compared according to the complexity, area
and number of clock cycles. The operations of these circuits have been verified
according to the truth table. The proposed layouts are significantly smaller
than the same circuits using standard CMOS technology as well as the
existing circuits in QCA. The different types of shift registers and counters
have been designed and analyzed with the help of proposed D and JK flip
flops. It is shown that clocking requirements, number of zones, as well as the
underlying CMOS circuitry complexity are significantly reduced compared
with previous QCA circuits.