The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
Problem Set 6
solution part 2
Design of Clocked Sequential Circuits
Discussion: 20/11/2015 – 26/11/2015
Design Steps :
1) Define inputs ,outputs and possible states from the verbal description madn assign binary values for inputs
,outputs and states .
2) State Diagram
3) State Table
4) Get Equations From K-Map
5) Draw the circuit
You need to know FlipFlops exciation Tables . :
Page 1
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
Exercise 6-2: (Problem 5.16)
Design a sequential circuit with two D flip-flops A and B and one input x_in.
a) When the x_in = 0, the state of the circuit remains the same. When x_in = 1, the circuit goes
through the state transitions from 00 to 01, to 11, to 10, back to 00, and repeats.
Page 2
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
b) When the x_in = 0, the state of the circuit remains the same. When x_in = 1, the circuit goes
through the state transitions from 00 to 11, to 01, to 10, back to 00, and repeats.
Exercise 6-3: (Problem 5.18)
Design a sequential circuit with two JK flip-flops A and B and two inputs E and F. If E = 0, the circuit
remains in the same state regardless of the value of F. When E = 1 and F = 1, the circuit goes through the
state transitions from 00 to 01, to 10, to 11, back to 00, and repeats. When E = 1 and F = 0, the circuit
goes through the state transitions from 00 to 11, to 10, to 01, back to 00 and repeats.
Solution :
-We first get the values of Next States from Verbal description given
-T hen Use Excitation Table to get Flip-Flop inputs values
-Use Kmap to get equation for Ja, Ka,Jb,Kb
-Design your circuit by drawing 2 JK fliplfops and connecting input equations
Page 3
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Present State
A
B
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Ja
Jb

Inputs
E
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
F
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Media Engineering and Technology
Winter 2015
Next State
Anext
Bnext
0
0
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
Flip Flop inputs
Ja
Ka
0
x
0
x
1
x
0
x
0
x
0
x
0
x
1
X
X
0
X
0
X
1
x
0
x
0
x
0
x
0
x
1
Jb
0
0
1
1
x
x
x
x
0
0
1
1
x
x
x
x
Kb
x
x
x
x
0
0
1
1
X
X
X
x
0
0
1
1
KA
Kb
Draw the two Jk flip- flops using these equations
Page 4
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
Exercise 6-4: (Problem 5.19)
A sequential circuit has three flip-flops A, B and C; one input x_in; and one output y_out. The state
diagram is shown in the figure below. The circuit is to be designed by treating the unused states as don’t
care conditions. Analyze the circuit obtained from the design to determine the effect of the unused
states.
Page 5
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
Notice here the unused states are don’t
cares
*Draw the logic diagream of 3 Dflip flops
Page 6
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
Exercise 6-6: (Problem 5.20)
Design the sequential circuit specified by the state diagram of the figure below, using T flip-flops.
Page 7
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
*Draw the logic diagram of two T-Flip Flops
Exercise 6-7
Design FSM that detects sequence 1011 and outputs 1 when it is found . overlapping is allowed .
a) Using Moore FSM
b) Using Mealy FSM
Solution :
a) Moore
-Input is 1 bit let it be x
-Output is 1 bit let it be z
-States are :
000:Nthg found from sequence
001: first “1” found
010:”10”found
011:”101” found
100:”1011 “ all sequence found
S0
[0]
S1
[0]
[]0
a
[]0
a
S2
[0]
*We have 5 states ,we need 3 bits to write binary names of each state
S4
[1]
[]0
a
[]0
a
S3
[0]
Page 8
[]0
a
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
We have 2 differents outputs either Z=0 , or Z =1 ,Since each of them has its own independent state where it can be
written  Moore Design
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
*Anxt = BCX
*Z=AB’C’ --doesn’t need kmap
*Bnxt
Anxt
0
0
0
0
0
0
0
1
0
0
x
x
x
x
x
x
Bnxt
0
0
1
0
0
1
1
0
1
0
x
x
x
x
x
x
Cnxt
0
1
0
1
0
1
0
0
0
1
x
x
x
x
x
x
Z
0
0
0
0
0
0
0
0
1
1
x
x
x
x
x
x
cnxt
Page 9
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Media Engineering and Technology
Winter 2015
-Draw the circuit
Since the state is written in 3 bits , therefore we need 3 flipflops t hold the state ,each holding on Q =(1 bit )
Note :
IN Moore FSM ,output is directly dependent only on present state [outputs of flipflops)
Outputs change only with positive edge of clock
(B) Mealy Design
When some outputs do not have their own independent states in the state diagram ,this this is a
Mealy FSM,
*if we remove state S4 ,output [z=1] will not have its own state  Mealy Machine
*Not all outputs have their own states , then we write on arrows
only 4 states  2 bits to write their binary names .
S0
-States are :
 00: S0
 01: S1
 10 :S2
 11: S3
[]0
a
S1
[]0
a
S2
[]0
a
S3
[]0
a
Page
10
The German University in Cairo
CSEN 605: Digital System Design
Dr.Mohamed Elmahdy
Eng.Yasmin
Mohamed
Present State
Media Engineering and Technology
Winter 2015
Input
Nxt State
Output
B
C
x
Bnxt
Cnxt
Z
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
1
0
1
1
*Get equations From K-Map :
Z=BCX
Bnxt
Cnxt
*Draw Circuit
* NOTE : In Mealy FSM , output has direct relation with both input & present state .Since input can
change at anytime therefore , output also can change at anytime not necessarily with positive edge .
Page
11